tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2017 Texas Instruments, Inc.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13#ifndef __DT_BINDINGS_CLK_AM4_H
14#define __DT_BINDINGS_CLK_AM4_H
15
16#define AM4_CLKCTRL_OFFSET 0x20
17#define AM4_CLKCTRL_INDEX(offset) ((offset) - AM4_CLKCTRL_OFFSET)
18
19/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
20
21/* l4_wkup clocks */
22#define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120)
23#define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
24#define AM4_WKUP_M3_CLKCTRL AM4_CLKCTRL_INDEX(0x228)
25#define AM4_COUNTER_32K_CLKCTRL AM4_CLKCTRL_INDEX(0x230)
26#define AM4_TIMER1_CLKCTRL AM4_CLKCTRL_INDEX(0x328)
27#define AM4_WD_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x338)
28#define AM4_I2C1_CLKCTRL AM4_CLKCTRL_INDEX(0x340)
29#define AM4_UART1_CLKCTRL AM4_CLKCTRL_INDEX(0x348)
30#define AM4_SMARTREFLEX0_CLKCTRL AM4_CLKCTRL_INDEX(0x350)
31#define AM4_SMARTREFLEX1_CLKCTRL AM4_CLKCTRL_INDEX(0x358)
32#define AM4_CONTROL_CLKCTRL AM4_CLKCTRL_INDEX(0x360)
33#define AM4_GPIO1_CLKCTRL AM4_CLKCTRL_INDEX(0x368)
34
35/* mpu clocks */
36#define AM4_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
37
38/* gfx_l3 clocks */
39#define AM4_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
40
41/* l4_rtc clocks */
42#define AM4_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
43
44/* l4_per clocks */
45#define AM4_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
46#define AM4_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28)
47#define AM4_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30)
48#define AM4_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40)
49#define AM4_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50)
50#define AM4_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58)
51#define AM4_VPFE0_CLKCTRL AM4_CLKCTRL_INDEX(0x68)
52#define AM4_VPFE1_CLKCTRL AM4_CLKCTRL_INDEX(0x70)
53#define AM4_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78)
54#define AM4_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80)
55#define AM4_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88)
56#define AM4_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90)
57#define AM4_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0)
58#define AM4_GPMC_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
59#define AM4_MCASP0_CLKCTRL AM4_CLKCTRL_INDEX(0x238)
60#define AM4_MCASP1_CLKCTRL AM4_CLKCTRL_INDEX(0x240)
61#define AM4_MMC3_CLKCTRL AM4_CLKCTRL_INDEX(0x248)
62#define AM4_QSPI_CLKCTRL AM4_CLKCTRL_INDEX(0x258)
63#define AM4_USB_OTG_SS0_CLKCTRL AM4_CLKCTRL_INDEX(0x260)
64#define AM4_USB_OTG_SS1_CLKCTRL AM4_CLKCTRL_INDEX(0x268)
65#define AM4_PRUSS_CLKCTRL AM4_CLKCTRL_INDEX(0x320)
66#define AM4_L4_LS_CLKCTRL AM4_CLKCTRL_INDEX(0x420)
67#define AM4_D_CAN0_CLKCTRL AM4_CLKCTRL_INDEX(0x428)
68#define AM4_D_CAN1_CLKCTRL AM4_CLKCTRL_INDEX(0x430)
69#define AM4_EPWMSS0_CLKCTRL AM4_CLKCTRL_INDEX(0x438)
70#define AM4_EPWMSS1_CLKCTRL AM4_CLKCTRL_INDEX(0x440)
71#define AM4_EPWMSS2_CLKCTRL AM4_CLKCTRL_INDEX(0x448)
72#define AM4_EPWMSS3_CLKCTRL AM4_CLKCTRL_INDEX(0x450)
73#define AM4_EPWMSS4_CLKCTRL AM4_CLKCTRL_INDEX(0x458)
74#define AM4_EPWMSS5_CLKCTRL AM4_CLKCTRL_INDEX(0x460)
75#define AM4_ELM_CLKCTRL AM4_CLKCTRL_INDEX(0x468)
76#define AM4_GPIO2_CLKCTRL AM4_CLKCTRL_INDEX(0x478)
77#define AM4_GPIO3_CLKCTRL AM4_CLKCTRL_INDEX(0x480)
78#define AM4_GPIO4_CLKCTRL AM4_CLKCTRL_INDEX(0x488)
79#define AM4_GPIO5_CLKCTRL AM4_CLKCTRL_INDEX(0x490)
80#define AM4_GPIO6_CLKCTRL AM4_CLKCTRL_INDEX(0x498)
81#define AM4_HDQ1W_CLKCTRL AM4_CLKCTRL_INDEX(0x4a0)
82#define AM4_I2C2_CLKCTRL AM4_CLKCTRL_INDEX(0x4a8)
83#define AM4_I2C3_CLKCTRL AM4_CLKCTRL_INDEX(0x4b0)
84#define AM4_MAILBOX_CLKCTRL AM4_CLKCTRL_INDEX(0x4b8)
85#define AM4_MMC1_CLKCTRL AM4_CLKCTRL_INDEX(0x4c0)
86#define AM4_MMC2_CLKCTRL AM4_CLKCTRL_INDEX(0x4c8)
87#define AM4_RNG_CLKCTRL AM4_CLKCTRL_INDEX(0x4e0)
88#define AM4_SPI0_CLKCTRL AM4_CLKCTRL_INDEX(0x500)
89#define AM4_SPI1_CLKCTRL AM4_CLKCTRL_INDEX(0x508)
90#define AM4_SPI2_CLKCTRL AM4_CLKCTRL_INDEX(0x510)
91#define AM4_SPI3_CLKCTRL AM4_CLKCTRL_INDEX(0x518)
92#define AM4_SPI4_CLKCTRL AM4_CLKCTRL_INDEX(0x520)
93#define AM4_SPINLOCK_CLKCTRL AM4_CLKCTRL_INDEX(0x528)
94#define AM4_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x530)
95#define AM4_TIMER3_CLKCTRL AM4_CLKCTRL_INDEX(0x538)
96#define AM4_TIMER4_CLKCTRL AM4_CLKCTRL_INDEX(0x540)
97#define AM4_TIMER5_CLKCTRL AM4_CLKCTRL_INDEX(0x548)
98#define AM4_TIMER6_CLKCTRL AM4_CLKCTRL_INDEX(0x550)
99#define AM4_TIMER7_CLKCTRL AM4_CLKCTRL_INDEX(0x558)
100#define AM4_TIMER8_CLKCTRL AM4_CLKCTRL_INDEX(0x560)
101#define AM4_TIMER9_CLKCTRL AM4_CLKCTRL_INDEX(0x568)
102#define AM4_TIMER10_CLKCTRL AM4_CLKCTRL_INDEX(0x570)
103#define AM4_TIMER11_CLKCTRL AM4_CLKCTRL_INDEX(0x578)
104#define AM4_UART2_CLKCTRL AM4_CLKCTRL_INDEX(0x580)
105#define AM4_UART3_CLKCTRL AM4_CLKCTRL_INDEX(0x588)
106#define AM4_UART4_CLKCTRL AM4_CLKCTRL_INDEX(0x590)
107#define AM4_UART5_CLKCTRL AM4_CLKCTRL_INDEX(0x598)
108#define AM4_UART6_CLKCTRL AM4_CLKCTRL_INDEX(0x5a0)
109#define AM4_OCP2SCP0_CLKCTRL AM4_CLKCTRL_INDEX(0x5b8)
110#define AM4_OCP2SCP1_CLKCTRL AM4_CLKCTRL_INDEX(0x5c0)
111#define AM4_EMIF_CLKCTRL AM4_CLKCTRL_INDEX(0x720)
112#define AM4_DSS_CORE_CLKCTRL AM4_CLKCTRL_INDEX(0xa20)
113#define AM4_CPGMAC0_CLKCTRL AM4_CLKCTRL_INDEX(0xb20)
114
115/* XXX: Compatibility part end. */
116
117/* l3s_tsc clocks */
118#define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120
119#define AM4_L3S_TSC_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_TSC_CLKCTRL_OFFSET)
120#define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
121
122/* l4_wkup_aon clocks */
123#define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228
124#define AM4_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_AON_CLKCTRL_OFFSET)
125#define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228)
126#define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
127
128/* l4_wkup clocks */
129#define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220
130#define AM4_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_CLKCTRL_OFFSET)
131#define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
132#define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328)
133#define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338)
134#define AM4_L4_WKUP_I2C1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x340)
135#define AM4_L4_WKUP_UART1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x348)
136#define AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x350)
137#define AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x358)
138#define AM4_L4_WKUP_CONTROL_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x360)
139#define AM4_L4_WKUP_GPIO1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x368)
140
141/* mpu clocks */
142#define AM4_MPU_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
143
144/* gfx_l3 clocks */
145#define AM4_GFX_L3_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
146
147/* l4_rtc clocks */
148#define AM4_L4_RTC_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
149
150/* l3 clocks */
151#define AM4_L3_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
152#define AM4_L3_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28)
153#define AM4_L3_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30)
154#define AM4_L3_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40)
155#define AM4_L3_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50)
156#define AM4_L3_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58)
157#define AM4_L3_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78)
158#define AM4_L3_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80)
159#define AM4_L3_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88)
160#define AM4_L3_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90)
161#define AM4_L3_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0)
162
163/* l3s clocks */
164#define AM4_L3S_CLKCTRL_OFFSET 0x68
165#define AM4_L3S_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_CLKCTRL_OFFSET)
166#define AM4_L3S_VPFE0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x68)
167#define AM4_L3S_VPFE1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x70)
168#define AM4_L3S_GPMC_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x220)
169#define AM4_L3S_MCASP0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x238)
170#define AM4_L3S_MCASP1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x240)
171#define AM4_L3S_MMC3_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x248)
172#define AM4_L3S_QSPI_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x258)
173#define AM4_L3S_USB_OTG_SS0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x260)
174#define AM4_L3S_USB_OTG_SS1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x268)
175
176/* pruss_ocp clocks */
177#define AM4_PRUSS_OCP_CLKCTRL_OFFSET 0x320
178#define AM4_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM4_PRUSS_OCP_CLKCTRL_OFFSET)
179#define AM4_PRUSS_OCP_PRUSS_CLKCTRL AM4_PRUSS_OCP_CLKCTRL_INDEX(0x320)
180
181/* l4ls clocks */
182#define AM4_L4LS_CLKCTRL_OFFSET 0x420
183#define AM4_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM4_L4LS_CLKCTRL_OFFSET)
184#define AM4_L4LS_L4_LS_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x420)
185#define AM4_L4LS_D_CAN0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x428)
186#define AM4_L4LS_D_CAN1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x430)
187#define AM4_L4LS_EPWMSS0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x438)
188#define AM4_L4LS_EPWMSS1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x440)
189#define AM4_L4LS_EPWMSS2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x448)
190#define AM4_L4LS_EPWMSS3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x450)
191#define AM4_L4LS_EPWMSS4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x458)
192#define AM4_L4LS_EPWMSS5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x460)
193#define AM4_L4LS_ELM_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x468)
194#define AM4_L4LS_GPIO2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x478)
195#define AM4_L4LS_GPIO3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x480)
196#define AM4_L4LS_GPIO4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x488)
197#define AM4_L4LS_GPIO5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x490)
198#define AM4_L4LS_GPIO6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x498)
199#define AM4_L4LS_HDQ1W_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4a0)
200#define AM4_L4LS_I2C2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4a8)
201#define AM4_L4LS_I2C3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4b0)
202#define AM4_L4LS_MAILBOX_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4b8)
203#define AM4_L4LS_MMC1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4c0)
204#define AM4_L4LS_MMC2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4c8)
205#define AM4_L4LS_RNG_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4e0)
206#define AM4_L4LS_SPI0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x500)
207#define AM4_L4LS_SPI1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x508)
208#define AM4_L4LS_SPI2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x510)
209#define AM4_L4LS_SPI3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x518)
210#define AM4_L4LS_SPI4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x520)
211#define AM4_L4LS_SPINLOCK_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x528)
212#define AM4_L4LS_TIMER2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x530)
213#define AM4_L4LS_TIMER3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x538)
214#define AM4_L4LS_TIMER4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x540)
215#define AM4_L4LS_TIMER5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x548)
216#define AM4_L4LS_TIMER6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x550)
217#define AM4_L4LS_TIMER7_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x558)
218#define AM4_L4LS_TIMER8_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x560)
219#define AM4_L4LS_TIMER9_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x568)
220#define AM4_L4LS_TIMER10_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x570)
221#define AM4_L4LS_TIMER11_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x578)
222#define AM4_L4LS_UART2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x580)
223#define AM4_L4LS_UART3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x588)
224#define AM4_L4LS_UART4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x590)
225#define AM4_L4LS_UART5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x598)
226#define AM4_L4LS_UART6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5a0)
227#define AM4_L4LS_OCP2SCP0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5b8)
228#define AM4_L4LS_OCP2SCP1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5c0)
229
230/* emif clocks */
231#define AM4_EMIF_CLKCTRL_OFFSET 0x720
232#define AM4_EMIF_CLKCTRL_INDEX(offset) ((offset) - AM4_EMIF_CLKCTRL_OFFSET)
233#define AM4_EMIF_EMIF_CLKCTRL AM4_EMIF_CLKCTRL_INDEX(0x720)
234
235/* dss clocks */
236#define AM4_DSS_CLKCTRL_OFFSET 0xa20
237#define AM4_DSS_CLKCTRL_INDEX(offset) ((offset) - AM4_DSS_CLKCTRL_OFFSET)
238#define AM4_DSS_DSS_CORE_CLKCTRL AM4_DSS_CLKCTRL_INDEX(0xa20)
239
240/* cpsw_125mhz clocks */
241#define AM4_CPSW_125MHZ_CLKCTRL_OFFSET 0xb20
242#define AM4_CPSW_125MHZ_CLKCTRL_INDEX(offset) ((offset) - AM4_CPSW_125MHZ_CLKCTRL_OFFSET)
243#define AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL AM4_CPSW_125MHZ_CLKCTRL_INDEX(0xb20)
244
245#endif