tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
15#include "phy-qcom-ufs-qmp-14nm.h"
16
17#define UFS_PHY_NAME "ufs_phy_qmp_14nm"
18#define UFS_PHY_VDDA_PHY_UV (925000)
19
20static
21int ufs_qcom_phy_qmp_14nm_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
22 bool is_rate_B)
23{
24 int tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A);
25 int tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);
26 int err;
27
28 err = ufs_qcom_phy_calibrate(ufs_qcom_phy, phy_cal_table_rate_A,
29 tbl_size_A, phy_cal_table_rate_B, tbl_size_B, is_rate_B);
30
31 if (err)
32 dev_err(ufs_qcom_phy->dev,
33 "%s: ufs_qcom_phy_calibrate() failed %d\n",
34 __func__, err);
35 return err;
36}
37
38static
39void ufs_qcom_phy_qmp_14nm_advertise_quirks(struct ufs_qcom_phy *phy_common)
40{
41 phy_common->quirks =
42 UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;
43}
44
45static int ufs_qcom_phy_qmp_14nm_init(struct phy *generic_phy)
46{
47 struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
48 bool is_rate_B = false;
49 int ret;
50
51 if (phy_common->mode == PHY_MODE_UFS_HS_B)
52 is_rate_B = true;
53
54 ret = ufs_qcom_phy_qmp_14nm_phy_calibrate(phy_common, is_rate_B);
55 if (!ret)
56 /* phy calibrated, but yet to be started */
57 phy_common->is_started = false;
58
59 return ret;
60}
61
62static int ufs_qcom_phy_qmp_14nm_exit(struct phy *generic_phy)
63{
64 return 0;
65}
66
67static
68int ufs_qcom_phy_qmp_14nm_set_mode(struct phy *generic_phy,
69 enum phy_mode mode, int submode)
70{
71 struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
72
73 phy_common->mode = PHY_MODE_INVALID;
74
75 if (mode > 0)
76 phy_common->mode = mode;
77
78 return 0;
79}
80
81static
82void ufs_qcom_phy_qmp_14nm_power_control(struct ufs_qcom_phy *phy, bool val)
83{
84 writel_relaxed(val ? 0x1 : 0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
85 /*
86 * Before any transactions involving PHY, ensure PHY knows
87 * that it's analog rail is powered ON (or OFF).
88 */
89 mb();
90}
91
92static inline
93void ufs_qcom_phy_qmp_14nm_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val)
94{
95 /*
96 * 14nm PHY does not have TX_LANE_ENABLE register.
97 * Implement this function so as not to propagate error to caller.
98 */
99}
100
101static inline void ufs_qcom_phy_qmp_14nm_start_serdes(struct ufs_qcom_phy *phy)
102{
103 u32 tmp;
104
105 tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START);
106 tmp &= ~MASK_SERDES_START;
107 tmp |= (1 << OFFSET_SERDES_START);
108 writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START);
109 /* Ensure register value is committed */
110 mb();
111}
112
113static int ufs_qcom_phy_qmp_14nm_is_pcs_ready(struct ufs_qcom_phy *phy_common)
114{
115 int err = 0;
116 u32 val;
117
118 err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS,
119 val, (val & MASK_PCS_READY), 10, 1000000);
120 if (err)
121 dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n",
122 __func__, err);
123 return err;
124}
125
126static const struct phy_ops ufs_qcom_phy_qmp_14nm_phy_ops = {
127 .init = ufs_qcom_phy_qmp_14nm_init,
128 .exit = ufs_qcom_phy_qmp_14nm_exit,
129 .power_on = ufs_qcom_phy_power_on,
130 .power_off = ufs_qcom_phy_power_off,
131 .set_mode = ufs_qcom_phy_qmp_14nm_set_mode,
132 .owner = THIS_MODULE,
133};
134
135static struct ufs_qcom_phy_specific_ops phy_14nm_ops = {
136 .start_serdes = ufs_qcom_phy_qmp_14nm_start_serdes,
137 .is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_14nm_is_pcs_ready,
138 .set_tx_lane_enable = ufs_qcom_phy_qmp_14nm_set_tx_lane_enable,
139 .power_control = ufs_qcom_phy_qmp_14nm_power_control,
140};
141
142static int ufs_qcom_phy_qmp_14nm_probe(struct platform_device *pdev)
143{
144 struct device *dev = &pdev->dev;
145 struct phy *generic_phy;
146 struct ufs_qcom_phy_qmp_14nm *phy;
147 struct ufs_qcom_phy *phy_common;
148 int err = 0;
149
150 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
151 if (!phy) {
152 err = -ENOMEM;
153 goto out;
154 }
155 phy_common = &phy->common_cfg;
156
157 generic_phy = ufs_qcom_phy_generic_probe(pdev, phy_common,
158 &ufs_qcom_phy_qmp_14nm_phy_ops, &phy_14nm_ops);
159
160 if (!generic_phy) {
161 err = -EIO;
162 goto out;
163 }
164
165 err = ufs_qcom_phy_init_clks(phy_common);
166 if (err)
167 goto out;
168
169 err = ufs_qcom_phy_init_vregulators(phy_common);
170 if (err)
171 goto out;
172
173 phy_common->vdda_phy.max_uV = UFS_PHY_VDDA_PHY_UV;
174 phy_common->vdda_phy.min_uV = UFS_PHY_VDDA_PHY_UV;
175
176 ufs_qcom_phy_qmp_14nm_advertise_quirks(phy_common);
177
178 phy_set_drvdata(generic_phy, phy);
179
180 strlcpy(phy_common->name, UFS_PHY_NAME, sizeof(phy_common->name));
181
182out:
183 return err;
184}
185
186static const struct of_device_id ufs_qcom_phy_qmp_14nm_of_match[] = {
187 {.compatible = "qcom,ufs-phy-qmp-14nm"},
188 {.compatible = "qcom,msm8996-ufs-phy-qmp-14nm"},
189 {},
190};
191MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_14nm_of_match);
192
193static struct platform_driver ufs_qcom_phy_qmp_14nm_driver = {
194 .probe = ufs_qcom_phy_qmp_14nm_probe,
195 .driver = {
196 .of_match_table = ufs_qcom_phy_qmp_14nm_of_match,
197 .name = "ufs_qcom_phy_qmp_14nm",
198 },
199};
200
201module_platform_driver(ufs_qcom_phy_qmp_14nm_driver);
202
203MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP 14nm");
204MODULE_LICENSE("GPL v2");