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1Amlogic Meson Display Controller
2================================
3
4The Amlogic Meson Display controller is composed of several components
5that are going to be documented below:
6
7DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
8 | vd1 _______ _____________ _________________ | |
9D |-------| |----| | | | | HDMI PLL |
10D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
11R |-------| |----| Processing | | | | |
12 | osd2 | | | |---| Enci ----------|----|-----VDAC------|
13R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----|
14A | osd1 | | | Blenders | | Encl ----------|----|---------------|
15M |-------|______|----|____________| |________________| | |
16___|__________________________________________________________|_______________|
17
18
19VIU: Video Input Unit
20---------------------
21
22The Video Input Unit is in charge of the pixel scanout from the DDR memory.
23It fetches the frames addresses, stride and parameters from the "Canvas" memory.
24This part is also in charge of the CSC (Colorspace Conversion).
25It can handle 2 OSD Planes and 2 Video Planes.
26
27VPP: Video Post Processing
28--------------------------
29
30The Video Post Processing is in charge of the scaling and blending of the
31various planes into a single pixel stream.
32There is a special "pre-blending" used by the video planes with a dedicated
33scaler and a "post-blending" to merge with the OSD Planes.
34The OSD planes also have a dedicated scaler for one of the OSD.
35
36VENC: Video Encoders
37--------------------
38
39The VENC is composed of the multiple pixel encoders :
40 - ENCI : Interlace Video encoder for CVBS and Interlace HDMI
41 - ENCP : Progressive Video Encoder for HDMI
42 - ENCL : LCD LVDS Encoder
43The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock
44tree and provides the scanout clock to the VPP and VIU.
45The ENCI is connected to a single VDAC for Composite Output.
46The ENCI and ENCP are connected to an on-chip HDMI Transceiver.
47
48Device Tree Bindings:
49---------------------
50
51VPU: Video Processing Unit
52--------------------------
53
54Required properties:
55- compatible: value should be different for each SoC family as :
56 - GXBB (S905) : "amlogic,meson-gxbb-vpu"
57 - GXL (S905X, S905D) : "amlogic,meson-gxl-vpu"
58 - GXM (S912) : "amlogic,meson-gxm-vpu"
59 followed by the common "amlogic,meson-gx-vpu"
60- reg: base address and size of he following memory-mapped regions :
61 - vpu
62 - hhi
63 - dmc
64- reg-names: should contain the names of the previous memory regions
65- interrupts: should contain the VENC Vsync interrupt number
66
67Optional properties:
68- power-domains: Optional phandle to associated power domain as described in
69 the file ../power/power_domain.txt
70- amlogic,canvas: phandle to canvas provider node as described in the file
71 ../soc/amlogic/amlogic,canvas.txt
72
73Required nodes:
74
75The connections to the VPU output video ports are modeled using the OF graph
76bindings specified in Documentation/devicetree/bindings/graph.txt.
77
78The following table lists for each supported model the port number
79corresponding to each VPU output.
80
81 Port 0 Port 1
82-----------------------------------------
83 S905 (GXBB) CVBS VDAC HDMI-TX
84 S905X (GXL) CVBS VDAC HDMI-TX
85 S905D (GXL) CVBS VDAC HDMI-TX
86 S912 (GXM) CVBS VDAC HDMI-TX
87
88Example:
89
90tv-connector {
91 compatible = "composite-video-connector";
92
93 port {
94 tv_connector_in: endpoint {
95 remote-endpoint = <&cvbs_vdac_out>;
96 };
97 };
98};
99
100vpu: vpu@d0100000 {
101 compatible = "amlogic,meson-gxbb-vpu";
102 reg = <0x0 0xd0100000 0x0 0x100000>,
103 <0x0 0xc883c000 0x0 0x1000>,
104 <0x0 0xc8838000 0x0 0x1000>;
105 reg-names = "vpu", "hhi", "dmc";
106 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
107 #address-cells = <1>;
108 #size-cells = <0>;
109
110 /* CVBS VDAC output port */
111 port@0 {
112 reg = <0>;
113
114 cvbs_vdac_out: endpoint {
115 remote-endpoint = <&tv_connector_in>;
116 };
117 };
118};