tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Amlogic Meson6 SoCs timer handling.
3 *
4 * Copyright (C) 2014 Carlo Caione <carlo@caione.org>
5 *
6 * Based on code from Amlogic, Inc
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/bitfield.h>
14#include <linux/bitops.h>
15#include <linux/clk.h>
16#include <linux/clockchips.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/irqreturn.h>
20#include <linux/sched_clock.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/of_irq.h>
24
25#ifdef CONFIG_ARM
26#include <linux/delay.h>
27#endif
28
29#define MESON_ISA_TIMER_MUX 0x00
30#define MESON_ISA_TIMER_MUX_TIMERD_EN BIT(19)
31#define MESON_ISA_TIMER_MUX_TIMERC_EN BIT(18)
32#define MESON_ISA_TIMER_MUX_TIMERB_EN BIT(17)
33#define MESON_ISA_TIMER_MUX_TIMERA_EN BIT(16)
34#define MESON_ISA_TIMER_MUX_TIMERD_MODE BIT(15)
35#define MESON_ISA_TIMER_MUX_TIMERC_MODE BIT(14)
36#define MESON_ISA_TIMER_MUX_TIMERB_MODE BIT(13)
37#define MESON_ISA_TIMER_MUX_TIMERA_MODE BIT(12)
38#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK GENMASK(10, 8)
39#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_SYSTEM_CLOCK 0x0
40#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1US 0x1
41#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_10US 0x2
42#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_100US 0x3
43#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1MS 0x4
44#define MESON_ISA_TIMER_MUX_TIMERD_INPUT_CLOCK_MASK GENMASK(7, 6)
45#define MESON_ISA_TIMER_MUX_TIMERC_INPUT_CLOCK_MASK GENMASK(5, 4)
46#define MESON_ISA_TIMER_MUX_TIMERB_INPUT_CLOCK_MASK GENMASK(3, 2)
47#define MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK GENMASK(1, 0)
48#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1US 0x0
49#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_10US 0x1
50#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_100US 0x0
51#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1MS 0x3
52
53#define MESON_ISA_TIMERA 0x04
54#define MESON_ISA_TIMERB 0x08
55#define MESON_ISA_TIMERC 0x0c
56#define MESON_ISA_TIMERD 0x10
57#define MESON_ISA_TIMERE 0x14
58
59static void __iomem *timer_base;
60
61#ifdef CONFIG_ARM
62static unsigned long meson6_read_current_timer(void)
63{
64 return readl_relaxed(timer_base + MESON_ISA_TIMERE);
65}
66
67static struct delay_timer meson6_delay_timer = {
68 .read_current_timer = meson6_read_current_timer,
69 .freq = 1000 * 1000,
70};
71#endif
72
73static u64 notrace meson6_timer_sched_read(void)
74{
75 return (u64)readl(timer_base + MESON_ISA_TIMERE);
76}
77
78static void meson6_clkevt_time_stop(void)
79{
80 u32 val = readl(timer_base + MESON_ISA_TIMER_MUX);
81
82 writel(val & ~MESON_ISA_TIMER_MUX_TIMERA_EN,
83 timer_base + MESON_ISA_TIMER_MUX);
84}
85
86static void meson6_clkevt_time_setup(unsigned long delay)
87{
88 writel(delay, timer_base + MESON_ISA_TIMERA);
89}
90
91static void meson6_clkevt_time_start(bool periodic)
92{
93 u32 val = readl(timer_base + MESON_ISA_TIMER_MUX);
94
95 if (periodic)
96 val |= MESON_ISA_TIMER_MUX_TIMERA_MODE;
97 else
98 val &= ~MESON_ISA_TIMER_MUX_TIMERA_MODE;
99
100 writel(val | MESON_ISA_TIMER_MUX_TIMERA_EN,
101 timer_base + MESON_ISA_TIMER_MUX);
102}
103
104static int meson6_shutdown(struct clock_event_device *evt)
105{
106 meson6_clkevt_time_stop();
107 return 0;
108}
109
110static int meson6_set_oneshot(struct clock_event_device *evt)
111{
112 meson6_clkevt_time_stop();
113 meson6_clkevt_time_start(false);
114 return 0;
115}
116
117static int meson6_set_periodic(struct clock_event_device *evt)
118{
119 meson6_clkevt_time_stop();
120 meson6_clkevt_time_setup(USEC_PER_SEC / HZ - 1);
121 meson6_clkevt_time_start(true);
122 return 0;
123}
124
125static int meson6_clkevt_next_event(unsigned long evt,
126 struct clock_event_device *unused)
127{
128 meson6_clkevt_time_stop();
129 meson6_clkevt_time_setup(evt);
130 meson6_clkevt_time_start(false);
131
132 return 0;
133}
134
135static struct clock_event_device meson6_clockevent = {
136 .name = "meson6_tick",
137 .rating = 400,
138 .features = CLOCK_EVT_FEAT_PERIODIC |
139 CLOCK_EVT_FEAT_ONESHOT,
140 .set_state_shutdown = meson6_shutdown,
141 .set_state_periodic = meson6_set_periodic,
142 .set_state_oneshot = meson6_set_oneshot,
143 .tick_resume = meson6_shutdown,
144 .set_next_event = meson6_clkevt_next_event,
145};
146
147static irqreturn_t meson6_timer_interrupt(int irq, void *dev_id)
148{
149 struct clock_event_device *evt = (struct clock_event_device *)dev_id;
150
151 evt->event_handler(evt);
152
153 return IRQ_HANDLED;
154}
155
156static struct irqaction meson6_timer_irq = {
157 .name = "meson6_timer",
158 .flags = IRQF_TIMER | IRQF_IRQPOLL,
159 .handler = meson6_timer_interrupt,
160 .dev_id = &meson6_clockevent,
161};
162
163static int __init meson6_timer_init(struct device_node *node)
164{
165 u32 val;
166 int ret, irq;
167
168 timer_base = of_io_request_and_map(node, 0, "meson6-timer");
169 if (IS_ERR(timer_base)) {
170 pr_err("Can't map registers\n");
171 return -ENXIO;
172 }
173
174 irq = irq_of_parse_and_map(node, 0);
175 if (irq <= 0) {
176 pr_err("Can't parse IRQ\n");
177 return -EINVAL;
178 }
179
180 /* Set 1us for timer E */
181 val = readl(timer_base + MESON_ISA_TIMER_MUX);
182 val &= ~MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK;
183 val |= FIELD_PREP(MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK,
184 MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1US);
185 writel(val, timer_base + MESON_ISA_TIMER_MUX);
186
187 sched_clock_register(meson6_timer_sched_read, 32, USEC_PER_SEC);
188 clocksource_mmio_init(timer_base + MESON_ISA_TIMERE, node->name,
189 1000 * 1000, 300, 32, clocksource_mmio_readl_up);
190
191 /* Timer A base 1us */
192 val &= ~MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK;
193 val |= FIELD_PREP(MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK,
194 MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1US);
195 writel(val, timer_base + MESON_ISA_TIMER_MUX);
196
197 /* Stop the timer A */
198 meson6_clkevt_time_stop();
199
200 ret = setup_irq(irq, &meson6_timer_irq);
201 if (ret) {
202 pr_warn("failed to setup irq %d\n", irq);
203 return ret;
204 }
205
206 meson6_clockevent.cpumask = cpu_possible_mask;
207 meson6_clockevent.irq = irq;
208
209 clockevents_config_and_register(&meson6_clockevent, USEC_PER_SEC,
210 1, 0xfffe);
211
212#ifdef CONFIG_ARM
213 /* Also use MESON_ISA_TIMERE for delays */
214 register_current_timer_delay(&meson6_delay_timer);
215#endif
216
217 return 0;
218}
219TIMER_OF_DECLARE(meson6, "amlogic,meson6-timer",
220 meson6_timer_init);