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1/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2/* Copyright (c) 2018 Mellanox Technologies. */
3
4#ifndef MLX5_CORE_EQ_H
5#define MLX5_CORE_EQ_H
6
7enum {
8 MLX5_EQ_PAGEREQ_IDX = 0,
9 MLX5_EQ_CMD_IDX = 1,
10 MLX5_EQ_ASYNC_IDX = 2,
11 /* reserved to be used by mlx5_core ulps (mlx5e/mlx5_ib) */
12 MLX5_EQ_PFAULT_IDX = 3,
13 MLX5_EQ_MAX_ASYNC_EQS,
14 /* completion eqs vector indices start here */
15 MLX5_EQ_VEC_COMP_BASE = MLX5_EQ_MAX_ASYNC_EQS,
16};
17
18#define MLX5_NUM_CMD_EQE (32)
19#define MLX5_NUM_ASYNC_EQE (0x1000)
20#define MLX5_NUM_SPARE_EQE (0x80)
21
22struct mlx5_eq;
23struct mlx5_core_dev;
24
25struct mlx5_eq_param {
26 u8 index;
27 int nent;
28 u64 mask;
29 void *context;
30 irq_handler_t handler;
31};
32
33struct mlx5_eq *
34mlx5_eq_create_generic(struct mlx5_core_dev *dev, const char *name,
35 struct mlx5_eq_param *param);
36int
37mlx5_eq_destroy_generic(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
38
39struct mlx5_eqe *mlx5_eq_get_eqe(struct mlx5_eq *eq, u32 cc);
40void mlx5_eq_update_ci(struct mlx5_eq *eq, u32 cc, bool arm);
41
42/* The HCA will think the queue has overflowed if we
43 * don't tell it we've been processing events. We
44 * create EQs with MLX5_NUM_SPARE_EQE extra entries,
45 * so we must update our consumer index at
46 * least that often.
47 *
48 * mlx5_eq_update_cc must be called on every EQE @EQ irq handler
49 */
50static inline u32 mlx5_eq_update_cc(struct mlx5_eq *eq, u32 cc)
51{
52 if (unlikely(cc >= MLX5_NUM_SPARE_EQE)) {
53 mlx5_eq_update_ci(eq, cc, 0);
54 cc = 0;
55 }
56 return cc;
57}
58
59struct mlx5_nb {
60 struct notifier_block nb;
61 u8 event_type;
62};
63
64#define mlx5_nb_cof(ptr, type, member) \
65 (container_of(container_of(ptr, struct mlx5_nb, nb), type, member))
66
67#define MLX5_NB_INIT(name, handler, event) do { \
68 (name)->nb.notifier_call = handler; \
69 (name)->event_type = MLX5_EVENT_TYPE_##event; \
70} while (0)
71
72#endif /* MLX5_CORE_EQ_H */