Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
38#include <linux/mlx5/mlx5_ifc.h>
39
40#if defined(__LITTLE_ENDIAN)
41#define MLX5_SET_HOST_ENDIANNESS 0
42#elif defined(__BIG_ENDIAN)
43#define MLX5_SET_HOST_ENDIANNESS 0x80
44#else
45#error Host endianness not defined
46#endif
47
48/* helper macros */
49#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51#define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld))
52#define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
53#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
54#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
55#define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))
56#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
57#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
58#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
59#define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
60#define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld))
61#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
62
63#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
64#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
65#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
66#define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
67#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
68#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
69#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
70#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
71
72/* insert a value to a struct */
73#define MLX5_SET(typ, p, fld, v) do { \
74 u32 _v = v; \
75 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
76 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
77 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
78 (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \
79 << __mlx5_dw_bit_off(typ, fld))); \
80} while (0)
81
82#define MLX5_ARRAY_SET(typ, p, fld, idx, v) do { \
83 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 32); \
84 MLX5_SET(typ, p, fld[idx], v); \
85} while (0)
86
87#define MLX5_SET_TO_ONES(typ, p, fld) do { \
88 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
89 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
90 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
91 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
92 << __mlx5_dw_bit_off(typ, fld))); \
93} while (0)
94
95#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
96__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
97__mlx5_mask(typ, fld))
98
99#define MLX5_GET_PR(typ, p, fld) ({ \
100 u32 ___t = MLX5_GET(typ, p, fld); \
101 pr_debug(#fld " = 0x%x\n", ___t); \
102 ___t; \
103})
104
105#define __MLX5_SET64(typ, p, fld, v) do { \
106 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
107 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
108} while (0)
109
110#define MLX5_SET64(typ, p, fld, v) do { \
111 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
112 __MLX5_SET64(typ, p, fld, v); \
113} while (0)
114
115#define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
116 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
117 __MLX5_SET64(typ, p, fld[idx], v); \
118} while (0)
119
120#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
121
122#define MLX5_GET64_PR(typ, p, fld) ({ \
123 u64 ___t = MLX5_GET64(typ, p, fld); \
124 pr_debug(#fld " = 0x%llx\n", ___t); \
125 ___t; \
126})
127
128#define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\
129__mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
130__mlx5_mask16(typ, fld))
131
132#define MLX5_SET16(typ, p, fld, v) do { \
133 u16 _v = v; \
134 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \
135 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
136 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \
137 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \
138 << __mlx5_16_bit_off(typ, fld))); \
139} while (0)
140
141/* Big endian getters */
142#define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
143 __mlx5_64_off(typ, fld)))
144
145#define MLX5_GET_BE(type_t, typ, p, fld) ({ \
146 type_t tmp; \
147 switch (sizeof(tmp)) { \
148 case sizeof(u8): \
149 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
150 break; \
151 case sizeof(u16): \
152 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
153 break; \
154 case sizeof(u32): \
155 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
156 break; \
157 case sizeof(u64): \
158 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
159 break; \
160 } \
161 tmp; \
162 })
163
164enum mlx5_inline_modes {
165 MLX5_INLINE_MODE_NONE,
166 MLX5_INLINE_MODE_L2,
167 MLX5_INLINE_MODE_IP,
168 MLX5_INLINE_MODE_TCP_UDP,
169};
170
171enum {
172 MLX5_MAX_COMMANDS = 32,
173 MLX5_CMD_DATA_BLOCK_SIZE = 512,
174 MLX5_PCI_CMD_XPORT = 7,
175 MLX5_MKEY_BSF_OCTO_SIZE = 4,
176 MLX5_MAX_PSVS = 4,
177};
178
179enum {
180 MLX5_EXTENDED_UD_AV = 0x80000000,
181};
182
183enum {
184 MLX5_CQ_STATE_ARMED = 9,
185 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
186 MLX5_CQ_STATE_FIRED = 0xa,
187};
188
189enum {
190 MLX5_STAT_RATE_OFFSET = 5,
191};
192
193enum {
194 MLX5_INLINE_SEG = 0x80000000,
195};
196
197enum {
198 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
199};
200
201enum {
202 MLX5_MIN_PKEY_TABLE_SIZE = 128,
203 MLX5_MAX_LOG_PKEY_TABLE = 5,
204};
205
206enum {
207 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
208};
209
210enum {
211 MLX5_PFAULT_SUBTYPE_WQE = 0,
212 MLX5_PFAULT_SUBTYPE_RDMA = 1,
213};
214
215enum wqe_page_fault_type {
216 MLX5_WQE_PF_TYPE_RMP = 0,
217 MLX5_WQE_PF_TYPE_REQ_SEND_OR_WRITE = 1,
218 MLX5_WQE_PF_TYPE_RESP = 2,
219 MLX5_WQE_PF_TYPE_REQ_READ_OR_ATOMIC = 3,
220};
221
222enum {
223 MLX5_PERM_LOCAL_READ = 1 << 2,
224 MLX5_PERM_LOCAL_WRITE = 1 << 3,
225 MLX5_PERM_REMOTE_READ = 1 << 4,
226 MLX5_PERM_REMOTE_WRITE = 1 << 5,
227 MLX5_PERM_ATOMIC = 1 << 6,
228 MLX5_PERM_UMR_EN = 1 << 7,
229};
230
231enum {
232 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
233 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
234 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
235 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
236 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
237};
238
239enum {
240 MLX5_EN_RD = (u64)1,
241 MLX5_EN_WR = (u64)2
242};
243
244enum {
245 MLX5_ADAPTER_PAGE_SHIFT = 12,
246 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
247};
248
249enum {
250 MLX5_BFREGS_PER_UAR = 4,
251 MLX5_MAX_UARS = 1 << 8,
252 MLX5_NON_FP_BFREGS_PER_UAR = 2,
253 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR -
254 MLX5_NON_FP_BFREGS_PER_UAR,
255 MLX5_MAX_BFREGS = MLX5_MAX_UARS *
256 MLX5_NON_FP_BFREGS_PER_UAR,
257 MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE,
258 MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE,
259 MLX5_MIN_DYN_BFREGS = 512,
260 MLX5_MAX_DYN_BFREGS = 1024,
261};
262
263enum {
264 MLX5_MKEY_MASK_LEN = 1ull << 0,
265 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
266 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
267 MLX5_MKEY_MASK_PD = 1ull << 7,
268 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
269 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
270 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
271 MLX5_MKEY_MASK_KEY = 1ull << 13,
272 MLX5_MKEY_MASK_QPN = 1ull << 14,
273 MLX5_MKEY_MASK_LR = 1ull << 17,
274 MLX5_MKEY_MASK_LW = 1ull << 18,
275 MLX5_MKEY_MASK_RR = 1ull << 19,
276 MLX5_MKEY_MASK_RW = 1ull << 20,
277 MLX5_MKEY_MASK_A = 1ull << 21,
278 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
279 MLX5_MKEY_MASK_FREE = 1ull << 29,
280};
281
282enum {
283 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
284
285 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
286 MLX5_UMR_CHECK_FREE = (2 << 5),
287
288 MLX5_UMR_INLINE = (1 << 7),
289};
290
291#define MLX5_UMR_MTT_ALIGNMENT 0x40
292#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
293#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
294
295#define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
296
297enum {
298 MLX5_EVENT_QUEUE_TYPE_QP = 0,
299 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
300 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
301 MLX5_EVENT_QUEUE_TYPE_DCT = 6,
302};
303
304/* mlx5 components can subscribe to any one of these events via
305 * mlx5_eq_notifier_register API.
306 */
307enum mlx5_event {
308 /* Special value to subscribe to any event */
309 MLX5_EVENT_TYPE_NOTIFY_ANY = 0x0,
310 /* HW events enum start: comp events are not subscribable */
311 MLX5_EVENT_TYPE_COMP = 0x0,
312 /* HW Async events enum start: subscribable events */
313 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
314 MLX5_EVENT_TYPE_COMM_EST = 0x02,
315 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
316 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
317 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
318
319 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
320 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
321 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
322 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
323 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
324 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
325
326 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
327 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
328 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
329 MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 0x16,
330 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17,
331 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
332 MLX5_EVENT_TYPE_GENERAL_EVENT = 0x22,
333 MLX5_EVENT_TYPE_MONITOR_COUNTER = 0x24,
334 MLX5_EVENT_TYPE_PPS_EVENT = 0x25,
335
336 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
337 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
338
339 MLX5_EVENT_TYPE_CMD = 0x0a,
340 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
341
342 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
343 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
344
345 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c,
346
347 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20,
348 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21,
349
350 MLX5_EVENT_TYPE_DEVICE_TRACER = 0x26,
351
352 MLX5_EVENT_TYPE_MAX = MLX5_EVENT_TYPE_DEVICE_TRACER + 1,
353};
354
355enum {
356 MLX5_TRACER_SUBTYPE_OWNERSHIP_CHANGE = 0x0,
357 MLX5_TRACER_SUBTYPE_TRACES_AVAILABLE = 0x1,
358};
359
360enum {
361 MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
362};
363
364enum {
365 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
366 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
367 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
368 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
369 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
370 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
371 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
372};
373
374enum {
375 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
376 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
377 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
378 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
379 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
380 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
381 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
382 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
383 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
384 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
385 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
386 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
387};
388
389enum {
390 MLX5_ROCE_VERSION_1 = 0,
391 MLX5_ROCE_VERSION_2 = 2,
392};
393
394enum {
395 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
396 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
397};
398
399enum {
400 MLX5_ROCE_L3_TYPE_IPV4 = 0,
401 MLX5_ROCE_L3_TYPE_IPV6 = 1,
402};
403
404enum {
405 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
406 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
407};
408
409enum {
410 MLX5_OPCODE_NOP = 0x00,
411 MLX5_OPCODE_SEND_INVAL = 0x01,
412 MLX5_OPCODE_RDMA_WRITE = 0x08,
413 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
414 MLX5_OPCODE_SEND = 0x0a,
415 MLX5_OPCODE_SEND_IMM = 0x0b,
416 MLX5_OPCODE_LSO = 0x0e,
417 MLX5_OPCODE_RDMA_READ = 0x10,
418 MLX5_OPCODE_ATOMIC_CS = 0x11,
419 MLX5_OPCODE_ATOMIC_FA = 0x12,
420 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
421 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
422 MLX5_OPCODE_BIND_MW = 0x18,
423 MLX5_OPCODE_CONFIG_CMD = 0x1f,
424 MLX5_OPCODE_ENHANCED_MPSW = 0x29,
425
426 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
427 MLX5_RECV_OPCODE_SEND = 0x01,
428 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
429 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
430
431 MLX5_CQE_OPCODE_ERROR = 0x1e,
432 MLX5_CQE_OPCODE_RESIZE = 0x16,
433
434 MLX5_OPCODE_SET_PSV = 0x20,
435 MLX5_OPCODE_GET_PSV = 0x21,
436 MLX5_OPCODE_CHECK_PSV = 0x22,
437 MLX5_OPCODE_RGET_PSV = 0x26,
438 MLX5_OPCODE_RCHECK_PSV = 0x27,
439
440 MLX5_OPCODE_UMR = 0x25,
441
442};
443
444enum {
445 MLX5_SET_PORT_RESET_QKEY = 0,
446 MLX5_SET_PORT_GUID0 = 16,
447 MLX5_SET_PORT_NODE_GUID = 17,
448 MLX5_SET_PORT_SYS_GUID = 18,
449 MLX5_SET_PORT_GID_TABLE = 19,
450 MLX5_SET_PORT_PKEY_TABLE = 20,
451};
452
453enum {
454 MLX5_BW_NO_LIMIT = 0,
455 MLX5_100_MBPS_UNIT = 3,
456 MLX5_GBPS_UNIT = 4,
457};
458
459enum {
460 MLX5_MAX_PAGE_SHIFT = 31
461};
462
463enum {
464 MLX5_CAP_OFF_CMDIF_CSUM = 46,
465};
466
467enum {
468 /*
469 * Max wqe size for rdma read is 512 bytes, so this
470 * limits our max_sge_rd as the wqe needs to fit:
471 * - ctrl segment (16 bytes)
472 * - rdma segment (16 bytes)
473 * - scatter elements (16 bytes each)
474 */
475 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
476};
477
478enum mlx5_odp_transport_cap_bits {
479 MLX5_ODP_SUPPORT_SEND = 1 << 31,
480 MLX5_ODP_SUPPORT_RECV = 1 << 30,
481 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
482 MLX5_ODP_SUPPORT_READ = 1 << 28,
483};
484
485struct mlx5_odp_caps {
486 char reserved[0x10];
487 struct {
488 __be32 rc_odp_caps;
489 __be32 uc_odp_caps;
490 __be32 ud_odp_caps;
491 } per_transport_caps;
492 char reserved2[0xe4];
493};
494
495struct mlx5_cmd_layout {
496 u8 type;
497 u8 rsvd0[3];
498 __be32 inlen;
499 __be64 in_ptr;
500 __be32 in[4];
501 __be32 out[4];
502 __be64 out_ptr;
503 __be32 outlen;
504 u8 token;
505 u8 sig;
506 u8 rsvd1;
507 u8 status_own;
508};
509
510struct health_buffer {
511 __be32 assert_var[5];
512 __be32 rsvd0[3];
513 __be32 assert_exit_ptr;
514 __be32 assert_callra;
515 __be32 rsvd1[2];
516 __be32 fw_ver;
517 __be32 hw_id;
518 __be32 rsvd2;
519 u8 irisc_index;
520 u8 synd;
521 __be16 ext_synd;
522};
523
524enum mlx5_cmd_addr_l_sz_offset {
525 MLX5_NIC_IFC_OFFSET = 8,
526};
527
528struct mlx5_init_seg {
529 __be32 fw_rev;
530 __be32 cmdif_rev_fw_sub;
531 __be32 rsvd0[2];
532 __be32 cmdq_addr_h;
533 __be32 cmdq_addr_l_sz;
534 __be32 cmd_dbell;
535 __be32 rsvd1[120];
536 __be32 initializing;
537 struct health_buffer health;
538 __be32 rsvd2[880];
539 __be32 internal_timer_h;
540 __be32 internal_timer_l;
541 __be32 rsvd3[2];
542 __be32 health_counter;
543 __be32 rsvd4[1019];
544 __be64 ieee1588_clk;
545 __be32 ieee1588_clk_type;
546 __be32 clr_intx;
547};
548
549struct mlx5_eqe_comp {
550 __be32 reserved[6];
551 __be32 cqn;
552};
553
554struct mlx5_eqe_qp_srq {
555 __be32 reserved1[5];
556 u8 type;
557 u8 reserved2[3];
558 __be32 qp_srq_n;
559};
560
561struct mlx5_eqe_cq_err {
562 __be32 cqn;
563 u8 reserved1[7];
564 u8 syndrome;
565};
566
567struct mlx5_eqe_port_state {
568 u8 reserved0[8];
569 u8 port;
570};
571
572struct mlx5_eqe_gpio {
573 __be32 reserved0[2];
574 __be64 gpio_event;
575};
576
577struct mlx5_eqe_congestion {
578 u8 type;
579 u8 rsvd0;
580 u8 congestion_level;
581};
582
583struct mlx5_eqe_stall_vl {
584 u8 rsvd0[3];
585 u8 port_vl;
586};
587
588struct mlx5_eqe_cmd {
589 __be32 vector;
590 __be32 rsvd[6];
591};
592
593struct mlx5_eqe_page_req {
594 u8 rsvd0[2];
595 __be16 func_id;
596 __be32 num_pages;
597 __be32 rsvd1[5];
598};
599
600struct mlx5_eqe_page_fault {
601 __be32 bytes_committed;
602 union {
603 struct {
604 u16 reserved1;
605 __be16 wqe_index;
606 u16 reserved2;
607 __be16 packet_length;
608 __be32 token;
609 u8 reserved4[8];
610 __be32 pftype_wq;
611 } __packed wqe;
612 struct {
613 __be32 r_key;
614 u16 reserved1;
615 __be16 packet_length;
616 __be32 rdma_op_len;
617 __be64 rdma_va;
618 __be32 pftype_token;
619 } __packed rdma;
620 } __packed;
621} __packed;
622
623struct mlx5_eqe_vport_change {
624 u8 rsvd0[2];
625 __be16 vport_num;
626 __be32 rsvd1[6];
627} __packed;
628
629struct mlx5_eqe_port_module {
630 u8 reserved_at_0[1];
631 u8 module;
632 u8 reserved_at_2[1];
633 u8 module_status;
634 u8 reserved_at_4[2];
635 u8 error_type;
636} __packed;
637
638struct mlx5_eqe_pps {
639 u8 rsvd0[3];
640 u8 pin;
641 u8 rsvd1[4];
642 union {
643 struct {
644 __be32 time_sec;
645 __be32 time_nsec;
646 };
647 struct {
648 __be64 time_stamp;
649 };
650 };
651 u8 rsvd2[12];
652} __packed;
653
654struct mlx5_eqe_dct {
655 __be32 reserved[6];
656 __be32 dctn;
657};
658
659struct mlx5_eqe_temp_warning {
660 __be64 sensor_warning_msb;
661 __be64 sensor_warning_lsb;
662} __packed;
663
664union ev_data {
665 __be32 raw[7];
666 struct mlx5_eqe_cmd cmd;
667 struct mlx5_eqe_comp comp;
668 struct mlx5_eqe_qp_srq qp_srq;
669 struct mlx5_eqe_cq_err cq_err;
670 struct mlx5_eqe_port_state port;
671 struct mlx5_eqe_gpio gpio;
672 struct mlx5_eqe_congestion cong;
673 struct mlx5_eqe_stall_vl stall_vl;
674 struct mlx5_eqe_page_req req_pages;
675 struct mlx5_eqe_page_fault page_fault;
676 struct mlx5_eqe_vport_change vport_change;
677 struct mlx5_eqe_port_module port_module;
678 struct mlx5_eqe_pps pps;
679 struct mlx5_eqe_dct dct;
680 struct mlx5_eqe_temp_warning temp_warning;
681} __packed;
682
683struct mlx5_eqe {
684 u8 rsvd0;
685 u8 type;
686 u8 rsvd1;
687 u8 sub_type;
688 __be32 rsvd2[7];
689 union ev_data data;
690 __be16 rsvd3;
691 u8 signature;
692 u8 owner;
693} __packed;
694
695struct mlx5_cmd_prot_block {
696 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
697 u8 rsvd0[48];
698 __be64 next;
699 __be32 block_num;
700 u8 rsvd1;
701 u8 token;
702 u8 ctrl_sig;
703 u8 sig;
704};
705
706enum {
707 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
708};
709
710struct mlx5_err_cqe {
711 u8 rsvd0[32];
712 __be32 srqn;
713 u8 rsvd1[18];
714 u8 vendor_err_synd;
715 u8 syndrome;
716 __be32 s_wqe_opcode_qpn;
717 __be16 wqe_counter;
718 u8 signature;
719 u8 op_own;
720};
721
722struct mlx5_cqe64 {
723 u8 outer_l3_tunneled;
724 u8 rsvd0;
725 __be16 wqe_id;
726 u8 lro_tcppsh_abort_dupack;
727 u8 lro_min_ttl;
728 __be16 lro_tcp_win;
729 __be32 lro_ack_seq_num;
730 __be32 rss_hash_result;
731 u8 rss_hash_type;
732 u8 ml_path;
733 u8 rsvd20[2];
734 __be16 check_sum;
735 __be16 slid;
736 __be32 flags_rqpn;
737 u8 hds_ip_ext;
738 u8 l4_l3_hdr_type;
739 __be16 vlan_info;
740 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
741 __be32 imm_inval_pkey;
742 u8 rsvd40[4];
743 __be32 byte_cnt;
744 __be32 timestamp_h;
745 __be32 timestamp_l;
746 __be32 sop_drop_qpn;
747 __be16 wqe_counter;
748 u8 signature;
749 u8 op_own;
750};
751
752struct mlx5_mini_cqe8 {
753 union {
754 __be32 rx_hash_result;
755 struct {
756 __be16 checksum;
757 __be16 rsvd;
758 };
759 struct {
760 __be16 wqe_counter;
761 u8 s_wqe_opcode;
762 u8 reserved;
763 } s_wqe_info;
764 };
765 __be32 byte_cnt;
766};
767
768enum {
769 MLX5_NO_INLINE_DATA,
770 MLX5_INLINE_DATA32_SEG,
771 MLX5_INLINE_DATA64_SEG,
772 MLX5_COMPRESSED,
773};
774
775enum {
776 MLX5_CQE_FORMAT_CSUM = 0x1,
777};
778
779#define MLX5_MINI_CQE_ARRAY_SIZE 8
780
781static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
782{
783 return (cqe->op_own >> 2) & 0x3;
784}
785
786static inline u8 get_cqe_opcode(struct mlx5_cqe64 *cqe)
787{
788 return cqe->op_own >> 4;
789}
790
791static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
792{
793 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
794}
795
796static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
797{
798 return (cqe->l4_l3_hdr_type >> 4) & 0x7;
799}
800
801static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe)
802{
803 return (cqe->l4_l3_hdr_type >> 2) & 0x3;
804}
805
806static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
807{
808 return cqe->outer_l3_tunneled & 0x1;
809}
810
811static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe)
812{
813 return cqe->l4_l3_hdr_type & 0x1;
814}
815
816static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
817{
818 u32 hi, lo;
819
820 hi = be32_to_cpu(cqe->timestamp_h);
821 lo = be32_to_cpu(cqe->timestamp_l);
822
823 return (u64)lo | ((u64)hi << 32);
824}
825
826#define MLX5_MPWQE_LOG_NUM_STRIDES_BASE (9)
827#define MLX5_MPWQE_LOG_STRIDE_SZ_BASE (6)
828
829struct mpwrq_cqe_bc {
830 __be16 filler_consumed_strides;
831 __be16 byte_cnt;
832};
833
834static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe)
835{
836 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
837
838 return be16_to_cpu(bc->byte_cnt);
839}
840
841static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc)
842{
843 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides);
844}
845
846static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe)
847{
848 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
849
850 return mpwrq_get_cqe_bc_consumed_strides(bc);
851}
852
853static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe)
854{
855 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
856
857 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides);
858}
859
860static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe)
861{
862 return be16_to_cpu(cqe->wqe_counter);
863}
864
865enum {
866 CQE_L4_HDR_TYPE_NONE = 0x0,
867 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
868 CQE_L4_HDR_TYPE_UDP = 0x2,
869 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
870 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
871};
872
873enum {
874 CQE_RSS_HTYPE_IP = 0x3 << 2,
875 /* cqe->rss_hash_type[3:2] - IP destination selected for hash
876 * (00 = none, 01 = IPv4, 10 = IPv6, 11 = Reserved)
877 */
878 CQE_RSS_HTYPE_L4 = 0x3 << 6,
879 /* cqe->rss_hash_type[7:6] - L4 destination selected for hash
880 * (00 = none, 01 = TCP. 10 = UDP, 11 = IPSEC.SPI
881 */
882};
883
884enum {
885 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
886 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
887 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
888};
889
890enum {
891 CQE_L2_OK = 1 << 0,
892 CQE_L3_OK = 1 << 1,
893 CQE_L4_OK = 1 << 2,
894};
895
896struct mlx5_sig_err_cqe {
897 u8 rsvd0[16];
898 __be32 expected_trans_sig;
899 __be32 actual_trans_sig;
900 __be32 expected_reftag;
901 __be32 actual_reftag;
902 __be16 syndrome;
903 u8 rsvd22[2];
904 __be32 mkey;
905 __be64 err_offset;
906 u8 rsvd30[8];
907 __be32 qpn;
908 u8 rsvd38[2];
909 u8 signature;
910 u8 op_own;
911};
912
913struct mlx5_wqe_srq_next_seg {
914 u8 rsvd0[2];
915 __be16 next_wqe_index;
916 u8 signature;
917 u8 rsvd1[11];
918};
919
920union mlx5_ext_cqe {
921 struct ib_grh grh;
922 u8 inl[64];
923};
924
925struct mlx5_cqe128 {
926 union mlx5_ext_cqe inl_grh;
927 struct mlx5_cqe64 cqe64;
928};
929
930enum {
931 MLX5_MKEY_STATUS_FREE = 1 << 6,
932};
933
934enum {
935 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
936 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
937 MLX5_MKEY_BSF_EN = 1 << 30,
938 MLX5_MKEY_LEN64 = 1 << 31,
939};
940
941struct mlx5_mkey_seg {
942 /* This is a two bit field occupying bits 31-30.
943 * bit 31 is always 0,
944 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
945 */
946 u8 status;
947 u8 pcie_control;
948 u8 flags;
949 u8 version;
950 __be32 qpn_mkey7_0;
951 u8 rsvd1[4];
952 __be32 flags_pd;
953 __be64 start_addr;
954 __be64 len;
955 __be32 bsfs_octo_size;
956 u8 rsvd2[16];
957 __be32 xlt_oct_size;
958 u8 rsvd3[3];
959 u8 log2_page_size;
960 u8 rsvd4[4];
961};
962
963#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
964
965enum {
966 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
967};
968
969enum {
970 VPORT_STATE_DOWN = 0x0,
971 VPORT_STATE_UP = 0x1,
972};
973
974enum {
975 MLX5_VPORT_ADMIN_STATE_DOWN = 0x0,
976 MLX5_VPORT_ADMIN_STATE_UP = 0x1,
977 MLX5_VPORT_ADMIN_STATE_AUTO = 0x2,
978};
979
980enum {
981 MLX5_L3_PROT_TYPE_IPV4 = 0,
982 MLX5_L3_PROT_TYPE_IPV6 = 1,
983};
984
985enum {
986 MLX5_L4_PROT_TYPE_TCP = 0,
987 MLX5_L4_PROT_TYPE_UDP = 1,
988};
989
990enum {
991 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
992 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
993 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
994 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
995 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
996};
997
998enum {
999 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
1000 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
1001 MLX5_MATCH_INNER_HEADERS = 1 << 2,
1002
1003};
1004
1005enum {
1006 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
1007 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
1008};
1009
1010enum {
1011 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
1012 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
1013 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
1014};
1015
1016enum mlx5_list_type {
1017 MLX5_NVPRT_LIST_TYPE_UC = 0x0,
1018 MLX5_NVPRT_LIST_TYPE_MC = 0x1,
1019 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
1020};
1021
1022enum {
1023 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1024 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
1025};
1026
1027enum mlx5_wol_mode {
1028 MLX5_WOL_DISABLE = 0,
1029 MLX5_WOL_SECURED_MAGIC = 1 << 1,
1030 MLX5_WOL_MAGIC = 1 << 2,
1031 MLX5_WOL_ARP = 1 << 3,
1032 MLX5_WOL_BROADCAST = 1 << 4,
1033 MLX5_WOL_MULTICAST = 1 << 5,
1034 MLX5_WOL_UNICAST = 1 << 6,
1035 MLX5_WOL_PHY_ACTIVITY = 1 << 7,
1036};
1037
1038enum mlx5_mpls_supported_fields {
1039 MLX5_FIELD_SUPPORT_MPLS_LABEL = 1 << 0,
1040 MLX5_FIELD_SUPPORT_MPLS_EXP = 1 << 1,
1041 MLX5_FIELD_SUPPORT_MPLS_S_BOS = 1 << 2,
1042 MLX5_FIELD_SUPPORT_MPLS_TTL = 1 << 3
1043};
1044
1045enum mlx5_flex_parser_protos {
1046 MLX5_FLEX_PROTO_CW_MPLS_GRE = 1 << 4,
1047 MLX5_FLEX_PROTO_CW_MPLS_UDP = 1 << 5,
1048};
1049
1050/* MLX5 DEV CAPs */
1051
1052/* TODO: EAT.ME */
1053enum mlx5_cap_mode {
1054 HCA_CAP_OPMOD_GET_MAX = 0,
1055 HCA_CAP_OPMOD_GET_CUR = 1,
1056};
1057
1058enum mlx5_cap_type {
1059 MLX5_CAP_GENERAL = 0,
1060 MLX5_CAP_ETHERNET_OFFLOADS,
1061 MLX5_CAP_ODP,
1062 MLX5_CAP_ATOMIC,
1063 MLX5_CAP_ROCE,
1064 MLX5_CAP_IPOIB_OFFLOADS,
1065 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1066 MLX5_CAP_FLOW_TABLE,
1067 MLX5_CAP_ESWITCH_FLOW_TABLE,
1068 MLX5_CAP_ESWITCH,
1069 MLX5_CAP_RESERVED,
1070 MLX5_CAP_VECTOR_CALC,
1071 MLX5_CAP_QOS,
1072 MLX5_CAP_DEBUG,
1073 MLX5_CAP_RESERVED_14,
1074 MLX5_CAP_DEV_MEM,
1075 /* NUM OF CAP Types */
1076 MLX5_CAP_NUM
1077};
1078
1079enum mlx5_pcam_reg_groups {
1080 MLX5_PCAM_REGS_5000_TO_507F = 0x0,
1081};
1082
1083enum mlx5_pcam_feature_groups {
1084 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1085};
1086
1087enum mlx5_mcam_reg_groups {
1088 MLX5_MCAM_REGS_FIRST_128 = 0x0,
1089};
1090
1091enum mlx5_mcam_feature_groups {
1092 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1093};
1094
1095enum mlx5_qcam_reg_groups {
1096 MLX5_QCAM_REGS_FIRST_128 = 0x0,
1097};
1098
1099enum mlx5_qcam_feature_groups {
1100 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1101};
1102
1103/* GET Dev Caps macros */
1104#define MLX5_CAP_GEN(mdev, cap) \
1105 MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
1106
1107#define MLX5_CAP_GEN_64(mdev, cap) \
1108 MLX5_GET64(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
1109
1110#define MLX5_CAP_GEN_MAX(mdev, cap) \
1111 MLX5_GET(cmd_hca_cap, mdev->caps.hca_max[MLX5_CAP_GENERAL], cap)
1112
1113#define MLX5_CAP_ETH(mdev, cap) \
1114 MLX5_GET(per_protocol_networking_offload_caps,\
1115 mdev->caps.hca_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1116
1117#define MLX5_CAP_ETH_MAX(mdev, cap) \
1118 MLX5_GET(per_protocol_networking_offload_caps,\
1119 mdev->caps.hca_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1120
1121#define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \
1122 MLX5_GET(per_protocol_networking_offload_caps,\
1123 mdev->caps.hca_cur[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS], cap)
1124
1125#define MLX5_CAP_ROCE(mdev, cap) \
1126 MLX5_GET(roce_cap, mdev->caps.hca_cur[MLX5_CAP_ROCE], cap)
1127
1128#define MLX5_CAP_ROCE_MAX(mdev, cap) \
1129 MLX5_GET(roce_cap, mdev->caps.hca_max[MLX5_CAP_ROCE], cap)
1130
1131#define MLX5_CAP_ATOMIC(mdev, cap) \
1132 MLX5_GET(atomic_caps, mdev->caps.hca_cur[MLX5_CAP_ATOMIC], cap)
1133
1134#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1135 MLX5_GET(atomic_caps, mdev->caps.hca_max[MLX5_CAP_ATOMIC], cap)
1136
1137#define MLX5_CAP_FLOWTABLE(mdev, cap) \
1138 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
1139
1140#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1141 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap)
1142
1143#define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
1144 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1145
1146#define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
1147 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1148
1149#define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \
1150 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap)
1151
1152#define MLX5_CAP_FLOWTABLE_NIC_TX_MAX(mdev, cap) \
1153 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit.cap)
1154
1155#define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
1156 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1157
1158#define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \
1159 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
1160
1161#define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
1162 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1163
1164#define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \
1165 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1166
1167#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1168 MLX5_GET(flow_table_eswitch_cap, \
1169 mdev->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1170
1171#define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1172 MLX5_GET(flow_table_eswitch_cap, \
1173 mdev->caps.hca_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1174
1175#define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1176 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1177
1178#define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1179 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1180
1181#define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1182 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1183
1184#define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1185 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1186
1187#define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1188 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1189
1190#define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1191 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1192
1193#define MLX5_CAP_ESW(mdev, cap) \
1194 MLX5_GET(e_switch_cap, \
1195 mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap)
1196
1197#define MLX5_CAP_ESW_MAX(mdev, cap) \
1198 MLX5_GET(e_switch_cap, \
1199 mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap)
1200
1201#define MLX5_CAP_ODP(mdev, cap)\
1202 MLX5_GET(odp_cap, mdev->caps.hca_cur[MLX5_CAP_ODP], cap)
1203
1204#define MLX5_CAP_VECTOR_CALC(mdev, cap) \
1205 MLX5_GET(vector_calc_cap, \
1206 mdev->caps.hca_cur[MLX5_CAP_VECTOR_CALC], cap)
1207
1208#define MLX5_CAP_QOS(mdev, cap)\
1209 MLX5_GET(qos_cap, mdev->caps.hca_cur[MLX5_CAP_QOS], cap)
1210
1211#define MLX5_CAP_DEBUG(mdev, cap)\
1212 MLX5_GET(debug_cap, mdev->caps.hca_cur[MLX5_CAP_DEBUG], cap)
1213
1214#define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
1215 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1216
1217#define MLX5_CAP_PCAM_REG(mdev, reg) \
1218 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
1219
1220#define MLX5_CAP_MCAM_REG(mdev, reg) \
1221 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
1222
1223#define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
1224 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1225
1226#define MLX5_CAP_QCAM_REG(mdev, fld) \
1227 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1228
1229#define MLX5_CAP_QCAM_FEATURE(mdev, fld) \
1230 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1231
1232#define MLX5_CAP_FPGA(mdev, cap) \
1233 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1234
1235#define MLX5_CAP64_FPGA(mdev, cap) \
1236 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1237
1238#define MLX5_CAP_DEV_MEM(mdev, cap)\
1239 MLX5_GET(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)
1240
1241#define MLX5_CAP64_DEV_MEM(mdev, cap)\
1242 MLX5_GET64(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)
1243
1244enum {
1245 MLX5_CMD_STAT_OK = 0x0,
1246 MLX5_CMD_STAT_INT_ERR = 0x1,
1247 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1248 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1249 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1250 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1251 MLX5_CMD_STAT_RES_BUSY = 0x6,
1252 MLX5_CMD_STAT_LIM_ERR = 0x8,
1253 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1254 MLX5_CMD_STAT_IX_ERR = 0xa,
1255 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1256 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1257 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1258 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1259 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1260 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1261};
1262
1263enum {
1264 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1265 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1266 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1267 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1268 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1269 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1270 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1271 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
1272 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
1273 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
1274};
1275
1276enum {
1277 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0,
1278};
1279
1280static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1281{
1282 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1283 return 0;
1284 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1285}
1286
1287#define MLX5_BY_PASS_NUM_REGULAR_PRIOS 16
1288#define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 16
1289#define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1290#define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1291 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1292 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
1293
1294#endif /* MLX5_DEVICE_H */