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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Driver for the MMC / SD / SDIO cell found in:
4 *
5 * TC6393XB TC6391XB TC6387XB T7L66XB ASIC3
6 *
7 * Copyright (C) 2015-17 Renesas Electronics Corporation
8 * Copyright (C) 2016-17 Sang Engineering, Wolfram Sang
9 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
10 * Copyright (C) 2007 Ian Molton
11 * Copyright (C) 2004 Ian Molton
12 */
13
14#ifndef TMIO_MMC_H
15#define TMIO_MMC_H
16
17#include <linux/dmaengine.h>
18#include <linux/highmem.h>
19#include <linux/mutex.h>
20#include <linux/pagemap.h>
21#include <linux/scatterlist.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24
25#define CTL_SD_CMD 0x00
26#define CTL_ARG_REG 0x04
27#define CTL_STOP_INTERNAL_ACTION 0x08
28#define CTL_XFER_BLK_COUNT 0xa
29#define CTL_RESPONSE 0x0c
30/* driver merges STATUS and following STATUS2 */
31#define CTL_STATUS 0x1c
32/* driver merges IRQ_MASK and following IRQ_MASK2 */
33#define CTL_IRQ_MASK 0x20
34#define CTL_SD_CARD_CLK_CTL 0x24
35#define CTL_SD_XFER_LEN 0x26
36#define CTL_SD_MEM_CARD_OPT 0x28
37#define CTL_SD_ERROR_DETAIL_STATUS 0x2c
38#define CTL_SD_DATA_PORT 0x30
39#define CTL_TRANSACTION_CTL 0x34
40#define CTL_SDIO_STATUS 0x36
41#define CTL_SDIO_IRQ_MASK 0x38
42#define CTL_DMA_ENABLE 0xd8
43#define CTL_RESET_SD 0xe0
44#define CTL_VERSION 0xe2
45#define CTL_SDIF_MODE 0xe6
46
47/* Definitions for values the CTL_STOP_INTERNAL_ACTION register can take */
48#define TMIO_STOP_STP BIT(0)
49#define TMIO_STOP_SEC BIT(8)
50
51/* Definitions for values the CTL_STATUS register can take */
52#define TMIO_STAT_CMDRESPEND BIT(0)
53#define TMIO_STAT_DATAEND BIT(2)
54#define TMIO_STAT_CARD_REMOVE BIT(3)
55#define TMIO_STAT_CARD_INSERT BIT(4)
56#define TMIO_STAT_SIGSTATE BIT(5)
57#define TMIO_STAT_WRPROTECT BIT(7)
58#define TMIO_STAT_CARD_REMOVE_A BIT(8)
59#define TMIO_STAT_CARD_INSERT_A BIT(9)
60#define TMIO_STAT_SIGSTATE_A BIT(10)
61
62/* These belong technically to CTL_STATUS2, but the driver merges them */
63#define TMIO_STAT_CMD_IDX_ERR BIT(16)
64#define TMIO_STAT_CRCFAIL BIT(17)
65#define TMIO_STAT_STOPBIT_ERR BIT(18)
66#define TMIO_STAT_DATATIMEOUT BIT(19)
67#define TMIO_STAT_RXOVERFLOW BIT(20)
68#define TMIO_STAT_TXUNDERRUN BIT(21)
69#define TMIO_STAT_CMDTIMEOUT BIT(22)
70#define TMIO_STAT_DAT0 BIT(23) /* only known on R-Car so far */
71#define TMIO_STAT_RXRDY BIT(24)
72#define TMIO_STAT_TXRQ BIT(25)
73#define TMIO_STAT_ALWAYS_SET_27 BIT(27) /* only known on R-Car 2+ so far */
74#define TMIO_STAT_ILL_FUNC BIT(29) /* only when !TMIO_MMC_HAS_IDLE_WAIT */
75#define TMIO_STAT_SCLKDIVEN BIT(29) /* only when TMIO_MMC_HAS_IDLE_WAIT */
76#define TMIO_STAT_CMD_BUSY BIT(30)
77#define TMIO_STAT_ILL_ACCESS BIT(31)
78
79/* Definitions for values the CTL_SD_CARD_CLK_CTL register can take */
80#define CLK_CTL_DIV_MASK 0xff
81#define CLK_CTL_SCLKEN BIT(8)
82
83/* Definitions for values the CTL_SD_MEM_CARD_OPT register can take */
84#define CARD_OPT_WIDTH8 BIT(13)
85#define CARD_OPT_WIDTH BIT(15)
86
87/* Definitions for values the CTL_SDIO_STATUS register can take */
88#define TMIO_SDIO_STAT_IOIRQ 0x0001
89#define TMIO_SDIO_STAT_EXPUB52 0x4000
90#define TMIO_SDIO_STAT_EXWT 0x8000
91#define TMIO_SDIO_MASK_ALL 0xc007
92
93#define TMIO_SDIO_SETBITS_MASK 0x0006
94
95/* Definitions for values the CTL_DMA_ENABLE register can take */
96#define DMA_ENABLE_DMASDRW BIT(1)
97
98/* Define some IRQ masks */
99/* This is the mask used at reset by the chip */
100#define TMIO_MASK_INIT_RCAR2 0x8b7f031d /* Initial value for R-Car Gen2+ */
101#define TMIO_MASK_ALL 0x837f031d
102#define TMIO_MASK_READOP (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND)
103#define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND)
104#define TMIO_MASK_CMD (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT | \
105 TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT)
106#define TMIO_MASK_IRQ (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD)
107
108struct tmio_mmc_data;
109struct tmio_mmc_host;
110
111struct tmio_mmc_dma_ops {
112 void (*start)(struct tmio_mmc_host *host, struct mmc_data *data);
113 void (*enable)(struct tmio_mmc_host *host, bool enable);
114 void (*request)(struct tmio_mmc_host *host,
115 struct tmio_mmc_data *pdata);
116 void (*release)(struct tmio_mmc_host *host);
117 void (*abort)(struct tmio_mmc_host *host);
118 void (*dataend)(struct tmio_mmc_host *host);
119};
120
121struct tmio_mmc_host {
122 void __iomem *ctl;
123 struct mmc_command *cmd;
124 struct mmc_request *mrq;
125 struct mmc_data *data;
126 struct mmc_host *mmc;
127 struct mmc_host_ops ops;
128
129 /* Callbacks for clock / power control */
130 void (*set_pwr)(struct platform_device *host, int state);
131
132 /* pio related stuff */
133 struct scatterlist *sg_ptr;
134 struct scatterlist *sg_orig;
135 unsigned int sg_len;
136 unsigned int sg_off;
137 unsigned int bus_shift;
138
139 struct platform_device *pdev;
140 struct tmio_mmc_data *pdata;
141
142 /* DMA support */
143 bool dma_on;
144 struct dma_chan *chan_rx;
145 struct dma_chan *chan_tx;
146 struct tasklet_struct dma_issue;
147 struct scatterlist bounce_sg;
148 u8 *bounce_buf;
149
150 /* Track lost interrupts */
151 struct delayed_work delayed_reset_work;
152 struct work_struct done;
153
154 /* Cache */
155 u32 sdcard_irq_mask;
156 u32 sdio_irq_mask;
157 unsigned int clk_cache;
158 u32 sdcard_irq_setbit_mask;
159
160 spinlock_t lock; /* protect host private data */
161 unsigned long last_req_ts;
162 struct mutex ios_lock; /* protect set_ios() context */
163 bool native_hotplug;
164 bool sdio_irq_enabled;
165
166 /* Mandatory callback */
167 int (*clk_enable)(struct tmio_mmc_host *host);
168 void (*set_clock)(struct tmio_mmc_host *host, unsigned int clock);
169
170 /* Optional callbacks */
171 void (*clk_disable)(struct tmio_mmc_host *host);
172 int (*multi_io_quirk)(struct mmc_card *card,
173 unsigned int direction, int blk_size);
174 int (*write16_hook)(struct tmio_mmc_host *host, int addr);
175 void (*reset)(struct tmio_mmc_host *host);
176 void (*hw_reset)(struct tmio_mmc_host *host);
177 void (*prepare_tuning)(struct tmio_mmc_host *host, unsigned long tap);
178 bool (*check_scc_error)(struct tmio_mmc_host *host);
179
180 /*
181 * Mandatory callback for tuning to occur which is optional for SDR50
182 * and mandatory for SDR104.
183 */
184 unsigned int (*init_tuning)(struct tmio_mmc_host *host);
185 int (*select_tuning)(struct tmio_mmc_host *host);
186
187 /* Tuning values: 1 for success, 0 for failure */
188 DECLARE_BITMAP(taps, BITS_PER_BYTE * sizeof(long));
189 unsigned int tap_num;
190 unsigned long tap_set;
191
192 void (*prepare_hs400_tuning)(struct tmio_mmc_host *host);
193 void (*hs400_downgrade)(struct tmio_mmc_host *host);
194 void (*hs400_complete)(struct tmio_mmc_host *host);
195
196 const struct tmio_mmc_dma_ops *dma_ops;
197};
198
199struct tmio_mmc_host *tmio_mmc_host_alloc(struct platform_device *pdev,
200 struct tmio_mmc_data *pdata);
201void tmio_mmc_host_free(struct tmio_mmc_host *host);
202int tmio_mmc_host_probe(struct tmio_mmc_host *host);
203void tmio_mmc_host_remove(struct tmio_mmc_host *host);
204void tmio_mmc_do_data_irq(struct tmio_mmc_host *host);
205
206void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
207void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
208irqreturn_t tmio_mmc_irq(int irq, void *devid);
209
210static inline char *tmio_mmc_kmap_atomic(struct scatterlist *sg,
211 unsigned long *flags)
212{
213 local_irq_save(*flags);
214 return kmap_atomic(sg_page(sg)) + sg->offset;
215}
216
217static inline void tmio_mmc_kunmap_atomic(struct scatterlist *sg,
218 unsigned long *flags, void *virt)
219{
220 kunmap_atomic(virt - sg->offset);
221 local_irq_restore(*flags);
222}
223
224#ifdef CONFIG_PM
225int tmio_mmc_host_runtime_suspend(struct device *dev);
226int tmio_mmc_host_runtime_resume(struct device *dev);
227#endif
228
229static inline u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr)
230{
231 return ioread16(host->ctl + (addr << host->bus_shift));
232}
233
234static inline void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr,
235 u16 *buf, int count)
236{
237 ioread16_rep(host->ctl + (addr << host->bus_shift), buf, count);
238}
239
240static inline u32 sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host *host,
241 int addr)
242{
243 return ioread16(host->ctl + (addr << host->bus_shift)) |
244 ioread16(host->ctl + ((addr + 2) << host->bus_shift)) << 16;
245}
246
247static inline void sd_ctrl_read32_rep(struct tmio_mmc_host *host, int addr,
248 u32 *buf, int count)
249{
250 ioread32_rep(host->ctl + (addr << host->bus_shift), buf, count);
251}
252
253static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr,
254 u16 val)
255{
256 /* If there is a hook and it returns non-zero then there
257 * is an error and the write should be skipped
258 */
259 if (host->write16_hook && host->write16_hook(host, addr))
260 return;
261 iowrite16(val, host->ctl + (addr << host->bus_shift));
262}
263
264static inline void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,
265 u16 *buf, int count)
266{
267 iowrite16_rep(host->ctl + (addr << host->bus_shift), buf, count);
268}
269
270static inline void sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host *host,
271 int addr, u32 val)
272{
273 if (addr == CTL_IRQ_MASK || addr == CTL_STATUS)
274 val |= host->sdcard_irq_setbit_mask;
275
276 iowrite16(val & 0xffff, host->ctl + (addr << host->bus_shift));
277 iowrite16(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
278}
279
280static inline void sd_ctrl_write32(struct tmio_mmc_host *host, int addr, u32 val)
281{
282 iowrite32(val, host->ctl + (addr << host->bus_shift));
283}
284
285static inline void sd_ctrl_write32_rep(struct tmio_mmc_host *host, int addr,
286 const u32 *buf, int count)
287{
288 iowrite32_rep(host->ctl + (addr << host->bus_shift), buf, count);
289}
290
291#endif