tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __ATMEL_ISC_REGS_H
3#define __ATMEL_ISC_REGS_H
4
5#include <linux/bitops.h>
6
7/* ISC Control Enable Register 0 */
8#define ISC_CTRLEN 0x00000000
9
10/* ISC Control Disable Register 0 */
11#define ISC_CTRLDIS 0x00000004
12
13/* ISC Control Status Register 0 */
14#define ISC_CTRLSR 0x00000008
15
16#define ISC_CTRL_CAPTURE BIT(0)
17#define ISC_CTRL_UPPRO BIT(1)
18#define ISC_CTRL_HISREQ BIT(2)
19#define ISC_CTRL_HISCLR BIT(3)
20
21/* ISC Parallel Front End Configuration 0 Register */
22#define ISC_PFE_CFG0 0x0000000c
23
24#define ISC_PFE_CFG0_HPOL_LOW BIT(0)
25#define ISC_PFE_CFG0_VPOL_LOW BIT(1)
26#define ISC_PFE_CFG0_PPOL_LOW BIT(2)
27
28#define ISC_PFE_CFG0_MODE_PROGRESSIVE (0x0 << 4)
29#define ISC_PFE_CFG0_MODE_MASK GENMASK(6, 4)
30
31#define ISC_PFE_CFG0_BPS_EIGHT (0x4 << 28)
32#define ISC_PFG_CFG0_BPS_NINE (0x3 << 28)
33#define ISC_PFG_CFG0_BPS_TEN (0x2 << 28)
34#define ISC_PFG_CFG0_BPS_ELEVEN (0x1 << 28)
35#define ISC_PFG_CFG0_BPS_TWELVE (0x0 << 28)
36#define ISC_PFE_CFG0_BPS_MASK GENMASK(30, 28)
37
38/* ISC Clock Enable Register */
39#define ISC_CLKEN 0x00000018
40
41/* ISC Clock Disable Register */
42#define ISC_CLKDIS 0x0000001c
43
44/* ISC Clock Status Register */
45#define ISC_CLKSR 0x00000020
46#define ISC_CLKSR_SIP BIT(31)
47
48#define ISC_CLK(n) BIT(n)
49
50/* ISC Clock Configuration Register */
51#define ISC_CLKCFG 0x00000024
52#define ISC_CLKCFG_DIV_SHIFT(n) ((n)*16)
53#define ISC_CLKCFG_DIV_MASK(n) GENMASK(((n)*16 + 7), (n)*16)
54#define ISC_CLKCFG_SEL_SHIFT(n) ((n)*16 + 8)
55#define ISC_CLKCFG_SEL_MASK(n) GENMASK(((n)*17 + 8), ((n)*16 + 8))
56
57/* ISC Interrupt Enable Register */
58#define ISC_INTEN 0x00000028
59
60/* ISC Interrupt Disable Register */
61#define ISC_INTDIS 0x0000002c
62
63/* ISC Interrupt Mask Register */
64#define ISC_INTMASK 0x00000030
65
66/* ISC Interrupt Status Register */
67#define ISC_INTSR 0x00000034
68
69#define ISC_INT_DDONE BIT(8)
70#define ISC_INT_HISDONE BIT(12)
71
72/* ISC White Balance Control Register */
73#define ISC_WB_CTRL 0x00000058
74
75/* ISC White Balance Configuration Register */
76#define ISC_WB_CFG 0x0000005c
77
78/* ISC White Balance Offset for R, GR Register */
79#define ISC_WB_O_RGR 0x00000060
80
81/* ISC White Balance Offset for B, GB Register */
82#define ISC_WB_O_BGR 0x00000064
83
84/* ISC White Balance Gain for R, GR Register */
85#define ISC_WB_G_RGR 0x00000068
86
87/* ISC White Balance Gain for B, GB Register */
88#define ISC_WB_G_BGR 0x0000006c
89
90/* ISC Color Filter Array Control Register */
91#define ISC_CFA_CTRL 0x00000070
92
93/* ISC Color Filter Array Configuration Register */
94#define ISC_CFA_CFG 0x00000074
95#define ISC_CFA_CFG_EITPOL BIT(4)
96
97#define ISC_BAY_CFG_GRGR 0x0
98#define ISC_BAY_CFG_RGRG 0x1
99#define ISC_BAY_CFG_GBGB 0x2
100#define ISC_BAY_CFG_BGBG 0x3
101
102/* ISC Color Correction Control Register */
103#define ISC_CC_CTRL 0x00000078
104
105/* ISC Color Correction RR RG Register */
106#define ISC_CC_RR_RG 0x0000007c
107
108/* ISC Color Correction RB OR Register */
109#define ISC_CC_RB_OR 0x00000080
110
111/* ISC Color Correction GR GG Register */
112#define ISC_CC_GR_GG 0x00000084
113
114/* ISC Color Correction GB OG Register */
115#define ISC_CC_GB_OG 0x00000088
116
117/* ISC Color Correction BR BG Register */
118#define ISC_CC_BR_BG 0x0000008c
119
120/* ISC Color Correction BB OB Register */
121#define ISC_CC_BB_OB 0x00000090
122
123/* ISC Gamma Correction Control Register */
124#define ISC_GAM_CTRL 0x00000094
125
126/* ISC_Gamma Correction Blue Entry Register */
127#define ISC_GAM_BENTRY 0x00000098
128
129/* ISC_Gamma Correction Green Entry Register */
130#define ISC_GAM_GENTRY 0x00000198
131
132/* ISC_Gamma Correction Green Entry Register */
133#define ISC_GAM_RENTRY 0x00000298
134
135/* Color Space Conversion Control Register */
136#define ISC_CSC_CTRL 0x00000398
137
138/* Color Space Conversion YR YG Register */
139#define ISC_CSC_YR_YG 0x0000039c
140
141/* Color Space Conversion YB OY Register */
142#define ISC_CSC_YB_OY 0x000003a0
143
144/* Color Space Conversion CBR CBG Register */
145#define ISC_CSC_CBR_CBG 0x000003a4
146
147/* Color Space Conversion CBB OCB Register */
148#define ISC_CSC_CBB_OCB 0x000003a8
149
150/* Color Space Conversion CRR CRG Register */
151#define ISC_CSC_CRR_CRG 0x000003ac
152
153/* Color Space Conversion CRB OCR Register */
154#define ISC_CSC_CRB_OCR 0x000003b0
155
156/* Contrast And Brightness Control Register */
157#define ISC_CBC_CTRL 0x000003b4
158
159/* Contrast And Brightness Configuration Register */
160#define ISC_CBC_CFG 0x000003b8
161
162/* Brightness Register */
163#define ISC_CBC_BRIGHT 0x000003bc
164#define ISC_CBC_BRIGHT_MASK GENMASK(10, 0)
165
166/* Contrast Register */
167#define ISC_CBC_CONTRAST 0x000003c0
168#define ISC_CBC_CONTRAST_MASK GENMASK(11, 0)
169
170/* Subsampling 4:4:4 to 4:2:2 Control Register */
171#define ISC_SUB422_CTRL 0x000003c4
172
173/* Subsampling 4:2:2 to 4:2:0 Control Register */
174#define ISC_SUB420_CTRL 0x000003cc
175
176/* Rounding, Limiting and Packing Configuration Register */
177#define ISC_RLP_CFG 0x000003d0
178
179#define ISC_RLP_CFG_MODE_DAT8 0x0
180#define ISC_RLP_CFG_MODE_DAT9 0x1
181#define ISC_RLP_CFG_MODE_DAT10 0x2
182#define ISC_RLP_CFG_MODE_DAT11 0x3
183#define ISC_RLP_CFG_MODE_DAT12 0x4
184#define ISC_RLP_CFG_MODE_DATY8 0x5
185#define ISC_RLP_CFG_MODE_DATY10 0x6
186#define ISC_RLP_CFG_MODE_ARGB444 0x7
187#define ISC_RLP_CFG_MODE_ARGB555 0x8
188#define ISC_RLP_CFG_MODE_RGB565 0x9
189#define ISC_RLP_CFG_MODE_ARGB32 0xa
190#define ISC_RLP_CFG_MODE_YYCC 0xb
191#define ISC_RLP_CFG_MODE_YYCC_LIMITED 0xc
192#define ISC_RLP_CFG_MODE_MASK GENMASK(3, 0)
193
194/* Histogram Control Register */
195#define ISC_HIS_CTRL 0x000003d4
196
197#define ISC_HIS_CTRL_EN BIT(0)
198#define ISC_HIS_CTRL_DIS 0x0
199
200/* Histogram Configuration Register */
201#define ISC_HIS_CFG 0x000003d8
202
203#define ISC_HIS_CFG_MODE_GR 0x0
204#define ISC_HIS_CFG_MODE_R 0x1
205#define ISC_HIS_CFG_MODE_GB 0x2
206#define ISC_HIS_CFG_MODE_B 0x3
207#define ISC_HIS_CFG_MODE_Y 0x4
208#define ISC_HIS_CFG_MODE_RAW 0x5
209#define ISC_HIS_CFG_MODE_YCCIR656 0x6
210
211#define ISC_HIS_CFG_BAYSEL_SHIFT 4
212
213#define ISC_HIS_CFG_RAR BIT(8)
214
215/* DMA Configuration Register */
216#define ISC_DCFG 0x000003e0
217#define ISC_DCFG_IMODE_PACKED8 0x0
218#define ISC_DCFG_IMODE_PACKED16 0x1
219#define ISC_DCFG_IMODE_PACKED32 0x2
220#define ISC_DCFG_IMODE_YC422SP 0x3
221#define ISC_DCFG_IMODE_YC422P 0x4
222#define ISC_DCFG_IMODE_YC420SP 0x5
223#define ISC_DCFG_IMODE_YC420P 0x6
224#define ISC_DCFG_IMODE_MASK GENMASK(2, 0)
225
226#define ISC_DCFG_YMBSIZE_SINGLE (0x0 << 4)
227#define ISC_DCFG_YMBSIZE_BEATS4 (0x1 << 4)
228#define ISC_DCFG_YMBSIZE_BEATS8 (0x2 << 4)
229#define ISC_DCFG_YMBSIZE_BEATS16 (0x3 << 4)
230#define ISC_DCFG_YMBSIZE_MASK GENMASK(5, 4)
231
232#define ISC_DCFG_CMBSIZE_SINGLE (0x0 << 8)
233#define ISC_DCFG_CMBSIZE_BEATS4 (0x1 << 8)
234#define ISC_DCFG_CMBSIZE_BEATS8 (0x2 << 8)
235#define ISC_DCFG_CMBSIZE_BEATS16 (0x3 << 8)
236#define ISC_DCFG_CMBSIZE_MASK GENMASK(9, 8)
237
238/* DMA Control Register */
239#define ISC_DCTRL 0x000003e4
240
241#define ISC_DCTRL_DVIEW_PACKED (0x0 << 1)
242#define ISC_DCTRL_DVIEW_SEMIPLANAR (0x1 << 1)
243#define ISC_DCTRL_DVIEW_PLANAR (0x2 << 1)
244#define ISC_DCTRL_DVIEW_MASK GENMASK(2, 1)
245
246#define ISC_DCTRL_IE_IS (0x0 << 4)
247
248/* DMA Descriptor Address Register */
249#define ISC_DNDA 0x000003e8
250
251/* DMA Address 0 Register */
252#define ISC_DAD0 0x000003ec
253
254/* DMA Address 1 Register */
255#define ISC_DAD1 0x000003f4
256
257/* DMA Address 2 Register */
258#define ISC_DAD2 0x000003fc
259
260/* Histogram Entry */
261#define ISC_HIS_ENTRY 0x00000410
262
263#endif