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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * CAAM hardware register-level view
4 *
5 * Copyright 2008-2011 Freescale Semiconductor, Inc.
6 * Copyright 2018 NXP
7 */
8
9#ifndef REGS_H
10#define REGS_H
11
12#include <linux/types.h>
13#include <linux/bitops.h>
14#include <linux/io.h>
15
16/*
17 * Architecture-specific register access methods
18 *
19 * CAAM's bus-addressable registers are 64 bits internally.
20 * They have been wired to be safely accessible on 32-bit
21 * architectures, however. Registers were organized such
22 * that (a) they can be contained in 32 bits, (b) if not, then they
23 * can be treated as two 32-bit entities, or finally (c) if they
24 * must be treated as a single 64-bit value, then this can safely
25 * be done with two 32-bit cycles.
26 *
27 * For 32-bit operations on 64-bit values, CAAM follows the same
28 * 64-bit register access conventions as it's predecessors, in that
29 * writes are "triggered" by a write to the register at the numerically
30 * higher address, thus, a full 64-bit write cycle requires a write
31 * to the lower address, followed by a write to the higher address,
32 * which will latch/execute the write cycle.
33 *
34 * For example, let's assume a SW reset of CAAM through the master
35 * configuration register.
36 * - SWRST is in bit 31 of MCFG.
37 * - MCFG begins at base+0x0000.
38 * - Bits 63-32 are a 32-bit word at base+0x0000 (numerically-lower)
39 * - Bits 31-0 are a 32-bit word at base+0x0004 (numerically-higher)
40 *
41 * (and on Power, the convention is 0-31, 32-63, I know...)
42 *
43 * Assuming a 64-bit write to this MCFG to perform a software reset
44 * would then require a write of 0 to base+0x0000, followed by a
45 * write of 0x80000000 to base+0x0004, which would "execute" the
46 * reset.
47 *
48 * Of course, since MCFG 63-32 is all zero, we could cheat and simply
49 * write 0x8000000 to base+0x0004, and the reset would work fine.
50 * However, since CAAM does contain some write-and-read-intended
51 * 64-bit registers, this code defines 64-bit access methods for
52 * the sake of internal consistency and simplicity, and so that a
53 * clean transition to 64-bit is possible when it becomes necessary.
54 *
55 * There are limitations to this that the developer must recognize.
56 * 32-bit architectures cannot enforce an atomic-64 operation,
57 * Therefore:
58 *
59 * - On writes, since the HW is assumed to latch the cycle on the
60 * write of the higher-numeric-address word, then ordered
61 * writes work OK.
62 *
63 * - For reads, where a register contains a relevant value of more
64 * that 32 bits, the hardware employs logic to latch the other
65 * "half" of the data until read, ensuring an accurate value.
66 * This is of particular relevance when dealing with CAAM's
67 * performance counters.
68 *
69 */
70
71extern bool caam_little_end;
72extern bool caam_imx;
73
74#define caam_to_cpu(len) \
75static inline u##len caam##len ## _to_cpu(u##len val) \
76{ \
77 if (caam_little_end) \
78 return le##len ## _to_cpu((__force __le##len)val); \
79 else \
80 return be##len ## _to_cpu((__force __be##len)val); \
81}
82
83#define cpu_to_caam(len) \
84static inline u##len cpu_to_caam##len(u##len val) \
85{ \
86 if (caam_little_end) \
87 return (__force u##len)cpu_to_le##len(val); \
88 else \
89 return (__force u##len)cpu_to_be##len(val); \
90}
91
92caam_to_cpu(16)
93caam_to_cpu(32)
94caam_to_cpu(64)
95cpu_to_caam(16)
96cpu_to_caam(32)
97cpu_to_caam(64)
98
99static inline void wr_reg32(void __iomem *reg, u32 data)
100{
101 if (caam_little_end)
102 iowrite32(data, reg);
103 else
104 iowrite32be(data, reg);
105}
106
107static inline u32 rd_reg32(void __iomem *reg)
108{
109 if (caam_little_end)
110 return ioread32(reg);
111
112 return ioread32be(reg);
113}
114
115static inline void clrsetbits_32(void __iomem *reg, u32 clear, u32 set)
116{
117 if (caam_little_end)
118 iowrite32((ioread32(reg) & ~clear) | set, reg);
119 else
120 iowrite32be((ioread32be(reg) & ~clear) | set, reg);
121}
122
123/*
124 * The only users of these wr/rd_reg64 functions is the Job Ring (JR).
125 * The DMA address registers in the JR are handled differently depending on
126 * platform:
127 *
128 * 1. All BE CAAM platforms and i.MX platforms (LE CAAM):
129 *
130 * base + 0x0000 : most-significant 32 bits
131 * base + 0x0004 : least-significant 32 bits
132 *
133 * The 32-bit version of this core therefore has to write to base + 0x0004
134 * to set the 32-bit wide DMA address.
135 *
136 * 2. All other LE CAAM platforms (LS1021A etc.)
137 * base + 0x0000 : least-significant 32 bits
138 * base + 0x0004 : most-significant 32 bits
139 */
140#ifdef CONFIG_64BIT
141static inline void wr_reg64(void __iomem *reg, u64 data)
142{
143 if (caam_little_end)
144 iowrite64(data, reg);
145 else
146 iowrite64be(data, reg);
147}
148
149static inline u64 rd_reg64(void __iomem *reg)
150{
151 if (caam_little_end)
152 return ioread64(reg);
153 else
154 return ioread64be(reg);
155}
156
157#else /* CONFIG_64BIT */
158static inline void wr_reg64(void __iomem *reg, u64 data)
159{
160 if (!caam_imx && caam_little_end) {
161 wr_reg32((u32 __iomem *)(reg) + 1, data >> 32);
162 wr_reg32((u32 __iomem *)(reg), data);
163 } else {
164 wr_reg32((u32 __iomem *)(reg), data >> 32);
165 wr_reg32((u32 __iomem *)(reg) + 1, data);
166 }
167}
168
169static inline u64 rd_reg64(void __iomem *reg)
170{
171 if (!caam_imx && caam_little_end)
172 return ((u64)rd_reg32((u32 __iomem *)(reg) + 1) << 32 |
173 (u64)rd_reg32((u32 __iomem *)(reg)));
174
175 return ((u64)rd_reg32((u32 __iomem *)(reg)) << 32 |
176 (u64)rd_reg32((u32 __iomem *)(reg) + 1));
177}
178#endif /* CONFIG_64BIT */
179
180static inline u64 cpu_to_caam_dma64(dma_addr_t value)
181{
182 if (caam_imx)
183 return (((u64)cpu_to_caam32(lower_32_bits(value)) << 32) |
184 (u64)cpu_to_caam32(upper_32_bits(value)));
185
186 return cpu_to_caam64(value);
187}
188
189static inline u64 caam_dma64_to_cpu(u64 value)
190{
191 if (caam_imx)
192 return (((u64)caam32_to_cpu(lower_32_bits(value)) << 32) |
193 (u64)caam32_to_cpu(upper_32_bits(value)));
194
195 return caam64_to_cpu(value);
196}
197
198#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
199#define cpu_to_caam_dma(value) cpu_to_caam_dma64(value)
200#define caam_dma_to_cpu(value) caam_dma64_to_cpu(value)
201#else
202#define cpu_to_caam_dma(value) cpu_to_caam32(value)
203#define caam_dma_to_cpu(value) caam32_to_cpu(value)
204#endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT */
205
206/*
207 * jr_outentry
208 * Represents each entry in a JobR output ring
209 */
210struct jr_outentry {
211 dma_addr_t desc;/* Pointer to completed descriptor */
212 u32 jrstatus; /* Status for completed descriptor */
213} __packed;
214
215/* Version registers (Era 10+) e80-eff */
216struct version_regs {
217 u32 crca; /* CRCA_VERSION */
218 u32 afha; /* AFHA_VERSION */
219 u32 kfha; /* KFHA_VERSION */
220 u32 pkha; /* PKHA_VERSION */
221 u32 aesa; /* AESA_VERSION */
222 u32 mdha; /* MDHA_VERSION */
223 u32 desa; /* DESA_VERSION */
224 u32 snw8a; /* SNW8A_VERSION */
225 u32 snw9a; /* SNW9A_VERSION */
226 u32 zuce; /* ZUCE_VERSION */
227 u32 zuca; /* ZUCA_VERSION */
228 u32 ccha; /* CCHA_VERSION */
229 u32 ptha; /* PTHA_VERSION */
230 u32 rng; /* RNG_VERSION */
231 u32 trng; /* TRNG_VERSION */
232 u32 aaha; /* AAHA_VERSION */
233 u32 rsvd[10];
234 u32 sr; /* SR_VERSION */
235 u32 dma; /* DMA_VERSION */
236 u32 ai; /* AI_VERSION */
237 u32 qi; /* QI_VERSION */
238 u32 jr; /* JR_VERSION */
239 u32 deco; /* DECO_VERSION */
240};
241
242/* Version registers bitfields */
243
244/* Number of CHAs instantiated */
245#define CHA_VER_NUM_MASK 0xffull
246/* CHA Miscellaneous Information */
247#define CHA_VER_MISC_SHIFT 8
248#define CHA_VER_MISC_MASK (0xffull << CHA_VER_MISC_SHIFT)
249/* CHA Revision Number */
250#define CHA_VER_REV_SHIFT 16
251#define CHA_VER_REV_MASK (0xffull << CHA_VER_REV_SHIFT)
252/* CHA Version ID */
253#define CHA_VER_VID_SHIFT 24
254#define CHA_VER_VID_MASK (0xffull << CHA_VER_VID_SHIFT)
255
256/*
257 * caam_perfmon - Performance Monitor/Secure Memory Status/
258 * CAAM Global Status/Component Version IDs
259 *
260 * Spans f00-fff wherever instantiated
261 */
262
263/* Number of DECOs */
264#define CHA_NUM_MS_DECONUM_SHIFT 24
265#define CHA_NUM_MS_DECONUM_MASK (0xfull << CHA_NUM_MS_DECONUM_SHIFT)
266
267/*
268 * CHA version IDs / instantiation bitfields (< Era 10)
269 * Defined for use with the cha_id fields in perfmon, but the same shift/mask
270 * selectors can be used to pull out the number of instantiated blocks within
271 * cha_num fields in perfmon because the locations are the same.
272 */
273#define CHA_ID_LS_AES_SHIFT 0
274#define CHA_ID_LS_AES_MASK (0xfull << CHA_ID_LS_AES_SHIFT)
275
276#define CHA_ID_LS_DES_SHIFT 4
277#define CHA_ID_LS_DES_MASK (0xfull << CHA_ID_LS_DES_SHIFT)
278
279#define CHA_ID_LS_ARC4_SHIFT 8
280#define CHA_ID_LS_ARC4_MASK (0xfull << CHA_ID_LS_ARC4_SHIFT)
281
282#define CHA_ID_LS_MD_SHIFT 12
283#define CHA_ID_LS_MD_MASK (0xfull << CHA_ID_LS_MD_SHIFT)
284
285#define CHA_ID_LS_RNG_SHIFT 16
286#define CHA_ID_LS_RNG_MASK (0xfull << CHA_ID_LS_RNG_SHIFT)
287
288#define CHA_ID_LS_SNW8_SHIFT 20
289#define CHA_ID_LS_SNW8_MASK (0xfull << CHA_ID_LS_SNW8_SHIFT)
290
291#define CHA_ID_LS_KAS_SHIFT 24
292#define CHA_ID_LS_KAS_MASK (0xfull << CHA_ID_LS_KAS_SHIFT)
293
294#define CHA_ID_LS_PK_SHIFT 28
295#define CHA_ID_LS_PK_MASK (0xfull << CHA_ID_LS_PK_SHIFT)
296
297#define CHA_ID_MS_CRC_SHIFT 0
298#define CHA_ID_MS_CRC_MASK (0xfull << CHA_ID_MS_CRC_SHIFT)
299
300#define CHA_ID_MS_SNW9_SHIFT 4
301#define CHA_ID_MS_SNW9_MASK (0xfull << CHA_ID_MS_SNW9_SHIFT)
302
303#define CHA_ID_MS_DECO_SHIFT 24
304#define CHA_ID_MS_DECO_MASK (0xfull << CHA_ID_MS_DECO_SHIFT)
305
306#define CHA_ID_MS_JR_SHIFT 28
307#define CHA_ID_MS_JR_MASK (0xfull << CHA_ID_MS_JR_SHIFT)
308
309/* Specific CHA version IDs */
310#define CHA_VER_VID_AES_LP 0x3ull
311#define CHA_VER_VID_AES_HP 0x4ull
312#define CHA_VER_VID_MD_LP256 0x0ull
313#define CHA_VER_VID_MD_LP512 0x1ull
314#define CHA_VER_VID_MD_HP 0x2ull
315
316struct sec_vid {
317 u16 ip_id;
318 u8 maj_rev;
319 u8 min_rev;
320};
321
322struct caam_perfmon {
323 /* Performance Monitor Registers f00-f9f */
324 u64 req_dequeued; /* PC_REQ_DEQ - Dequeued Requests */
325 u64 ob_enc_req; /* PC_OB_ENC_REQ - Outbound Encrypt Requests */
326 u64 ib_dec_req; /* PC_IB_DEC_REQ - Inbound Decrypt Requests */
327 u64 ob_enc_bytes; /* PC_OB_ENCRYPT - Outbound Bytes Encrypted */
328 u64 ob_prot_bytes; /* PC_OB_PROTECT - Outbound Bytes Protected */
329 u64 ib_dec_bytes; /* PC_IB_DECRYPT - Inbound Bytes Decrypted */
330 u64 ib_valid_bytes; /* PC_IB_VALIDATED Inbound Bytes Validated */
331 u64 rsvd[13];
332
333 /* CAAM Hardware Instantiation Parameters fa0-fbf */
334 u32 cha_rev_ms; /* CRNR - CHA Rev No. Most significant half*/
335 u32 cha_rev_ls; /* CRNR - CHA Rev No. Least significant half*/
336#define CTPR_MS_QI_SHIFT 25
337#define CTPR_MS_QI_MASK (0x1ull << CTPR_MS_QI_SHIFT)
338#define CTPR_MS_DPAA2 BIT(13)
339#define CTPR_MS_VIRT_EN_INCL 0x00000001
340#define CTPR_MS_VIRT_EN_POR 0x00000002
341#define CTPR_MS_PG_SZ_MASK 0x10
342#define CTPR_MS_PG_SZ_SHIFT 4
343 u32 comp_parms_ms; /* CTPR - Compile Parameters Register */
344 u32 comp_parms_ls; /* CTPR - Compile Parameters Register */
345 u64 rsvd1[2];
346
347 /* CAAM Global Status fc0-fdf */
348 u64 faultaddr; /* FAR - Fault Address */
349 u32 faultliodn; /* FALR - Fault Address LIODN */
350 u32 faultdetail; /* FADR - Fault Addr Detail */
351 u32 rsvd2;
352#define CSTA_PLEND BIT(10)
353#define CSTA_ALT_PLEND BIT(18)
354 u32 status; /* CSTA - CAAM Status */
355 u64 rsvd3;
356
357 /* Component Instantiation Parameters fe0-fff */
358 u32 rtic_id; /* RVID - RTIC Version ID */
359#define CCBVID_ERA_MASK 0xff000000
360#define CCBVID_ERA_SHIFT 24
361 u32 ccb_id; /* CCBVID - CCB Version ID */
362 u32 cha_id_ms; /* CHAVID - CHA Version ID Most Significant*/
363 u32 cha_id_ls; /* CHAVID - CHA Version ID Least Significant*/
364 u32 cha_num_ms; /* CHANUM - CHA Number Most Significant */
365 u32 cha_num_ls; /* CHANUM - CHA Number Least Significant*/
366#define SECVID_MS_IPID_MASK 0xffff0000
367#define SECVID_MS_IPID_SHIFT 16
368#define SECVID_MS_MAJ_REV_MASK 0x0000ff00
369#define SECVID_MS_MAJ_REV_SHIFT 8
370 u32 caam_id_ms; /* CAAMVID - CAAM Version ID MS */
371 u32 caam_id_ls; /* CAAMVID - CAAM Version ID LS */
372};
373
374/* LIODN programming for DMA configuration */
375#define MSTRID_LOCK_LIODN 0x80000000
376#define MSTRID_LOCK_MAKETRUSTED 0x00010000 /* only for JR masterid */
377
378#define MSTRID_LIODN_MASK 0x0fff
379struct masterid {
380 u32 liodn_ms; /* lock and make-trusted control bits */
381 u32 liodn_ls; /* LIODN for non-sequence and seq access */
382};
383
384/* Partition ID for DMA configuration */
385struct partid {
386 u32 rsvd1;
387 u32 pidr; /* partition ID, DECO */
388};
389
390/* RNGB test mode (replicated twice in some configurations) */
391/* Padded out to 0x100 */
392struct rngtst {
393 u32 mode; /* RTSTMODEx - Test mode */
394 u32 rsvd1[3];
395 u32 reset; /* RTSTRESETx - Test reset control */
396 u32 rsvd2[3];
397 u32 status; /* RTSTSSTATUSx - Test status */
398 u32 rsvd3;
399 u32 errstat; /* RTSTERRSTATx - Test error status */
400 u32 rsvd4;
401 u32 errctl; /* RTSTERRCTLx - Test error control */
402 u32 rsvd5;
403 u32 entropy; /* RTSTENTROPYx - Test entropy */
404 u32 rsvd6[15];
405 u32 verifctl; /* RTSTVERIFCTLx - Test verification control */
406 u32 rsvd7;
407 u32 verifstat; /* RTSTVERIFSTATx - Test verification status */
408 u32 rsvd8;
409 u32 verifdata; /* RTSTVERIFDx - Test verification data */
410 u32 rsvd9;
411 u32 xkey; /* RTSTXKEYx - Test XKEY */
412 u32 rsvd10;
413 u32 oscctctl; /* RTSTOSCCTCTLx - Test osc. counter control */
414 u32 rsvd11;
415 u32 oscct; /* RTSTOSCCTx - Test oscillator counter */
416 u32 rsvd12;
417 u32 oscctstat; /* RTSTODCCTSTATx - Test osc counter status */
418 u32 rsvd13[2];
419 u32 ofifo[4]; /* RTSTOFIFOx - Test output FIFO */
420 u32 rsvd14[15];
421};
422
423/* RNG4 TRNG test registers */
424struct rng4tst {
425#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
426#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in
427 both entropy shifter and
428 statistical checker */
429#define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both
430 entropy shifter and
431 statistical checker */
432#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in
433 entropy shifter, raw data
434 in statistical checker */
435#define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */
436 u32 rtmctl; /* misc. control register */
437 u32 rtscmisc; /* statistical check misc. register */
438 u32 rtpkrrng; /* poker range register */
439 union {
440 u32 rtpkrmax; /* PRGM=1: poker max. limit register */
441 u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
442 };
443#define RTSDCTL_ENT_DLY_SHIFT 16
444#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
445#define RTSDCTL_ENT_DLY_MIN 3200
446#define RTSDCTL_ENT_DLY_MAX 12800
447 u32 rtsdctl; /* seed control register */
448 union {
449 u32 rtsblim; /* PRGM=1: sparse bit limit register */
450 u32 rttotsam; /* PRGM=0: total samples register */
451 };
452 u32 rtfrqmin; /* frequency count min. limit register */
453#define RTFRQMAX_DISABLE (1 << 20)
454 union {
455 u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */
456 u32 rtfrqcnt; /* PRGM=0: freq. count register */
457 };
458 u32 rsvd1[40];
459#define RDSTA_SKVT 0x80000000
460#define RDSTA_SKVN 0x40000000
461#define RDSTA_IF0 0x00000001
462#define RDSTA_IF1 0x00000002
463#define RDSTA_IFMASK (RDSTA_IF1 | RDSTA_IF0)
464 u32 rdsta;
465 u32 rsvd2[15];
466};
467
468/*
469 * caam_ctrl - basic core configuration
470 * starts base + 0x0000 padded out to 0x1000
471 */
472
473#define KEK_KEY_SIZE 8
474#define TKEK_KEY_SIZE 8
475#define TDSK_KEY_SIZE 8
476
477#define DECO_RESET 1 /* Use with DECO reset/availability regs */
478#define DECO_RESET_0 (DECO_RESET << 0)
479#define DECO_RESET_1 (DECO_RESET << 1)
480#define DECO_RESET_2 (DECO_RESET << 2)
481#define DECO_RESET_3 (DECO_RESET << 3)
482#define DECO_RESET_4 (DECO_RESET << 4)
483
484struct caam_ctrl {
485 /* Basic Configuration Section 000-01f */
486 /* Read/Writable */
487 u32 rsvd1;
488 u32 mcr; /* MCFG Master Config Register */
489 u32 rsvd2;
490 u32 scfgr; /* SCFGR, Security Config Register */
491
492 /* Bus Access Configuration Section 010-11f */
493 /* Read/Writable */
494 struct masterid jr_mid[4]; /* JRxLIODNR - JobR LIODN setup */
495 u32 rsvd3[11];
496 u32 jrstart; /* JRSTART - Job Ring Start Register */
497 struct masterid rtic_mid[4]; /* RTICxLIODNR - RTIC LIODN setup */
498 u32 rsvd4[5];
499 u32 deco_rsr; /* DECORSR - Deco Request Source */
500 u32 rsvd11;
501 u32 deco_rq; /* DECORR - DECO Request */
502 struct partid deco_mid[5]; /* DECOxLIODNR - 1 per DECO */
503 u32 rsvd5[22];
504
505 /* DECO Availability/Reset Section 120-3ff */
506 u32 deco_avail; /* DAR - DECO availability */
507 u32 deco_reset; /* DRR - DECO reset */
508 u32 rsvd6[182];
509
510 /* Key Encryption/Decryption Configuration 400-5ff */
511 /* Read/Writable only while in Non-secure mode */
512 u32 kek[KEK_KEY_SIZE]; /* JDKEKR - Key Encryption Key */
513 u32 tkek[TKEK_KEY_SIZE]; /* TDKEKR - Trusted Desc KEK */
514 u32 tdsk[TDSK_KEY_SIZE]; /* TDSKR - Trusted Desc Signing Key */
515 u32 rsvd7[32];
516 u64 sknonce; /* SKNR - Secure Key Nonce */
517 u32 rsvd8[70];
518
519 /* RNG Test/Verification/Debug Access 600-7ff */
520 /* (Useful in Test/Debug modes only...) */
521 union {
522 struct rngtst rtst[2];
523 struct rng4tst r4tst[2];
524 };
525
526 u32 rsvd9[416];
527
528 /* Version registers - introduced with era 10 e80-eff */
529 struct version_regs vreg;
530 /* Performance Monitor f00-fff */
531 struct caam_perfmon perfmon;
532};
533
534/*
535 * Controller master config register defs
536 */
537#define MCFGR_SWRESET 0x80000000 /* software reset */
538#define MCFGR_WDENABLE 0x40000000 /* DECO watchdog enable */
539#define MCFGR_WDFAIL 0x20000000 /* DECO watchdog force-fail */
540#define MCFGR_DMA_RESET 0x10000000
541#define MCFGR_LONG_PTR 0x00010000 /* Use >32-bit desc addressing */
542#define SCFGR_RDBENABLE 0x00000400
543#define SCFGR_VIRT_EN 0x00008000
544#define DECORR_RQD0ENABLE 0x00000001 /* Enable DECO0 for direct access */
545#define DECORSR_JR0 0x00000001 /* JR to supply TZ, SDID, ICID */
546#define DECORSR_VALID 0x80000000
547#define DECORR_DEN0 0x00010000 /* DECO0 available for access*/
548
549/* AXI read cache control */
550#define MCFGR_ARCACHE_SHIFT 12
551#define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT)
552#define MCFGR_ARCACHE_BUFF (0x1 << MCFGR_ARCACHE_SHIFT)
553#define MCFGR_ARCACHE_CACH (0x2 << MCFGR_ARCACHE_SHIFT)
554#define MCFGR_ARCACHE_RALL (0x4 << MCFGR_ARCACHE_SHIFT)
555
556/* AXI write cache control */
557#define MCFGR_AWCACHE_SHIFT 8
558#define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT)
559#define MCFGR_AWCACHE_BUFF (0x1 << MCFGR_AWCACHE_SHIFT)
560#define MCFGR_AWCACHE_CACH (0x2 << MCFGR_AWCACHE_SHIFT)
561#define MCFGR_AWCACHE_WALL (0x8 << MCFGR_AWCACHE_SHIFT)
562
563/* AXI pipeline depth */
564#define MCFGR_AXIPIPE_SHIFT 4
565#define MCFGR_AXIPIPE_MASK (0xf << MCFGR_AXIPIPE_SHIFT)
566
567#define MCFGR_AXIPRI 0x00000008 /* Assert AXI priority sideband */
568#define MCFGR_LARGE_BURST 0x00000004 /* 128/256-byte burst size */
569#define MCFGR_BURST_64 0x00000001 /* 64-byte burst size */
570
571/* JRSTART register offsets */
572#define JRSTART_JR0_START 0x00000001 /* Start Job ring 0 */
573#define JRSTART_JR1_START 0x00000002 /* Start Job ring 1 */
574#define JRSTART_JR2_START 0x00000004 /* Start Job ring 2 */
575#define JRSTART_JR3_START 0x00000008 /* Start Job ring 3 */
576
577/*
578 * caam_job_ring - direct job ring setup
579 * 1-4 possible per instantiation, base + 1000/2000/3000/4000
580 * Padded out to 0x1000
581 */
582struct caam_job_ring {
583 /* Input ring */
584 u64 inpring_base; /* IRBAx - Input desc ring baseaddr */
585 u32 rsvd1;
586 u32 inpring_size; /* IRSx - Input ring size */
587 u32 rsvd2;
588 u32 inpring_avail; /* IRSAx - Input ring room remaining */
589 u32 rsvd3;
590 u32 inpring_jobadd; /* IRJAx - Input ring jobs added */
591
592 /* Output Ring */
593 u64 outring_base; /* ORBAx - Output status ring base addr */
594 u32 rsvd4;
595 u32 outring_size; /* ORSx - Output ring size */
596 u32 rsvd5;
597 u32 outring_rmvd; /* ORJRx - Output ring jobs removed */
598 u32 rsvd6;
599 u32 outring_used; /* ORSFx - Output ring slots full */
600
601 /* Status/Configuration */
602 u32 rsvd7;
603 u32 jroutstatus; /* JRSTAx - JobR output status */
604 u32 rsvd8;
605 u32 jrintstatus; /* JRINTx - JobR interrupt status */
606 u32 rconfig_hi; /* JRxCFG - Ring configuration */
607 u32 rconfig_lo;
608
609 /* Indices. CAAM maintains as "heads" of each queue */
610 u32 rsvd9;
611 u32 inp_rdidx; /* IRRIx - Input ring read index */
612 u32 rsvd10;
613 u32 out_wtidx; /* ORWIx - Output ring write index */
614
615 /* Command/control */
616 u32 rsvd11;
617 u32 jrcommand; /* JRCRx - JobR command */
618
619 u32 rsvd12[900];
620
621 /* Version registers - introduced with era 10 e80-eff */
622 struct version_regs vreg;
623 /* Performance Monitor f00-fff */
624 struct caam_perfmon perfmon;
625};
626
627#define JR_RINGSIZE_MASK 0x03ff
628/*
629 * jrstatus - Job Ring Output Status
630 * All values in lo word
631 * Also note, same values written out as status through QI
632 * in the command/status field of a frame descriptor
633 */
634#define JRSTA_SSRC_SHIFT 28
635#define JRSTA_SSRC_MASK 0xf0000000
636
637#define JRSTA_SSRC_NONE 0x00000000
638#define JRSTA_SSRC_CCB_ERROR 0x20000000
639#define JRSTA_SSRC_JUMP_HALT_USER 0x30000000
640#define JRSTA_SSRC_DECO 0x40000000
641#define JRSTA_SSRC_JRERROR 0x60000000
642#define JRSTA_SSRC_JUMP_HALT_CC 0x70000000
643
644#define JRSTA_DECOERR_JUMP 0x08000000
645#define JRSTA_DECOERR_INDEX_SHIFT 8
646#define JRSTA_DECOERR_INDEX_MASK 0xff00
647#define JRSTA_DECOERR_ERROR_MASK 0x00ff
648
649#define JRSTA_DECOERR_NONE 0x00
650#define JRSTA_DECOERR_LINKLEN 0x01
651#define JRSTA_DECOERR_LINKPTR 0x02
652#define JRSTA_DECOERR_JRCTRL 0x03
653#define JRSTA_DECOERR_DESCCMD 0x04
654#define JRSTA_DECOERR_ORDER 0x05
655#define JRSTA_DECOERR_KEYCMD 0x06
656#define JRSTA_DECOERR_LOADCMD 0x07
657#define JRSTA_DECOERR_STORECMD 0x08
658#define JRSTA_DECOERR_OPCMD 0x09
659#define JRSTA_DECOERR_FIFOLDCMD 0x0a
660#define JRSTA_DECOERR_FIFOSTCMD 0x0b
661#define JRSTA_DECOERR_MOVECMD 0x0c
662#define JRSTA_DECOERR_JUMPCMD 0x0d
663#define JRSTA_DECOERR_MATHCMD 0x0e
664#define JRSTA_DECOERR_SHASHCMD 0x0f
665#define JRSTA_DECOERR_SEQCMD 0x10
666#define JRSTA_DECOERR_DECOINTERNAL 0x11
667#define JRSTA_DECOERR_SHDESCHDR 0x12
668#define JRSTA_DECOERR_HDRLEN 0x13
669#define JRSTA_DECOERR_BURSTER 0x14
670#define JRSTA_DECOERR_DESCSIGNATURE 0x15
671#define JRSTA_DECOERR_DMA 0x16
672#define JRSTA_DECOERR_BURSTFIFO 0x17
673#define JRSTA_DECOERR_JRRESET 0x1a
674#define JRSTA_DECOERR_JOBFAIL 0x1b
675#define JRSTA_DECOERR_DNRERR 0x80
676#define JRSTA_DECOERR_UNDEFPCL 0x81
677#define JRSTA_DECOERR_PDBERR 0x82
678#define JRSTA_DECOERR_ANRPLY_LATE 0x83
679#define JRSTA_DECOERR_ANRPLY_REPLAY 0x84
680#define JRSTA_DECOERR_SEQOVF 0x85
681#define JRSTA_DECOERR_INVSIGN 0x86
682#define JRSTA_DECOERR_DSASIGN 0x87
683
684#define JRSTA_QIERR_ERROR_MASK 0x00ff
685
686#define JRSTA_CCBERR_JUMP 0x08000000
687#define JRSTA_CCBERR_INDEX_MASK 0xff00
688#define JRSTA_CCBERR_INDEX_SHIFT 8
689#define JRSTA_CCBERR_CHAID_MASK 0x00f0
690#define JRSTA_CCBERR_CHAID_SHIFT 4
691#define JRSTA_CCBERR_ERRID_MASK 0x000f
692
693#define JRSTA_CCBERR_CHAID_AES (0x01 << JRSTA_CCBERR_CHAID_SHIFT)
694#define JRSTA_CCBERR_CHAID_DES (0x02 << JRSTA_CCBERR_CHAID_SHIFT)
695#define JRSTA_CCBERR_CHAID_ARC4 (0x03 << JRSTA_CCBERR_CHAID_SHIFT)
696#define JRSTA_CCBERR_CHAID_MD (0x04 << JRSTA_CCBERR_CHAID_SHIFT)
697#define JRSTA_CCBERR_CHAID_RNG (0x05 << JRSTA_CCBERR_CHAID_SHIFT)
698#define JRSTA_CCBERR_CHAID_SNOW (0x06 << JRSTA_CCBERR_CHAID_SHIFT)
699#define JRSTA_CCBERR_CHAID_KASUMI (0x07 << JRSTA_CCBERR_CHAID_SHIFT)
700#define JRSTA_CCBERR_CHAID_PK (0x08 << JRSTA_CCBERR_CHAID_SHIFT)
701#define JRSTA_CCBERR_CHAID_CRC (0x09 << JRSTA_CCBERR_CHAID_SHIFT)
702
703#define JRSTA_CCBERR_ERRID_NONE 0x00
704#define JRSTA_CCBERR_ERRID_MODE 0x01
705#define JRSTA_CCBERR_ERRID_DATASIZ 0x02
706#define JRSTA_CCBERR_ERRID_KEYSIZ 0x03
707#define JRSTA_CCBERR_ERRID_PKAMEMSZ 0x04
708#define JRSTA_CCBERR_ERRID_PKBMEMSZ 0x05
709#define JRSTA_CCBERR_ERRID_SEQUENCE 0x06
710#define JRSTA_CCBERR_ERRID_PKDIVZRO 0x07
711#define JRSTA_CCBERR_ERRID_PKMODEVN 0x08
712#define JRSTA_CCBERR_ERRID_KEYPARIT 0x09
713#define JRSTA_CCBERR_ERRID_ICVCHK 0x0a
714#define JRSTA_CCBERR_ERRID_HARDWARE 0x0b
715#define JRSTA_CCBERR_ERRID_CCMAAD 0x0c
716#define JRSTA_CCBERR_ERRID_INVCHA 0x0f
717
718#define JRINT_ERR_INDEX_MASK 0x3fff0000
719#define JRINT_ERR_INDEX_SHIFT 16
720#define JRINT_ERR_TYPE_MASK 0xf00
721#define JRINT_ERR_TYPE_SHIFT 8
722#define JRINT_ERR_HALT_MASK 0xc
723#define JRINT_ERR_HALT_SHIFT 2
724#define JRINT_ERR_HALT_INPROGRESS 0x4
725#define JRINT_ERR_HALT_COMPLETE 0x8
726#define JRINT_JR_ERROR 0x02
727#define JRINT_JR_INT 0x01
728
729#define JRINT_ERR_TYPE_WRITE 1
730#define JRINT_ERR_TYPE_BAD_INPADDR 3
731#define JRINT_ERR_TYPE_BAD_OUTADDR 4
732#define JRINT_ERR_TYPE_INV_INPWRT 5
733#define JRINT_ERR_TYPE_INV_OUTWRT 6
734#define JRINT_ERR_TYPE_RESET 7
735#define JRINT_ERR_TYPE_REMOVE_OFL 8
736#define JRINT_ERR_TYPE_ADD_OFL 9
737
738#define JRCFG_SOE 0x04
739#define JRCFG_ICEN 0x02
740#define JRCFG_IMSK 0x01
741#define JRCFG_ICDCT_SHIFT 8
742#define JRCFG_ICTT_SHIFT 16
743
744#define JRCR_RESET 0x01
745
746/*
747 * caam_assurance - Assurance Controller View
748 * base + 0x6000 padded out to 0x1000
749 */
750
751struct rtic_element {
752 u64 address;
753 u32 rsvd;
754 u32 length;
755};
756
757struct rtic_block {
758 struct rtic_element element[2];
759};
760
761struct rtic_memhash {
762 u32 memhash_be[32];
763 u32 memhash_le[32];
764};
765
766struct caam_assurance {
767 /* Status/Command/Watchdog */
768 u32 rsvd1;
769 u32 status; /* RSTA - Status */
770 u32 rsvd2;
771 u32 cmd; /* RCMD - Command */
772 u32 rsvd3;
773 u32 ctrl; /* RCTL - Control */
774 u32 rsvd4;
775 u32 throttle; /* RTHR - Throttle */
776 u32 rsvd5[2];
777 u64 watchdog; /* RWDOG - Watchdog Timer */
778 u32 rsvd6;
779 u32 rend; /* REND - Endian corrections */
780 u32 rsvd7[50];
781
782 /* Block access/configuration @ 100/110/120/130 */
783 struct rtic_block memblk[4]; /* Memory Blocks A-D */
784 u32 rsvd8[32];
785
786 /* Block hashes @ 200/300/400/500 */
787 struct rtic_memhash hash[4]; /* Block hash values A-D */
788 u32 rsvd_3[640];
789};
790
791/*
792 * caam_queue_if - QI configuration and control
793 * starts base + 0x7000, padded out to 0x1000 long
794 */
795
796struct caam_queue_if {
797 u32 qi_control_hi; /* QICTL - QI Control */
798 u32 qi_control_lo;
799 u32 rsvd1;
800 u32 qi_status; /* QISTA - QI Status */
801 u32 qi_deq_cfg_hi; /* QIDQC - QI Dequeue Configuration */
802 u32 qi_deq_cfg_lo;
803 u32 qi_enq_cfg_hi; /* QISEQC - QI Enqueue Command */
804 u32 qi_enq_cfg_lo;
805 u32 rsvd2[1016];
806};
807
808/* QI control bits - low word */
809#define QICTL_DQEN 0x01 /* Enable frame pop */
810#define QICTL_STOP 0x02 /* Stop dequeue/enqueue */
811#define QICTL_SOE 0x04 /* Stop on error */
812
813/* QI control bits - high word */
814#define QICTL_MBSI 0x01
815#define QICTL_MHWSI 0x02
816#define QICTL_MWSI 0x04
817#define QICTL_MDWSI 0x08
818#define QICTL_CBSI 0x10 /* CtrlDataByteSwapInput */
819#define QICTL_CHWSI 0x20 /* CtrlDataHalfSwapInput */
820#define QICTL_CWSI 0x40 /* CtrlDataWordSwapInput */
821#define QICTL_CDWSI 0x80 /* CtrlDataDWordSwapInput */
822#define QICTL_MBSO 0x0100
823#define QICTL_MHWSO 0x0200
824#define QICTL_MWSO 0x0400
825#define QICTL_MDWSO 0x0800
826#define QICTL_CBSO 0x1000 /* CtrlDataByteSwapOutput */
827#define QICTL_CHWSO 0x2000 /* CtrlDataHalfSwapOutput */
828#define QICTL_CWSO 0x4000 /* CtrlDataWordSwapOutput */
829#define QICTL_CDWSO 0x8000 /* CtrlDataDWordSwapOutput */
830#define QICTL_DMBS 0x010000
831#define QICTL_EPO 0x020000
832
833/* QI status bits */
834#define QISTA_PHRDERR 0x01 /* PreHeader Read Error */
835#define QISTA_CFRDERR 0x02 /* Compound Frame Read Error */
836#define QISTA_OFWRERR 0x04 /* Output Frame Read Error */
837#define QISTA_BPDERR 0x08 /* Buffer Pool Depleted */
838#define QISTA_BTSERR 0x10 /* Buffer Undersize */
839#define QISTA_CFWRERR 0x20 /* Compound Frame Write Err */
840#define QISTA_STOPD 0x80000000 /* QI Stopped (see QICTL) */
841
842/* deco_sg_table - DECO view of scatter/gather table */
843struct deco_sg_table {
844 u64 addr; /* Segment Address */
845 u32 elen; /* E, F bits + 30-bit length */
846 u32 bpid_offset; /* Buffer Pool ID + 16-bit length */
847};
848
849/*
850 * caam_deco - descriptor controller - CHA cluster block
851 *
852 * Only accessible when direct DECO access is turned on
853 * (done in DECORR, via MID programmed in DECOxMID
854 *
855 * 5 typical, base + 0x8000/9000/a000/b000
856 * Padded out to 0x1000 long
857 */
858struct caam_deco {
859 u32 rsvd1;
860 u32 cls1_mode; /* CxC1MR - Class 1 Mode */
861 u32 rsvd2;
862 u32 cls1_keysize; /* CxC1KSR - Class 1 Key Size */
863 u32 cls1_datasize_hi; /* CxC1DSR - Class 1 Data Size */
864 u32 cls1_datasize_lo;
865 u32 rsvd3;
866 u32 cls1_icvsize; /* CxC1ICVSR - Class 1 ICV size */
867 u32 rsvd4[5];
868 u32 cha_ctrl; /* CCTLR - CHA control */
869 u32 rsvd5;
870 u32 irq_crtl; /* CxCIRQ - CCB interrupt done/error/clear */
871 u32 rsvd6;
872 u32 clr_written; /* CxCWR - Clear-Written */
873 u32 ccb_status_hi; /* CxCSTA - CCB Status/Error */
874 u32 ccb_status_lo;
875 u32 rsvd7[3];
876 u32 aad_size; /* CxAADSZR - Current AAD Size */
877 u32 rsvd8;
878 u32 cls1_iv_size; /* CxC1IVSZR - Current Class 1 IV Size */
879 u32 rsvd9[7];
880 u32 pkha_a_size; /* PKASZRx - Size of PKHA A */
881 u32 rsvd10;
882 u32 pkha_b_size; /* PKBSZRx - Size of PKHA B */
883 u32 rsvd11;
884 u32 pkha_n_size; /* PKNSZRx - Size of PKHA N */
885 u32 rsvd12;
886 u32 pkha_e_size; /* PKESZRx - Size of PKHA E */
887 u32 rsvd13[24];
888 u32 cls1_ctx[16]; /* CxC1CTXR - Class 1 Context @100 */
889 u32 rsvd14[48];
890 u32 cls1_key[8]; /* CxC1KEYR - Class 1 Key @200 */
891 u32 rsvd15[121];
892 u32 cls2_mode; /* CxC2MR - Class 2 Mode */
893 u32 rsvd16;
894 u32 cls2_keysize; /* CxX2KSR - Class 2 Key Size */
895 u32 cls2_datasize_hi; /* CxC2DSR - Class 2 Data Size */
896 u32 cls2_datasize_lo;
897 u32 rsvd17;
898 u32 cls2_icvsize; /* CxC2ICVSZR - Class 2 ICV Size */
899 u32 rsvd18[56];
900 u32 cls2_ctx[18]; /* CxC2CTXR - Class 2 Context @500 */
901 u32 rsvd19[46];
902 u32 cls2_key[32]; /* CxC2KEYR - Class2 Key @600 */
903 u32 rsvd20[84];
904 u32 inp_infofifo_hi; /* CxIFIFO - Input Info FIFO @7d0 */
905 u32 inp_infofifo_lo;
906 u32 rsvd21[2];
907 u64 inp_datafifo; /* CxDFIFO - Input Data FIFO */
908 u32 rsvd22[2];
909 u64 out_datafifo; /* CxOFIFO - Output Data FIFO */
910 u32 rsvd23[2];
911 u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */
912 u32 jr_ctl_lo;
913 u64 jr_descaddr; /* CxDADR - JobR Descriptor Address */
914#define DECO_OP_STATUS_HI_ERR_MASK 0xF00000FF
915 u32 op_status_hi; /* DxOPSTA - DECO Operation Status */
916 u32 op_status_lo;
917 u32 rsvd24[2];
918 u32 liodn; /* DxLSR - DECO LIODN Status - non-seq */
919 u32 td_liodn; /* DxLSR - DECO LIODN Status - trustdesc */
920 u32 rsvd26[6];
921 u64 math[4]; /* DxMTH - Math register */
922 u32 rsvd27[8];
923 struct deco_sg_table gthr_tbl[4]; /* DxGTR - Gather Tables */
924 u32 rsvd28[16];
925 struct deco_sg_table sctr_tbl[4]; /* DxSTR - Scatter Tables */
926 u32 rsvd29[48];
927 u32 descbuf[64]; /* DxDESB - Descriptor buffer */
928 u32 rscvd30[193];
929#define DESC_DBG_DECO_STAT_VALID 0x80000000
930#define DESC_DBG_DECO_STAT_MASK 0x00F00000
931#define DESC_DBG_DECO_STAT_SHIFT 20
932 u32 desc_dbg; /* DxDDR - DECO Debug Register */
933 u32 rsvd31[13];
934#define DESC_DER_DECO_STAT_MASK 0x000F0000
935#define DESC_DER_DECO_STAT_SHIFT 16
936 u32 dbg_exec; /* DxDER - DECO Debug Exec Register */
937 u32 rsvd32[112];
938};
939
940#define DECO_STAT_HOST_ERR 0xD
941
942#define DECO_JQCR_WHL 0x20000000
943#define DECO_JQCR_FOUR 0x10000000
944
945#define JR_BLOCK_NUMBER 1
946#define ASSURE_BLOCK_NUMBER 6
947#define QI_BLOCK_NUMBER 7
948#define DECO_BLOCK_NUMBER 8
949#define PG_SIZE_4K 0x1000
950#define PG_SIZE_64K 0x10000
951#endif /* REGS_H */