tjh.dev
Linux kernel mirror (for testing)
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1/*
2 * Copyright (C) 2012,2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __ARM64_KVM_ARM_H__
19#define __ARM64_KVM_ARM_H__
20
21#include <asm/esr.h>
22#include <asm/memory.h>
23#include <asm/types.h>
24
25/* Hyp Configuration Register (HCR) bits */
26#define HCR_FWB (UL(1) << 46)
27#define HCR_API (UL(1) << 41)
28#define HCR_APK (UL(1) << 40)
29#define HCR_TEA (UL(1) << 37)
30#define HCR_TERR (UL(1) << 36)
31#define HCR_TLOR (UL(1) << 35)
32#define HCR_E2H (UL(1) << 34)
33#define HCR_ID (UL(1) << 33)
34#define HCR_CD (UL(1) << 32)
35#define HCR_RW_SHIFT 31
36#define HCR_RW (UL(1) << HCR_RW_SHIFT)
37#define HCR_TRVM (UL(1) << 30)
38#define HCR_HCD (UL(1) << 29)
39#define HCR_TDZ (UL(1) << 28)
40#define HCR_TGE (UL(1) << 27)
41#define HCR_TVM (UL(1) << 26)
42#define HCR_TTLB (UL(1) << 25)
43#define HCR_TPU (UL(1) << 24)
44#define HCR_TPC (UL(1) << 23)
45#define HCR_TSW (UL(1) << 22)
46#define HCR_TAC (UL(1) << 21)
47#define HCR_TIDCP (UL(1) << 20)
48#define HCR_TSC (UL(1) << 19)
49#define HCR_TID3 (UL(1) << 18)
50#define HCR_TID2 (UL(1) << 17)
51#define HCR_TID1 (UL(1) << 16)
52#define HCR_TID0 (UL(1) << 15)
53#define HCR_TWE (UL(1) << 14)
54#define HCR_TWI (UL(1) << 13)
55#define HCR_DC (UL(1) << 12)
56#define HCR_BSU (3 << 10)
57#define HCR_BSU_IS (UL(1) << 10)
58#define HCR_FB (UL(1) << 9)
59#define HCR_VSE (UL(1) << 8)
60#define HCR_VI (UL(1) << 7)
61#define HCR_VF (UL(1) << 6)
62#define HCR_AMO (UL(1) << 5)
63#define HCR_IMO (UL(1) << 4)
64#define HCR_FMO (UL(1) << 3)
65#define HCR_PTW (UL(1) << 2)
66#define HCR_SWIO (UL(1) << 1)
67#define HCR_VM (UL(1) << 0)
68
69/*
70 * The bits we set in HCR:
71 * TLOR: Trap LORegion register accesses
72 * RW: 64bit by default, can be overridden for 32bit VMs
73 * TAC: Trap ACTLR
74 * TSC: Trap SMC
75 * TVM: Trap VM ops (until M+C set in SCTLR_EL1)
76 * TSW: Trap cache operations by set/way
77 * TWE: Trap WFE
78 * TWI: Trap WFI
79 * TIDCP: Trap L2CTLR/L2ECTLR
80 * BSU_IS: Upgrade barriers to the inner shareable domain
81 * FB: Force broadcast of all maintainance operations
82 * AMO: Override CPSR.A and enable signaling with VA
83 * IMO: Override CPSR.I and enable signaling with VI
84 * FMO: Override CPSR.F and enable signaling with VF
85 * SWIO: Turn set/way invalidates into set/way clean+invalidate
86 */
87#define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \
88 HCR_TVM | HCR_BSU_IS | HCR_FB | HCR_TAC | \
89 HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \
90 HCR_FMO | HCR_IMO)
91#define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF)
92#define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK)
93#define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)
94
95/* TCR_EL2 Registers bits */
96#define TCR_EL2_RES1 ((1 << 31) | (1 << 23))
97#define TCR_EL2_TBI (1 << 20)
98#define TCR_EL2_PS_SHIFT 16
99#define TCR_EL2_PS_MASK (7 << TCR_EL2_PS_SHIFT)
100#define TCR_EL2_PS_40B (2 << TCR_EL2_PS_SHIFT)
101#define TCR_EL2_TG0_MASK TCR_TG0_MASK
102#define TCR_EL2_SH0_MASK TCR_SH0_MASK
103#define TCR_EL2_ORGN0_MASK TCR_ORGN0_MASK
104#define TCR_EL2_IRGN0_MASK TCR_IRGN0_MASK
105#define TCR_EL2_T0SZ_MASK 0x3f
106#define TCR_EL2_MASK (TCR_EL2_TG0_MASK | TCR_EL2_SH0_MASK | \
107 TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK | TCR_EL2_T0SZ_MASK)
108
109/* VTCR_EL2 Registers bits */
110#define VTCR_EL2_RES1 (1U << 31)
111#define VTCR_EL2_HD (1 << 22)
112#define VTCR_EL2_HA (1 << 21)
113#define VTCR_EL2_PS_SHIFT TCR_EL2_PS_SHIFT
114#define VTCR_EL2_PS_MASK TCR_EL2_PS_MASK
115#define VTCR_EL2_TG0_MASK TCR_TG0_MASK
116#define VTCR_EL2_TG0_4K TCR_TG0_4K
117#define VTCR_EL2_TG0_16K TCR_TG0_16K
118#define VTCR_EL2_TG0_64K TCR_TG0_64K
119#define VTCR_EL2_SH0_MASK TCR_SH0_MASK
120#define VTCR_EL2_SH0_INNER TCR_SH0_INNER
121#define VTCR_EL2_ORGN0_MASK TCR_ORGN0_MASK
122#define VTCR_EL2_ORGN0_WBWA TCR_ORGN0_WBWA
123#define VTCR_EL2_IRGN0_MASK TCR_IRGN0_MASK
124#define VTCR_EL2_IRGN0_WBWA TCR_IRGN0_WBWA
125#define VTCR_EL2_SL0_SHIFT 6
126#define VTCR_EL2_SL0_MASK (3 << VTCR_EL2_SL0_SHIFT)
127#define VTCR_EL2_T0SZ_MASK 0x3f
128#define VTCR_EL2_VS_SHIFT 19
129#define VTCR_EL2_VS_8BIT (0 << VTCR_EL2_VS_SHIFT)
130#define VTCR_EL2_VS_16BIT (1 << VTCR_EL2_VS_SHIFT)
131
132#define VTCR_EL2_T0SZ(x) TCR_T0SZ(x)
133
134/*
135 * We configure the Stage-2 page tables to always restrict the IPA space to be
136 * 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are
137 * not known to exist and will break with this configuration.
138 *
139 * The VTCR_EL2 is configured per VM and is initialised in kvm_arm_setup_stage2().
140 *
141 * Note that when using 4K pages, we concatenate two first level page tables
142 * together. With 16K pages, we concatenate 16 first level page tables.
143 *
144 */
145
146#define VTCR_EL2_COMMON_BITS (VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \
147 VTCR_EL2_IRGN0_WBWA | VTCR_EL2_RES1)
148
149/*
150 * VTCR_EL2:SL0 indicates the entry level for Stage2 translation.
151 * Interestingly, it depends on the page size.
152 * See D.10.2.121, VTCR_EL2, in ARM DDI 0487C.a
153 *
154 * -----------------------------------------
155 * | Entry level | 4K | 16K/64K |
156 * ------------------------------------------
157 * | Level: 0 | 2 | - |
158 * ------------------------------------------
159 * | Level: 1 | 1 | 2 |
160 * ------------------------------------------
161 * | Level: 2 | 0 | 1 |
162 * ------------------------------------------
163 * | Level: 3 | - | 0 |
164 * ------------------------------------------
165 *
166 * The table roughly translates to :
167 *
168 * SL0(PAGE_SIZE, Entry_level) = TGRAN_SL0_BASE - Entry_Level
169 *
170 * Where TGRAN_SL0_BASE is a magic number depending on the page size:
171 * TGRAN_SL0_BASE(4K) = 2
172 * TGRAN_SL0_BASE(16K) = 3
173 * TGRAN_SL0_BASE(64K) = 3
174 * provided we take care of ruling out the unsupported cases and
175 * Entry_Level = 4 - Number_of_levels.
176 *
177 */
178#ifdef CONFIG_ARM64_64K_PAGES
179
180#define VTCR_EL2_TGRAN VTCR_EL2_TG0_64K
181#define VTCR_EL2_TGRAN_SL0_BASE 3UL
182
183#elif defined(CONFIG_ARM64_16K_PAGES)
184
185#define VTCR_EL2_TGRAN VTCR_EL2_TG0_16K
186#define VTCR_EL2_TGRAN_SL0_BASE 3UL
187
188#else /* 4K */
189
190#define VTCR_EL2_TGRAN VTCR_EL2_TG0_4K
191#define VTCR_EL2_TGRAN_SL0_BASE 2UL
192
193#endif
194
195#define VTCR_EL2_LVLS_TO_SL0(levels) \
196 ((VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels))) << VTCR_EL2_SL0_SHIFT)
197#define VTCR_EL2_SL0_TO_LVLS(sl0) \
198 ((sl0) + 4 - VTCR_EL2_TGRAN_SL0_BASE)
199#define VTCR_EL2_LVLS(vtcr) \
200 VTCR_EL2_SL0_TO_LVLS(((vtcr) & VTCR_EL2_SL0_MASK) >> VTCR_EL2_SL0_SHIFT)
201
202#define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN)
203#define VTCR_EL2_IPA(vtcr) (64 - ((vtcr) & VTCR_EL2_T0SZ_MASK))
204
205/*
206 * ARM VMSAv8-64 defines an algorithm for finding the translation table
207 * descriptors in section D4.2.8 in ARM DDI 0487C.a.
208 *
209 * The algorithm defines the expectations on the translation table
210 * addresses for each level, based on PAGE_SIZE, entry level
211 * and the translation table size (T0SZ). The variable "x" in the
212 * algorithm determines the alignment of a table base address at a given
213 * level and thus determines the alignment of VTTBR:BADDR for stage2
214 * page table entry level.
215 * Since the number of bits resolved at the entry level could vary
216 * depending on the T0SZ, the value of "x" is defined based on a
217 * Magic constant for a given PAGE_SIZE and Entry Level. The
218 * intermediate levels must be always aligned to the PAGE_SIZE (i.e,
219 * x = PAGE_SHIFT).
220 *
221 * The value of "x" for entry level is calculated as :
222 * x = Magic_N - T0SZ
223 *
224 * where Magic_N is an integer depending on the page size and the entry
225 * level of the page table as below:
226 *
227 * --------------------------------------------
228 * | Entry level | 4K 16K 64K |
229 * --------------------------------------------
230 * | Level: 0 (4 levels) | 28 | - | - |
231 * --------------------------------------------
232 * | Level: 1 (3 levels) | 37 | 31 | 25 |
233 * --------------------------------------------
234 * | Level: 2 (2 levels) | 46 | 42 | 38 |
235 * --------------------------------------------
236 * | Level: 3 (1 level) | - | 53 | 51 |
237 * --------------------------------------------
238 *
239 * We have a magic formula for the Magic_N below:
240 *
241 * Magic_N(PAGE_SIZE, Level) = 64 - ((PAGE_SHIFT - 3) * Number_of_levels)
242 *
243 * where Number_of_levels = (4 - Level). We are only interested in the
244 * value for Entry_Level for the stage2 page table.
245 *
246 * So, given that T0SZ = (64 - IPA_SHIFT), we can compute 'x' as follows:
247 *
248 * x = (64 - ((PAGE_SHIFT - 3) * Number_of_levels)) - (64 - IPA_SHIFT)
249 * = IPA_SHIFT - ((PAGE_SHIFT - 3) * Number of levels)
250 *
251 * Here is one way to explain the Magic Formula:
252 *
253 * x = log2(Size_of_Entry_Level_Table)
254 *
255 * Since, we can resolve (PAGE_SHIFT - 3) bits at each level, and another
256 * PAGE_SHIFT bits in the PTE, we have :
257 *
258 * Bits_Entry_level = IPA_SHIFT - ((PAGE_SHIFT - 3) * (n - 1) + PAGE_SHIFT)
259 * = IPA_SHIFT - (PAGE_SHIFT - 3) * n - 3
260 * where n = number of levels, and since each pointer is 8bytes, we have:
261 *
262 * x = Bits_Entry_Level + 3
263 * = IPA_SHIFT - (PAGE_SHIFT - 3) * n
264 *
265 * The only constraint here is that, we have to find the number of page table
266 * levels for a given IPA size (which we do, see stage2_pt_levels())
267 */
268#define ARM64_VTTBR_X(ipa, levels) ((ipa) - ((levels) * (PAGE_SHIFT - 3)))
269
270#define VTTBR_CNP_BIT (UL(1))
271#define VTTBR_VMID_SHIFT (UL(48))
272#define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT)
273
274/* Hyp System Trap Register */
275#define HSTR_EL2_T(x) (1 << x)
276
277/* Hyp Coprocessor Trap Register Shifts */
278#define CPTR_EL2_TFP_SHIFT 10
279
280/* Hyp Coprocessor Trap Register */
281#define CPTR_EL2_TCPAC (1 << 31)
282#define CPTR_EL2_TTA (1 << 20)
283#define CPTR_EL2_TFP (1 << CPTR_EL2_TFP_SHIFT)
284#define CPTR_EL2_TZ (1 << 8)
285#define CPTR_EL2_RES1 0x000032ff /* known RES1 bits in CPTR_EL2 */
286#define CPTR_EL2_DEFAULT CPTR_EL2_RES1
287
288/* Hyp Debug Configuration Register bits */
289#define MDCR_EL2_TPMS (1 << 14)
290#define MDCR_EL2_E2PB_MASK (UL(0x3))
291#define MDCR_EL2_E2PB_SHIFT (UL(12))
292#define MDCR_EL2_TDRA (1 << 11)
293#define MDCR_EL2_TDOSA (1 << 10)
294#define MDCR_EL2_TDA (1 << 9)
295#define MDCR_EL2_TDE (1 << 8)
296#define MDCR_EL2_HPME (1 << 7)
297#define MDCR_EL2_TPM (1 << 6)
298#define MDCR_EL2_TPMCR (1 << 5)
299#define MDCR_EL2_HPMN_MASK (0x1F)
300
301/* For compatibility with fault code shared with 32-bit */
302#define FSC_FAULT ESR_ELx_FSC_FAULT
303#define FSC_ACCESS ESR_ELx_FSC_ACCESS
304#define FSC_PERM ESR_ELx_FSC_PERM
305#define FSC_SEA ESR_ELx_FSC_EXTABT
306#define FSC_SEA_TTW0 (0x14)
307#define FSC_SEA_TTW1 (0x15)
308#define FSC_SEA_TTW2 (0x16)
309#define FSC_SEA_TTW3 (0x17)
310#define FSC_SECC (0x18)
311#define FSC_SECC_TTW0 (0x1c)
312#define FSC_SECC_TTW1 (0x1d)
313#define FSC_SECC_TTW2 (0x1e)
314#define FSC_SECC_TTW3 (0x1f)
315
316/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
317#define HPFAR_MASK (~UL(0xf))
318/*
319 * We have
320 * PAR [PA_Shift - 1 : 12] = PA [PA_Shift - 1 : 12]
321 * HPFAR [PA_Shift - 9 : 4] = FIPA [PA_Shift - 1 : 12]
322 */
323#define PAR_TO_HPFAR(par) \
324 (((par) & GENMASK_ULL(PHYS_MASK_SHIFT - 1, 12)) >> 8)
325
326#define ECN(x) { ESR_ELx_EC_##x, #x }
327
328#define kvm_arm_exception_class \
329 ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \
330 ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(CP14_64), ECN(SVC64), \
331 ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(IMP_DEF), ECN(IABT_LOW), \
332 ECN(IABT_CUR), ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \
333 ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \
334 ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \
335 ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \
336 ECN(BKPT32), ECN(VECTOR32), ECN(BRK64)
337
338#define CPACR_EL1_FPEN (3 << 20)
339#define CPACR_EL1_TTA (1 << 28)
340#define CPACR_EL1_DEFAULT (CPACR_EL1_FPEN | CPACR_EL1_ZEN_EL1EN)
341
342#endif /* __ARM64_KVM_ARM_H__ */