Linux kernel mirror (for testing)
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1/*
2 * Copyright (C) 2012 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef __ASM_CACHE_H
17#define __ASM_CACHE_H
18
19#include <asm/cputype.h>
20
21#define CTR_L1IP_SHIFT 14
22#define CTR_L1IP_MASK 3
23#define CTR_DMINLINE_SHIFT 16
24#define CTR_IMINLINE_SHIFT 0
25#define CTR_ERG_SHIFT 20
26#define CTR_CWG_SHIFT 24
27#define CTR_CWG_MASK 15
28#define CTR_IDC_SHIFT 28
29#define CTR_DIC_SHIFT 29
30
31#define CTR_CACHE_MINLINE_MASK \
32 (0xf << CTR_DMINLINE_SHIFT | 0xf << CTR_IMINLINE_SHIFT)
33
34#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
35
36#define ICACHE_POLICY_VPIPT 0
37#define ICACHE_POLICY_VIPT 2
38#define ICACHE_POLICY_PIPT 3
39
40#define L1_CACHE_SHIFT (6)
41#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
42
43
44#define CLIDR_LOUU_SHIFT 27
45#define CLIDR_LOC_SHIFT 24
46#define CLIDR_LOUIS_SHIFT 21
47
48#define CLIDR_LOUU(clidr) (((clidr) >> CLIDR_LOUU_SHIFT) & 0x7)
49#define CLIDR_LOC(clidr) (((clidr) >> CLIDR_LOC_SHIFT) & 0x7)
50#define CLIDR_LOUIS(clidr) (((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7)
51
52/*
53 * Memory returned by kmalloc() may be used for DMA, so we must make
54 * sure that all such allocations are cache aligned. Otherwise,
55 * unrelated code may cause parts of the buffer to be read into the
56 * cache before the transfer is done, causing old data to be seen by
57 * the CPU.
58 */
59#define ARCH_DMA_MINALIGN (128)
60
61#ifdef CONFIG_KASAN_SW_TAGS
62#define ARCH_SLAB_MINALIGN (1ULL << KASAN_SHADOW_SCALE_SHIFT)
63#endif
64
65#ifndef __ASSEMBLY__
66
67#include <linux/bitops.h>
68
69#define ICACHEF_ALIASING 0
70#define ICACHEF_VPIPT 1
71extern unsigned long __icache_flags;
72
73/*
74 * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
75 * permitted in the I-cache.
76 */
77static inline int icache_is_aliasing(void)
78{
79 return test_bit(ICACHEF_ALIASING, &__icache_flags);
80}
81
82static inline int icache_is_vpipt(void)
83{
84 return test_bit(ICACHEF_VPIPT, &__icache_flags);
85}
86
87static inline u32 cache_type_cwg(void)
88{
89 return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
90}
91
92#define __read_mostly __attribute__((__section__(".data..read_mostly")))
93
94static inline int cache_line_size(void)
95{
96 u32 cwg = cache_type_cwg();
97 return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
98}
99
100/*
101 * Read the effective value of CTR_EL0.
102 *
103 * According to ARM ARM for ARMv8-A (ARM DDI 0487C.a),
104 * section D10.2.33 "CTR_EL0, Cache Type Register" :
105 *
106 * CTR_EL0.IDC reports the data cache clean requirements for
107 * instruction to data coherence.
108 *
109 * 0 - dcache clean to PoU is required unless :
110 * (CLIDR_EL1.LoC == 0) || (CLIDR_EL1.LoUIS == 0 && CLIDR_EL1.LoUU == 0)
111 * 1 - dcache clean to PoU is not required for i-to-d coherence.
112 *
113 * This routine provides the CTR_EL0 with the IDC field updated to the
114 * effective state.
115 */
116static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void)
117{
118 u32 ctr = read_cpuid_cachetype();
119
120 if (!(ctr & BIT(CTR_IDC_SHIFT))) {
121 u64 clidr = read_sysreg(clidr_el1);
122
123 if (CLIDR_LOC(clidr) == 0 ||
124 (CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0))
125 ctr |= BIT(CTR_IDC_SHIFT);
126 }
127
128 return ctr;
129}
130
131#endif /* __ASSEMBLY__ */
132
133#endif