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1* Renesas R-Car PCIe interface 2 3Required properties: 4compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC; 5 "renesas,pcie-r8a7744" for the R8A7744 SoC; 6 "renesas,pcie-r8a7779" for the R8A7779 SoC; 7 "renesas,pcie-r8a7790" for the R8A7790 SoC; 8 "renesas,pcie-r8a7791" for the R8A7791 SoC; 9 "renesas,pcie-r8a7793" for the R8A7793 SoC; 10 "renesas,pcie-r8a7795" for the R8A7795 SoC; 11 "renesas,pcie-r8a7796" for the R8A7796 SoC; 12 "renesas,pcie-r8a77980" for the R8A77980 SoC; 13 "renesas,pcie-r8a77990" for the R8A77990 SoC; 14 "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or 15 RZ/G1 compatible device. 16 "renesas,pcie-rcar-gen3" for a generic R-Car Gen3 compatible device. 17 18 When compatible with the generic version, nodes must list the 19 SoC-specific version corresponding to the platform first 20 followed by the generic version. 21 22- reg: base address and length of the PCIe controller registers. 23- #address-cells: set to <3> 24- #size-cells: set to <2> 25- bus-range: PCI bus numbers covered 26- device_type: set to "pci" 27- ranges: ranges for the PCI memory and I/O regions. 28- dma-ranges: ranges for the inbound memory regions. 29- interrupts: two interrupt sources for MSI interrupts, followed by interrupt 30 source for hardware related interrupts (e.g. link speed change). 31- #interrupt-cells: set to <1> 32- interrupt-map-mask and interrupt-map: standard PCI properties 33 to define the mapping of the PCIe interface to interrupt numbers. 34- clocks: from common clock binding: clock specifiers for the PCIe controller 35 and PCIe bus clocks. 36- clock-names: from common clock binding: should be "pcie" and "pcie_bus". 37 38Optional properties: 39- phys: from common PHY binding: PHY phandle and specifier (only make sense 40 for R-Car gen3 SoCs where the PCIe PHYs have their own register blocks). 41- phy-names: from common PHY binding: should be "pcie". 42 43Example: 44 45SoC-specific DT Entry: 46 47 pcie: pcie@fe000000 { 48 compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2"; 49 reg = <0 0xfe000000 0 0x80000>; 50 #address-cells = <3>; 51 #size-cells = <2>; 52 bus-range = <0x00 0xff>; 53 device_type = "pci"; 54 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 55 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 56 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 57 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 58 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000 59 0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>; 60 interrupts = <0 116 4>, <0 117 4>, <0 118 4>; 61 #interrupt-cells = <1>; 62 interrupt-map-mask = <0 0 0 0>; 63 interrupt-map = <0 0 0 0 &gic 0 116 4>; 64 clocks = <&mstp3_clks R8A7791_CLK_PCIE>, <&pcie_bus_clk>; 65 clock-names = "pcie", "pcie_bus"; 66 };