kernel / Documentation / devicetree / bindings / net / dsa / dsa.txt

Distributed Switch Architecture Device Tree Bindings
----------------------------------------------------

Two bindings exist, one of which has been deprecated due to
limitations.

Current Binding
---------------

Switches are true Linux devices and can be probed by any means. Once
probed, they register to the DSA framework, passing a node
pointer. This node is expected to fulfil the following binding, and
may contain additional properties as required by the device it is
embedded within.

Required properties:

- ports		: A container for child nodes representing switch ports.

Optional properties:

- dsa,member	: A two element list indicates which DSA cluster, and position
		  within the cluster a switch takes. <0 0> is cluster 0,
		  switch 0. <0 1> is cluster 0, switch 1. <1 0> is cluster 1,
		  switch 0. A switch not part of any cluster (single device
		  hanging off a CPU port) must not specify this property

The ports container has the following properties

Required properties:

- #address-cells	: Must be 1
- #size-cells		: Must be 0

Each port children node must have the following mandatory properties:
- reg			: Describes the port address in the switch

An uplink/downlink port between switches in the cluster has the following
mandatory property:

- link			: Should be a list of phandles to other switch's DSA
			  port. This port is used as the outgoing port
			  towards the phandle ports. The full routing
			  information must be given, not just the one hop
			  routes to neighbouring switches.

A CPU port has the following mandatory property:

- ethernet		: Should be a phandle to a valid Ethernet device node.
                          This host device is what the switch port is
			  connected to.

A user port has the following optional property:

- label			: Describes the label associated with this port, which
                          will become the netdev name.

Port child nodes may also contain the following optional standardised
properties, described in binding documents:

- phy-handle		: Phandle to a PHY on an MDIO bus. See
			  Documentation/devicetree/bindings/net/ethernet.txt
			  for details.

- phy-mode		: See
			  Documentation/devicetree/bindings/net/ethernet.txt
			  for details.

- fixed-link		: Fixed-link subnode describing a link to a non-MDIO
			  managed entity. See
			  Documentation/devicetree/bindings/net/fixed-link.txt
			  for details.

Example

The following example shows three switches on three MDIO busses,
linked into one DSA cluster.

&mdio1 {
	#address-cells = <1>;
	#size-cells = <0>;

	switch0: switch0@0 {
		compatible = "marvell,mv88e6085";
		reg = <0>;

		dsa,member = <0 0>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				label = "lan0";
			};

			port@1 {
				reg = <1>;
				label = "lan1";
			};

			port@2 {
				reg = <2>;
				label = "lan2";
			};

			switch0port5: port@5 {
				reg = <5>;
				phy-mode = "rgmii-txid";
				link = <&switch1port6
					&switch2port9>;
				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};

			port@6 {
				reg = <6>;
				ethernet = <&fec1>;
				fixed-link {
					speed = <100>;
					full-duplex;
				};
			};
		};
	};
};

&mdio2 {
	#address-cells = <1>;
	#size-cells = <0>;

	switch1: switch1@0 {
		compatible = "marvell,mv88e6085";
		reg = <0>;

		dsa,member = <0 1>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				label = "lan3";
				phy-handle = <&switch1phy0>;
			};

			port@1 {
				reg = <1>;
				label = "lan4";
				phy-handle = <&switch1phy1>;
			};

			port@2 {
				reg = <2>;
				label = "lan5";
				phy-handle = <&switch1phy2>;
			};

			switch1port5: port@5 {
				reg = <5>;
				link = <&switch2port9>;
				phy-mode = "rgmii-txid";
				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};

			switch1port6: port@6 {
				reg = <6>;
				phy-mode = "rgmii-txid";
				link = <&switch0port5>;
				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};
		};
		mdio-bus {
			#address-cells = <1>;
			#size-cells = <0>;
			switch1phy0: switch1phy0@0 {
				reg = <0>;
			};
			switch1phy1: switch1phy0@1 {
				reg = <1>;
			};
			switch1phy2: switch1phy0@2 {
				reg = <2>;
			};
		};
	 };
};

&mdio4 {
	#address-cells = <1>;
	#size-cells = <0>;

	switch2: switch2@0 {
		compatible = "marvell,mv88e6085";
		reg = <0>;

		dsa,member = <0 2>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				label = "lan6";
			};

			port@1 {
				reg = <1>;
				label = "lan7";
			};

			port@2 {
				reg = <2>;
				label = "lan8";
			};

			port@3 {
				reg = <3>;
				label = "optical3";
				fixed-link {
					speed = <1000>;
					full-duplex;
					link-gpios = <&gpio6 2
					      GPIO_ACTIVE_HIGH>;
				};
			};

			port@4 {
				reg = <4>;
				label = "optical4";
				fixed-link {
					speed = <1000>;
					full-duplex;
					link-gpios = <&gpio6 3
					      GPIO_ACTIVE_HIGH>;
				};
			};

			switch2port9: port@9 {
				reg = <9>;
				phy-mode = "rgmii-txid";
				link = <&switch1port5
					&switch0port5>;
				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};
		};
	};
};

Deprecated Binding
------------------

The deprecated binding makes use of a platform device to represent the
switches. The switches themselves are not Linux devices, and make use
of an MDIO bus for management.

Required properties:
- compatible		: Should be "marvell,dsa"
- #address-cells	: Must be 2, first cell is the address on the MDIO bus
			  and second cell is the address in the switch tree.
			  Second cell is used only when cascading/chaining.
- #size-cells		: Must be 0
- dsa,ethernet		: Should be a phandle to a valid Ethernet device node
- dsa,mii-bus		: Should be a phandle to a valid MDIO bus device node

Optional properties:
- interrupts		: property with a value describing the switch
			  interrupt number (not supported by the driver)

A DSA node can contain multiple switch chips which are therefore child nodes of
the parent DSA node. The maximum number of allowed child nodes is 4
(DSA_MAX_SWITCHES).
Each of these switch child nodes should have the following required properties:

- reg			: Contains two fields. The first one describes the
			  address on the MII bus. The second is the switch
			  number that must be unique in cascaded configurations
- #address-cells	: Must be 1
- #size-cells		: Must be 0

A switch child node has the following optional property:

- eeprom-length		: Set to the length of an EEPROM connected to the
			  switch. Must be set if the switch can not detect
			  the presence and/or size of a connected EEPROM,
			  otherwise optional.

A switch may have multiple "port" children nodes

Each port children node must have the following mandatory properties:
- reg			: Describes the port address in the switch
- label			: Describes the label associated with this port, special
			  labels are "cpu" to indicate a CPU port and "dsa" to
			  indicate an uplink/downlink port.

Note that a port labelled "dsa" will imply checking for the uplink phandle
described below.

Optional property:
- link			: Should be a list of phandles to another switch's DSA port.
			  This property is only used when switches are being
			  chained/cascaded together. This port is used as outgoing port
			  towards the phandle port, which can be more than one hop away.

- phy-handle		: Phandle to a PHY on an external MDIO bus, not the
			  switch internal one. See
			  Documentation/devicetree/bindings/net/ethernet.txt
			  for details.

- phy-mode		: String representing the connection to the designated
			  PHY node specified by the 'phy-handle' property. See
			  Documentation/devicetree/bindings/net/ethernet.txt
			  for details.

- mii-bus		: Should be a phandle to a valid MDIO bus device node.
			  This mii-bus will be used in preference to the
			  global dsa,mii-bus defined above, for this switch.

Optional subnodes:
- fixed-link		: Fixed-link subnode describing a link to a non-MDIO
			  managed entity. See
			  Documentation/devicetree/bindings/net/fixed-link.txt
			  for details.

Example:

	dsa@0 {
		compatible = "marvell,dsa";
		#address-cells = <2>;
		#size-cells = <0>;

		interrupts = <10>;
		dsa,ethernet = <&ethernet0>;
		dsa,mii-bus = <&mii_bus0>;

		switch@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <16 0>;	/* MDIO address 16, switch 0 in tree */

			port@0 {
				reg = <0>;
				label = "lan1";
				phy-handle = <&phy0>;
			};

			port@1 {
				reg = <1>;
				label = "lan2";
			};

			port@5 {
				reg = <5>;
				label = "cpu";
			};

			switch0port6: port@6 {
				reg = <6>;
				label = "dsa";
				link = <&switch1port0
				        &switch2port0>;
			};
		};

		switch@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <17 1>;	/* MDIO address 17, switch 1 in tree */
			mii-bus = <&mii_bus1>;
			reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;

			switch1port0: port@0 {
				reg = <0>;
				label = "dsa";
				link = <&switch0port6>;
			};
			switch1port1: port@1 {
				reg = <1>;
				label = "dsa";
				link = <&switch2port1>;
			};
		};

		switch@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <18 2>;	/* MDIO address 18, switch 2 in tree */
			mii-bus = <&mii_bus1>;

			switch2port0: port@0 {
				reg = <0>;
				label = "dsa";
				link = <&switch1port1
				        &switch0port6>;
			};
		};
	};