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linux
1#
2# EDAC Kconfig
3# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
4# Licensed and distributed under the GPL
5
6config EDAC_ATOMIC_SCRUB
7 bool
8
9config EDAC_SUPPORT
10 bool
11
12menuconfig EDAC
13 tristate "EDAC (Error Detection And Correction) reporting"
14 depends on HAS_IOMEM && EDAC_SUPPORT && RAS
15 help
16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
18 in the CPU or supporting chipset or other subsystems:
19 memory errors, cache errors, PCI errors, thermal throttling, etc..
20 If unsure, select 'Y'.
21
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
23
24if EDAC
25
26config EDAC_LEGACY_SYSFS
27 bool "EDAC legacy sysfs"
28 default y
29 help
30 Enable the compatibility sysfs nodes.
31 Use 'Y' if your edac utilities aren't ported to work with the newer
32 structures.
33
34config EDAC_DEBUG
35 bool "Debugging"
36 select DEBUG_FS
37 help
38 This turns on debugging information for the entire EDAC subsystem.
39 You do so by inserting edac_module with "edac_debug_level=x." Valid
40 levels are 0-4 (from low to high) and by default it is set to 2.
41 Usually you should select 'N' here.
42
43config EDAC_DECODE_MCE
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
45 depends on CPU_SUP_AMD && X86_MCE_AMD
46 default y
47 ---help---
48 Enable this option if you want to decode Machine Check Exceptions
49 occurring on your machine in human-readable form.
50
51 You should definitely say Y here in case you want to decode MCEs
52 which occur really early upon boot, before the module infrastructure
53 has been initialized.
54
55config EDAC_GHES
56 bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
57 depends on ACPI_APEI_GHES && (EDAC=y)
58 help
59 Not all machines support hardware-driven error report. Some of those
60 provide a BIOS-driven error report mechanism via ACPI, using the
61 APEI/GHES driver. By enabling this option, the error reports provided
62 by GHES are sent to userspace via the EDAC API.
63
64 When this option is enabled, it will disable the hardware-driven
65 mechanisms, if a GHES BIOS is detected, entering into the
66 "Firmware First" mode.
67
68 It should be noticed that keeping both GHES and a hardware-driven
69 error mechanism won't work well, as BIOS will race with OS, while
70 reading the error registers. So, if you want to not use "Firmware
71 first" GHES error mechanism, you should disable GHES either at
72 compilation time or by passing "ghes.disable=1" Kernel parameter
73 at boot time.
74
75 In doubt, say 'Y'.
76
77config EDAC_AMD64
78 tristate "AMD64 (Opteron, Athlon64)"
79 depends on AMD_NB && EDAC_DECODE_MCE
80 help
81 Support for error detection and correction of DRAM ECC errors on
82 the AMD64 families (>= K8) of memory controllers.
83
84config EDAC_AMD64_ERROR_INJECTION
85 bool "Sysfs HW Error injection facilities"
86 depends on EDAC_AMD64
87 help
88 Recent Opterons (Family 10h and later) provide for Memory Error
89 Injection into the ECC detection circuits. The amd64_edac module
90 allows the operator/user to inject Uncorrectable and Correctable
91 errors into DRAM.
92
93 When enabled, in each of the respective memory controller directories
94 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
95
96 - inject_section (0..3, 16-byte section of 64-byte cacheline),
97 - inject_word (0..8, 16-bit word of 16-byte section),
98 - inject_ecc_vector (hex ecc vector: select bits of inject word)
99
100 In addition, there are two control files, inject_read and inject_write,
101 which trigger the DRAM ECC Read and Write respectively.
102
103config EDAC_AMD76X
104 tristate "AMD 76x (760, 762, 768)"
105 depends on PCI && X86_32
106 help
107 Support for error detection and correction on the AMD 76x
108 series of chipsets used with the Athlon processor.
109
110config EDAC_E7XXX
111 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
112 depends on PCI && X86_32
113 help
114 Support for error detection and correction on the Intel
115 E7205, E7500, E7501 and E7505 server chipsets.
116
117config EDAC_E752X
118 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
119 depends on PCI && X86
120 help
121 Support for error detection and correction on the Intel
122 E7520, E7525, E7320 server chipsets.
123
124config EDAC_I82443BXGX
125 tristate "Intel 82443BX/GX (440BX/GX)"
126 depends on PCI && X86_32
127 depends on BROKEN
128 help
129 Support for error detection and correction on the Intel
130 82443BX/GX memory controllers (440BX/GX chipsets).
131
132config EDAC_I82875P
133 tristate "Intel 82875p (D82875P, E7210)"
134 depends on PCI && X86_32
135 help
136 Support for error detection and correction on the Intel
137 DP82785P and E7210 server chipsets.
138
139config EDAC_I82975X
140 tristate "Intel 82975x (D82975x)"
141 depends on PCI && X86
142 help
143 Support for error detection and correction on the Intel
144 DP82975x server chipsets.
145
146config EDAC_I3000
147 tristate "Intel 3000/3010"
148 depends on PCI && X86
149 help
150 Support for error detection and correction on the Intel
151 3000 and 3010 server chipsets.
152
153config EDAC_I3200
154 tristate "Intel 3200"
155 depends on PCI && X86
156 help
157 Support for error detection and correction on the Intel
158 3200 and 3210 server chipsets.
159
160config EDAC_IE31200
161 tristate "Intel e312xx"
162 depends on PCI && X86
163 help
164 Support for error detection and correction on the Intel
165 E3-1200 based DRAM controllers.
166
167config EDAC_X38
168 tristate "Intel X38"
169 depends on PCI && X86
170 help
171 Support for error detection and correction on the Intel
172 X38 server chipsets.
173
174config EDAC_I5400
175 tristate "Intel 5400 (Seaburg) chipsets"
176 depends on PCI && X86
177 help
178 Support for error detection and correction the Intel
179 i5400 MCH chipset (Seaburg).
180
181config EDAC_I7CORE
182 tristate "Intel i7 Core (Nehalem) processors"
183 depends on PCI && X86 && X86_MCE_INTEL
184 help
185 Support for error detection and correction the Intel
186 i7 Core (Nehalem) Integrated Memory Controller that exists on
187 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
188 and Xeon 55xx processors.
189
190config EDAC_I82860
191 tristate "Intel 82860"
192 depends on PCI && X86_32
193 help
194 Support for error detection and correction on the Intel
195 82860 chipset.
196
197config EDAC_R82600
198 tristate "Radisys 82600 embedded chipset"
199 depends on PCI && X86_32
200 help
201 Support for error detection and correction on the Radisys
202 82600 embedded chipset.
203
204config EDAC_I5000
205 tristate "Intel Greencreek/Blackford chipset"
206 depends on X86 && PCI
207 help
208 Support for error detection and correction the Intel
209 Greekcreek/Blackford chipsets.
210
211config EDAC_I5100
212 tristate "Intel San Clemente MCH"
213 depends on X86 && PCI
214 help
215 Support for error detection and correction the Intel
216 San Clemente MCH.
217
218config EDAC_I7300
219 tristate "Intel Clarksboro MCH"
220 depends on X86 && PCI
221 help
222 Support for error detection and correction the Intel
223 Clarksboro MCH (Intel 7300 chipset).
224
225config EDAC_SBRIDGE
226 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
227 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
228 help
229 Support for error detection and correction the Intel
230 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
231
232config EDAC_SKX
233 tristate "Intel Skylake server Integrated MC"
234 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
235 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y
236 select DMI
237 select ACPI_ADXL
238 help
239 Support for error detection and correction the Intel
240 Skylake server Integrated Memory Controllers. If your
241 system has non-volatile DIMMs you should also manually
242 select CONFIG_ACPI_NFIT.
243
244config EDAC_PND2
245 tristate "Intel Pondicherry2"
246 depends on PCI && X86_64 && X86_MCE_INTEL
247 help
248 Support for error detection and correction on the Intel
249 Pondicherry2 Integrated Memory Controller. This SoC IP is
250 first used on the Apollo Lake platform and Denverton
251 micro-server but may appear on others in the future.
252
253config EDAC_MPC85XX
254 tristate "Freescale MPC83xx / MPC85xx"
255 depends on FSL_SOC
256 help
257 Support for error detection and correction on the Freescale
258 MPC8349, MPC8560, MPC8540, MPC8548, T4240
259
260config EDAC_LAYERSCAPE
261 tristate "Freescale Layerscape DDR"
262 depends on ARCH_LAYERSCAPE || SOC_LS1021A
263 help
264 Support for error detection and correction on Freescale memory
265 controllers on Layerscape SoCs.
266
267config EDAC_MV64X60
268 tristate "Marvell MV64x60"
269 depends on MV64X60
270 help
271 Support for error detection and correction on the Marvell
272 MV64360 and MV64460 chipsets.
273
274config EDAC_PASEMI
275 tristate "PA Semi PWRficient"
276 depends on PPC_PASEMI && PCI
277 help
278 Support for error detection and correction on PA Semi
279 PWRficient.
280
281config EDAC_CELL
282 tristate "Cell Broadband Engine memory controller"
283 depends on PPC_CELL_COMMON
284 help
285 Support for error detection and correction on the
286 Cell Broadband Engine internal memory controller
287 on platform without a hypervisor
288
289config EDAC_PPC4XX
290 tristate "PPC4xx IBM DDR2 Memory Controller"
291 depends on 4xx
292 help
293 This enables support for EDAC on the ECC memory used
294 with the IBM DDR2 memory controller found in various
295 PowerPC 4xx embedded processors such as the 405EX[r],
296 440SP, 440SPe, 460EX, 460GT and 460SX.
297
298config EDAC_AMD8131
299 tristate "AMD8131 HyperTransport PCI-X Tunnel"
300 depends on PCI && PPC_MAPLE
301 help
302 Support for error detection and correction on the
303 AMD8131 HyperTransport PCI-X Tunnel chip.
304 Note, add more Kconfig dependency if it's adopted
305 on some machine other than Maple.
306
307config EDAC_AMD8111
308 tristate "AMD8111 HyperTransport I/O Hub"
309 depends on PCI && PPC_MAPLE
310 help
311 Support for error detection and correction on the
312 AMD8111 HyperTransport I/O Hub chip.
313 Note, add more Kconfig dependency if it's adopted
314 on some machine other than Maple.
315
316config EDAC_CPC925
317 tristate "IBM CPC925 Memory Controller (PPC970FX)"
318 depends on PPC64
319 help
320 Support for error detection and correction on the
321 IBM CPC925 Bridge and Memory Controller, which is
322 a companion chip to the PowerPC 970 family of
323 processors.
324
325config EDAC_HIGHBANK_MC
326 tristate "Highbank Memory Controller"
327 depends on ARCH_HIGHBANK
328 help
329 Support for error detection and correction on the
330 Calxeda Highbank memory controller.
331
332config EDAC_HIGHBANK_L2
333 tristate "Highbank L2 Cache"
334 depends on ARCH_HIGHBANK
335 help
336 Support for error detection and correction on the
337 Calxeda Highbank memory controller.
338
339config EDAC_OCTEON_PC
340 tristate "Cavium Octeon Primary Caches"
341 depends on CPU_CAVIUM_OCTEON
342 help
343 Support for error detection and correction on the primary caches of
344 the cnMIPS cores of Cavium Octeon family SOCs.
345
346config EDAC_OCTEON_L2C
347 tristate "Cavium Octeon Secondary Caches (L2C)"
348 depends on CAVIUM_OCTEON_SOC
349 help
350 Support for error detection and correction on the
351 Cavium Octeon family of SOCs.
352
353config EDAC_OCTEON_LMC
354 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
355 depends on CAVIUM_OCTEON_SOC
356 help
357 Support for error detection and correction on the
358 Cavium Octeon family of SOCs.
359
360config EDAC_OCTEON_PCI
361 tristate "Cavium Octeon PCI Controller"
362 depends on PCI && CAVIUM_OCTEON_SOC
363 help
364 Support for error detection and correction on the
365 Cavium Octeon family of SOCs.
366
367config EDAC_THUNDERX
368 tristate "Cavium ThunderX EDAC"
369 depends on ARM64
370 depends on PCI
371 help
372 Support for error detection and correction on the
373 Cavium ThunderX memory controllers (LMC), Cache
374 Coherent Processor Interconnect (CCPI) and L2 cache
375 blocks (TAD, CBC, MCI).
376
377config EDAC_ALTERA
378 bool "Altera SOCFPGA ECC"
379 depends on EDAC=y && (ARCH_SOCFPGA || ARCH_STRATIX10)
380 help
381 Support for error detection and correction on the
382 Altera SOCs. This must be selected for SDRAM ECC.
383 Note that the preloader must initialize the SDRAM
384 before loading the kernel.
385
386config EDAC_ALTERA_L2C
387 bool "Altera L2 Cache ECC"
388 depends on EDAC_ALTERA=y && CACHE_L2X0
389 help
390 Support for error detection and correction on the
391 Altera L2 cache Memory for Altera SoCs. This option
392 requires L2 cache.
393
394config EDAC_ALTERA_OCRAM
395 bool "Altera On-Chip RAM ECC"
396 depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
397 help
398 Support for error detection and correction on the
399 Altera On-Chip RAM Memory for Altera SoCs.
400
401config EDAC_ALTERA_ETHERNET
402 bool "Altera Ethernet FIFO ECC"
403 depends on EDAC_ALTERA=y
404 help
405 Support for error detection and correction on the
406 Altera Ethernet FIFO Memory for Altera SoCs.
407
408config EDAC_ALTERA_NAND
409 bool "Altera NAND FIFO ECC"
410 depends on EDAC_ALTERA=y && MTD_NAND_DENALI
411 help
412 Support for error detection and correction on the
413 Altera NAND FIFO Memory for Altera SoCs.
414
415config EDAC_ALTERA_DMA
416 bool "Altera DMA FIFO ECC"
417 depends on EDAC_ALTERA=y && PL330_DMA=y
418 help
419 Support for error detection and correction on the
420 Altera DMA FIFO Memory for Altera SoCs.
421
422config EDAC_ALTERA_USB
423 bool "Altera USB FIFO ECC"
424 depends on EDAC_ALTERA=y && USB_DWC2
425 help
426 Support for error detection and correction on the
427 Altera USB FIFO Memory for Altera SoCs.
428
429config EDAC_ALTERA_QSPI
430 bool "Altera QSPI FIFO ECC"
431 depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
432 help
433 Support for error detection and correction on the
434 Altera QSPI FIFO Memory for Altera SoCs.
435
436config EDAC_ALTERA_SDMMC
437 bool "Altera SDMMC FIFO ECC"
438 depends on EDAC_ALTERA=y && MMC_DW
439 help
440 Support for error detection and correction on the
441 Altera SDMMC FIFO Memory for Altera SoCs.
442
443config EDAC_SYNOPSYS
444 tristate "Synopsys DDR Memory Controller"
445 depends on ARCH_ZYNQ || ARCH_ZYNQMP
446 help
447 Support for error detection and correction on the Synopsys DDR
448 memory controller.
449
450config EDAC_XGENE
451 tristate "APM X-Gene SoC"
452 depends on (ARM64 || COMPILE_TEST)
453 help
454 Support for error detection and correction on the
455 APM X-Gene family of SOCs.
456
457config EDAC_TI
458 tristate "Texas Instruments DDR3 ECC Controller"
459 depends on ARCH_KEYSTONE || SOC_DRA7XX
460 help
461 Support for error detection and correction on the
462 TI SoCs.
463
464config EDAC_QCOM
465 tristate "QCOM EDAC Controller"
466 depends on ARCH_QCOM && QCOM_LLCC
467 help
468 Support for error detection and correction on the
469 Qualcomm Technologies, Inc. SoCs.
470
471 This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).
472 As of now, it supports error reporting for Last Level Cache Controller (LLCC)
473 of Tag RAM and Data RAM.
474
475 For debugging issues having to do with stability and overall system
476 health, you should probably say 'Y' here.
477
478endif # EDAC