tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __KGD_PP_INTERFACE_H__
25#define __KGD_PP_INTERFACE_H__
26
27extern const struct amdgpu_ip_block_version pp_smu_ip_block;
28
29struct amd_vce_state {
30 /* vce clocks */
31 u32 evclk;
32 u32 ecclk;
33 /* gpu clocks */
34 u32 sclk;
35 u32 mclk;
36 u8 clk_idx;
37 u8 pstate;
38};
39
40
41enum amd_dpm_forced_level {
42 AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
43 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
44 AMD_DPM_FORCED_LEVEL_LOW = 0x4,
45 AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
46 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
47 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
48 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
49 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
50 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
51};
52
53enum amd_pm_state_type {
54 /* not used for dpm */
55 POWER_STATE_TYPE_DEFAULT,
56 POWER_STATE_TYPE_POWERSAVE,
57 /* user selectable states */
58 POWER_STATE_TYPE_BATTERY,
59 POWER_STATE_TYPE_BALANCED,
60 POWER_STATE_TYPE_PERFORMANCE,
61 /* internal states */
62 POWER_STATE_TYPE_INTERNAL_UVD,
63 POWER_STATE_TYPE_INTERNAL_UVD_SD,
64 POWER_STATE_TYPE_INTERNAL_UVD_HD,
65 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
66 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
67 POWER_STATE_TYPE_INTERNAL_BOOT,
68 POWER_STATE_TYPE_INTERNAL_THERMAL,
69 POWER_STATE_TYPE_INTERNAL_ACPI,
70 POWER_STATE_TYPE_INTERNAL_ULV,
71 POWER_STATE_TYPE_INTERNAL_3DPERF,
72};
73
74#define AMD_MAX_VCE_LEVELS 6
75
76enum amd_vce_level {
77 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
78 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
79 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
80 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
81 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
82 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
83};
84
85enum amd_fan_ctrl_mode {
86 AMD_FAN_CTRL_NONE = 0,
87 AMD_FAN_CTRL_MANUAL = 1,
88 AMD_FAN_CTRL_AUTO = 2,
89};
90
91enum pp_clock_type {
92 PP_SCLK,
93 PP_MCLK,
94 PP_PCIE,
95 OD_SCLK,
96 OD_MCLK,
97 OD_VDDC_CURVE,
98 OD_RANGE,
99};
100
101enum amd_pp_sensors {
102 AMDGPU_PP_SENSOR_GFX_SCLK = 0,
103 AMDGPU_PP_SENSOR_VDDNB,
104 AMDGPU_PP_SENSOR_VDDGFX,
105 AMDGPU_PP_SENSOR_UVD_VCLK,
106 AMDGPU_PP_SENSOR_UVD_DCLK,
107 AMDGPU_PP_SENSOR_VCE_ECCLK,
108 AMDGPU_PP_SENSOR_GPU_LOAD,
109 AMDGPU_PP_SENSOR_GFX_MCLK,
110 AMDGPU_PP_SENSOR_GPU_TEMP,
111 AMDGPU_PP_SENSOR_VCE_POWER,
112 AMDGPU_PP_SENSOR_UVD_POWER,
113 AMDGPU_PP_SENSOR_GPU_POWER,
114 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
115 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
116 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
117 AMDGPU_PP_SENSOR_MIN_FAN_RPM,
118 AMDGPU_PP_SENSOR_MAX_FAN_RPM,
119};
120
121enum amd_pp_task {
122 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
123 AMD_PP_TASK_ENABLE_USER_STATE,
124 AMD_PP_TASK_READJUST_POWER_STATE,
125 AMD_PP_TASK_COMPLETE_INIT,
126 AMD_PP_TASK_MAX
127};
128
129enum PP_SMC_POWER_PROFILE {
130 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0,
131 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1,
132 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2,
133 PP_SMC_POWER_PROFILE_VIDEO = 0x3,
134 PP_SMC_POWER_PROFILE_VR = 0x4,
135 PP_SMC_POWER_PROFILE_COMPUTE = 0x5,
136 PP_SMC_POWER_PROFILE_CUSTOM = 0x6,
137};
138
139enum {
140 PP_GROUP_UNKNOWN = 0,
141 PP_GROUP_GFX = 1,
142 PP_GROUP_SYS,
143 PP_GROUP_MAX
144};
145
146enum PP_OD_DPM_TABLE_COMMAND {
147 PP_OD_EDIT_SCLK_VDDC_TABLE,
148 PP_OD_EDIT_MCLK_VDDC_TABLE,
149 PP_OD_EDIT_VDDC_CURVE,
150 PP_OD_RESTORE_DEFAULT_TABLE,
151 PP_OD_COMMIT_DPM_TABLE
152};
153
154struct pp_states_info {
155 uint32_t nums;
156 uint32_t states[16];
157};
158
159#define PP_GROUP_MASK 0xF0000000
160#define PP_GROUP_SHIFT 28
161
162#define PP_BLOCK_MASK 0x0FFFFF00
163#define PP_BLOCK_SHIFT 8
164
165#define PP_BLOCK_GFX_CG 0x01
166#define PP_BLOCK_GFX_MG 0x02
167#define PP_BLOCK_GFX_3D 0x04
168#define PP_BLOCK_GFX_RLC 0x08
169#define PP_BLOCK_GFX_CP 0x10
170#define PP_BLOCK_SYS_BIF 0x01
171#define PP_BLOCK_SYS_MC 0x02
172#define PP_BLOCK_SYS_ROM 0x04
173#define PP_BLOCK_SYS_DRM 0x08
174#define PP_BLOCK_SYS_HDP 0x10
175#define PP_BLOCK_SYS_SDMA 0x20
176
177#define PP_STATE_MASK 0x0000000F
178#define PP_STATE_SHIFT 0
179#define PP_STATE_SUPPORT_MASK 0x000000F0
180#define PP_STATE_SUPPORT_SHIFT 0
181
182#define PP_STATE_CG 0x01
183#define PP_STATE_LS 0x02
184#define PP_STATE_DS 0x04
185#define PP_STATE_SD 0x08
186#define PP_STATE_SUPPORT_CG 0x10
187#define PP_STATE_SUPPORT_LS 0x20
188#define PP_STATE_SUPPORT_DS 0x40
189#define PP_STATE_SUPPORT_SD 0x80
190
191#define PP_CG_MSG_ID(group, block, support, state) \
192 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
193 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
194
195struct seq_file;
196enum amd_pp_clock_type;
197struct amd_pp_simple_clock_info;
198struct amd_pp_display_configuration;
199struct amd_pp_clock_info;
200struct pp_display_clock_request;
201struct pp_clock_levels_with_voltage;
202struct pp_clock_levels_with_latency;
203struct amd_pp_clocks;
204
205struct amd_pm_funcs {
206/* export for dpm on ci and si */
207 int (*pre_set_power_state)(void *handle);
208 int (*set_power_state)(void *handle);
209 void (*post_set_power_state)(void *handle);
210 void (*display_configuration_changed)(void *handle);
211 void (*print_power_state)(void *handle, void *ps);
212 bool (*vblank_too_short)(void *handle);
213 void (*enable_bapm)(void *handle, bool enable);
214 int (*check_state_equal)(void *handle,
215 void *cps,
216 void *rps,
217 bool *equal);
218/* export for sysfs */
219 void (*set_fan_control_mode)(void *handle, u32 mode);
220 u32 (*get_fan_control_mode)(void *handle);
221 int (*set_fan_speed_percent)(void *handle, u32 speed);
222 int (*get_fan_speed_percent)(void *handle, u32 *speed);
223 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
224 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
225 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
226 int (*get_sclk_od)(void *handle);
227 int (*set_sclk_od)(void *handle, uint32_t value);
228 int (*get_mclk_od)(void *handle);
229 int (*set_mclk_od)(void *handle, uint32_t value);
230 int (*read_sensor)(void *handle, int idx, void *value, int *size);
231 enum amd_dpm_forced_level (*get_performance_level)(void *handle);
232 enum amd_pm_state_type (*get_current_power_state)(void *handle);
233 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
234 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm);
235 int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
236 int (*get_pp_table)(void *handle, char **table);
237 int (*set_pp_table)(void *handle, const char *buf, size_t size);
238 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
239 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
240/* export to amdgpu */
241 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
242 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
243 enum amd_pm_state_type *user_state);
244 int (*load_firmware)(void *handle);
245 int (*wait_for_fw_loading_complete)(void *handle);
246 int (*set_powergating_by_smu)(void *handle,
247 uint32_t block_type, bool gate);
248 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
249 int (*set_power_limit)(void *handle, uint32_t n);
250 int (*get_power_limit)(void *handle, uint32_t *limit, bool default_limit);
251 int (*get_power_profile_mode)(void *handle, char *buf);
252 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
253 int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
254/* export to DC */
255 u32 (*get_sclk)(void *handle, bool low);
256 u32 (*get_mclk)(void *handle, bool low);
257 int (*display_configuration_change)(void *handle,
258 const struct amd_pp_display_configuration *input);
259 int (*get_display_power_level)(void *handle,
260 struct amd_pp_simple_clock_info *output);
261 int (*get_current_clocks)(void *handle,
262 struct amd_pp_clock_info *clocks);
263 int (*get_clock_by_type)(void *handle,
264 enum amd_pp_clock_type type,
265 struct amd_pp_clocks *clocks);
266 int (*get_clock_by_type_with_latency)(void *handle,
267 enum amd_pp_clock_type type,
268 struct pp_clock_levels_with_latency *clocks);
269 int (*get_clock_by_type_with_voltage)(void *handle,
270 enum amd_pp_clock_type type,
271 struct pp_clock_levels_with_voltage *clocks);
272 int (*set_watermarks_for_clocks_ranges)(void *handle,
273 void *clock_ranges);
274 int (*display_clock_voltage_request)(void *handle,
275 struct pp_display_clock_request *clock);
276 int (*get_display_mode_validation_clocks)(void *handle,
277 struct amd_pp_simple_clock_info *clocks);
278 int (*notify_smu_enable_pwe)(void *handle);
279 int (*enable_mgpu_fan_boost)(void *handle);
280 int (*set_active_display_count)(void *handle, uint32_t count);
281 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
282 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
283 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
284};
285
286#endif