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1* Samsung Exynos5433 CMU (Clock Management Units)
2
3The Exynos5433 clock controller generates and supplies clock to various
4controllers within the Exynos5433 SoC.
5
6Required Properties:
7
8- compatible: should be one of the following.
9 - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
10 which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
11 domains and bus clocks.
12 - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
13 which generates clocks for LLI (Low Latency Interface) IP.
14 - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
15 which generates clocks for DRAM Memory Controller domain.
16 - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
17 which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
18 - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
19 which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
20 - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
21 which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
22 - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
23 which generates clocks for G2D/MDMA IPs.
24 - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP
25 which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
26 - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD
27 which generates clocks for Cortex-A5/BUS/AUDIO clocks.
28 - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1"
29 and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS
30 which generates global data buses clock and global peripheral buses clock.
31 - "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D
32 which generates clocks for 3D Graphics Engine IP.
33 - "samsung,exynos5433-cmu-gscl" - clock controller compatible for CMU_GSCL
34 which generates clocks for GSCALER IPs.
35 - "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO
36 which generates clocks for Cortex-A53 Quad-core processor.
37 - "samsung,exynos5433-cmu-atlas" - clock controller compatible for CMU_ATLAS
38 which generates clocks for Cortex-A57 Quad-core processor, CoreSight and
39 L2 cache controller.
40 - "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL
41 which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs.
42 - "samsung,exynos5433-cmu-mfc" - clock controller compatible for CMU_MFC
43 which generates clocks for MFC(Multi-Format Codec) IP.
44 - "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC
45 which generates clocks for HEVC(High Efficiency Video Codec) decoder IP.
46 - "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP
47 which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.
48 - "samsung,exynos5433-cmu-cam0" - clock controller compatible for CMU_CAM0
49 which generates clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1}
50 IPs.
51 - "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1
52 which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs.
53
54- reg: physical base address of the controller and length of memory mapped
55 region.
56
57- #clock-cells: should be 1.
58
59- clocks: list of the clock controller input clock identifiers,
60 from common clock bindings. Please refer the next section
61 to find the input clocks for a given controller.
62
63- clock-names: list of the clock controller input clock names,
64 as described in clock-bindings.txt.
65
66 Input clocks for top clock controller:
67 - oscclk
68 - sclk_mphy_pll
69 - sclk_mfc_pll
70 - sclk_bus_pll
71
72 Input clocks for cpif clock controller:
73 - oscclk
74
75 Input clocks for mif clock controller:
76 - oscclk
77 - sclk_mphy_pll
78
79 Input clocks for fsys clock controller:
80 - oscclk
81 - sclk_ufs_mphy
82 - aclk_fsys_200
83 - sclk_pcie_100_fsys
84 - sclk_ufsunipro_fsys
85 - sclk_mmc2_fsys
86 - sclk_mmc1_fsys
87 - sclk_mmc0_fsys
88 - sclk_usbhost30_fsys
89 - sclk_usbdrd30_fsys
90
91 Input clocks for g2d clock controller:
92 - oscclk
93 - aclk_g2d_266
94 - aclk_g2d_400
95
96 Input clocks for disp clock controller:
97 - oscclk
98 - sclk_dsim1_disp
99 - sclk_dsim0_disp
100 - sclk_dsd_disp
101 - sclk_decon_tv_eclk_disp
102 - sclk_decon_vclk_disp
103 - sclk_decon_eclk_disp
104 - sclk_decon_tv_vclk_disp
105 - aclk_disp_333
106
107 Input clocks for audio clock controller:
108 - oscclk
109 - fout_aud_pll
110
111 Input clocks for bus0 clock controller:
112 - aclk_bus0_400
113
114 Input clocks for bus1 clock controller:
115 - aclk_bus1_400
116
117 Input clocks for bus2 clock controller:
118 - oscclk
119 - aclk_bus2_400
120
121 Input clocks for g3d clock controller:
122 - oscclk
123 - aclk_g3d_400
124
125 Input clocks for gscl clock controller:
126 - oscclk
127 - aclk_gscl_111
128 - aclk_gscl_333
129
130 Input clocks for apollo clock controller:
131 - oscclk
132 - sclk_bus_pll_apollo
133
134 Input clocks for atlas clock controller:
135 - oscclk
136 - sclk_bus_pll_atlas
137
138 Input clocks for mscl clock controller:
139 - oscclk
140 - sclk_jpeg_mscl
141 - aclk_mscl_400
142
143 Input clocks for mfc clock controller:
144 - oscclk
145 - aclk_mfc_400
146
147 Input clocks for hevc clock controller:
148 - oscclk
149 - aclk_hevc_400
150
151 Input clocks for isp clock controller:
152 - oscclk
153 - aclk_isp_dis_400
154 - aclk_isp_400
155
156 Input clocks for cam0 clock controller:
157 - oscclk
158 - aclk_cam0_333
159 - aclk_cam0_400
160 - aclk_cam0_552
161
162 Input clocks for cam1 clock controller:
163 - oscclk
164 - sclk_isp_uart_cam1
165 - sclk_isp_spi1_cam1
166 - sclk_isp_spi0_cam1
167 - aclk_cam1_333
168 - aclk_cam1_400
169 - aclk_cam1_552
170
171Optional properties:
172 - power-domains: a phandle to respective power domain node as described by
173 generic PM domain bindings (see power/power_domain.txt for more
174 information).
175
176Each clock is assigned an identifier and client nodes can use this identifier
177to specify the clock which they consume.
178
179All available clocks are defined as preprocessor macros in
180dt-bindings/clock/exynos5433.h header and can be used in device
181tree sources.
182
183Example 1: Examples of 'oscclk' source clock node are listed below.
184
185 xxti: xxti {
186 compatible = "fixed-clock";
187 clock-output-names = "oscclk";
188 #clock-cells = <0>;
189 };
190
191Example 2: Examples of clock controller nodes are listed below.
192
193 cmu_top: clock-controller@10030000 {
194 compatible = "samsung,exynos5433-cmu-top";
195 reg = <0x10030000 0x0c04>;
196 #clock-cells = <1>;
197
198 clock-names = "oscclk",
199 "sclk_mphy_pll",
200 "sclk_mfc_pll",
201 "sclk_bus_pll";
202 clocks = <&xxti>,
203 <&cmu_cpif CLK_SCLK_MPHY_PLL>,
204 <&cmu_mif CLK_SCLK_MFC_PLL>,
205 <&cmu_mif CLK_SCLK_BUS_PLL>;
206 };
207
208 cmu_cpif: clock-controller@10fc0000 {
209 compatible = "samsung,exynos5433-cmu-cpif";
210 reg = <0x10fc0000 0x0c04>;
211 #clock-cells = <1>;
212
213 clock-names = "oscclk";
214 clocks = <&xxti>;
215 };
216
217 cmu_mif: clock-controller@105b0000 {
218 compatible = "samsung,exynos5433-cmu-mif";
219 reg = <0x105b0000 0x100c>;
220 #clock-cells = <1>;
221
222 clock-names = "oscclk",
223 "sclk_mphy_pll";
224 clocks = <&xxti>,
225 <&cmu_cpif CLK_SCLK_MPHY_PLL>;
226 };
227
228 cmu_peric: clock-controller@14c80000 {
229 compatible = "samsung,exynos5433-cmu-peric";
230 reg = <0x14c80000 0x0b08>;
231 #clock-cells = <1>;
232 };
233
234 cmu_peris: clock-controller@10040000 {
235 compatible = "samsung,exynos5433-cmu-peris";
236 reg = <0x10040000 0x0b20>;
237 #clock-cells = <1>;
238 };
239
240 cmu_fsys: clock-controller@156e0000 {
241 compatible = "samsung,exynos5433-cmu-fsys";
242 reg = <0x156e0000 0x0b04>;
243 #clock-cells = <1>;
244
245 clock-names = "oscclk",
246 "sclk_ufs_mphy",
247 "aclk_fsys_200",
248 "sclk_pcie_100_fsys",
249 "sclk_ufsunipro_fsys",
250 "sclk_mmc2_fsys",
251 "sclk_mmc1_fsys",
252 "sclk_mmc0_fsys",
253 "sclk_usbhost30_fsys",
254 "sclk_usbdrd30_fsys";
255 clocks = <&xxti>,
256 <&cmu_cpif CLK_SCLK_UFS_MPHY>,
257 <&cmu_top CLK_ACLK_FSYS_200>,
258 <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
259 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
260 <&cmu_top CLK_SCLK_MMC2_FSYS>,
261 <&cmu_top CLK_SCLK_MMC1_FSYS>,
262 <&cmu_top CLK_SCLK_MMC0_FSYS>,
263 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
264 <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
265 };
266
267 cmu_g2d: clock-controller@12460000 {
268 compatible = "samsung,exynos5433-cmu-g2d";
269 reg = <0x12460000 0x0b08>;
270 #clock-cells = <1>;
271
272 clock-names = "oscclk",
273 "aclk_g2d_266",
274 "aclk_g2d_400";
275 clocks = <&xxti>,
276 <&cmu_top CLK_ACLK_G2D_266>,
277 <&cmu_top CLK_ACLK_G2D_400>;
278 power-domains = <&pd_g2d>;
279 };
280
281 cmu_disp: clock-controller@13b90000 {
282 compatible = "samsung,exynos5433-cmu-disp";
283 reg = <0x13b90000 0x0c04>;
284 #clock-cells = <1>;
285
286 clock-names = "oscclk",
287 "sclk_dsim1_disp",
288 "sclk_dsim0_disp",
289 "sclk_dsd_disp",
290 "sclk_decon_tv_eclk_disp",
291 "sclk_decon_vclk_disp",
292 "sclk_decon_eclk_disp",
293 "sclk_decon_tv_vclk_disp",
294 "aclk_disp_333";
295 clocks = <&xxti>,
296 <&cmu_mif CLK_SCLK_DSIM1_DISP>,
297 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
298 <&cmu_mif CLK_SCLK_DSD_DISP>,
299 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
300 <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
301 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
302 <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
303 <&cmu_mif CLK_ACLK_DISP_333>;
304 power-domains = <&pd_disp>;
305 };
306
307 cmu_aud: clock-controller@114c0000 {
308 compatible = "samsung,exynos5433-cmu-aud";
309 reg = <0x114c0000 0x0b04>;
310 #clock-cells = <1>;
311
312 clock-names = "oscclk", "fout_aud_pll";
313 clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
314 power-domains = <&pd_aud>;
315 };
316
317 cmu_bus0: clock-controller@13600000 {
318 compatible = "samsung,exynos5433-cmu-bus0";
319 reg = <0x13600000 0x0b04>;
320 #clock-cells = <1>;
321
322 clock-names = "aclk_bus0_400";
323 clocks = <&cmu_top CLK_ACLK_BUS0_400>;
324 };
325
326 cmu_bus1: clock-controller@14800000 {
327 compatible = "samsung,exynos5433-cmu-bus1";
328 reg = <0x14800000 0x0b04>;
329 #clock-cells = <1>;
330
331 clock-names = "aclk_bus1_400";
332 clocks = <&cmu_top CLK_ACLK_BUS1_400>;
333 };
334
335 cmu_bus2: clock-controller@13400000 {
336 compatible = "samsung,exynos5433-cmu-bus2";
337 reg = <0x13400000 0x0b04>;
338 #clock-cells = <1>;
339
340 clock-names = "oscclk", "aclk_bus2_400";
341 clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
342 };
343
344 cmu_g3d: clock-controller@14aa0000 {
345 compatible = "samsung,exynos5433-cmu-g3d";
346 reg = <0x14aa0000 0x1000>;
347 #clock-cells = <1>;
348
349 clock-names = "oscclk", "aclk_g3d_400";
350 clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
351 power-domains = <&pd_g3d>;
352 };
353
354 cmu_gscl: clock-controller@13cf0000 {
355 compatible = "samsung,exynos5433-cmu-gscl";
356 reg = <0x13cf0000 0x0b10>;
357 #clock-cells = <1>;
358
359 clock-names = "oscclk",
360 "aclk_gscl_111",
361 "aclk_gscl_333";
362 clocks = <&xxti>,
363 <&cmu_top CLK_ACLK_GSCL_111>,
364 <&cmu_top CLK_ACLK_GSCL_333>;
365 power-domains = <&pd_gscl>;
366 };
367
368 cmu_apollo: clock-controller@11900000 {
369 compatible = "samsung,exynos5433-cmu-apollo";
370 reg = <0x11900000 0x1088>;
371 #clock-cells = <1>;
372
373 clock-names = "oscclk", "sclk_bus_pll_apollo";
374 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
375 };
376
377 cmu_atlas: clock-controller@11800000 {
378 compatible = "samsung,exynos5433-cmu-atlas";
379 reg = <0x11800000 0x1088>;
380 #clock-cells = <1>;
381
382 clock-names = "oscclk", "sclk_bus_pll_atlas";
383 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
384 };
385
386 cmu_mscl: clock-controller@105d0000 {
387 compatible = "samsung,exynos5433-cmu-mscl";
388 reg = <0x105d0000 0x0b10>;
389 #clock-cells = <1>;
390
391 clock-names = "oscclk",
392 "sclk_jpeg_mscl",
393 "aclk_mscl_400";
394 clocks = <&xxti>,
395 <&cmu_top CLK_SCLK_JPEG_MSCL>,
396 <&cmu_top CLK_ACLK_MSCL_400>;
397 power-domains = <&pd_mscl>;
398 };
399
400 cmu_mfc: clock-controller@15280000 {
401 compatible = "samsung,exynos5433-cmu-mfc";
402 reg = <0x15280000 0x0b08>;
403 #clock-cells = <1>;
404
405 clock-names = "oscclk", "aclk_mfc_400";
406 clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
407 power-domains = <&pd_mfc>;
408 };
409
410 cmu_hevc: clock-controller@14f80000 {
411 compatible = "samsung,exynos5433-cmu-hevc";
412 reg = <0x14f80000 0x0b08>;
413 #clock-cells = <1>;
414
415 clock-names = "oscclk", "aclk_hevc_400";
416 clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
417 power-domains = <&pd_hevc>;
418 };
419
420 cmu_isp: clock-controller@146d0000 {
421 compatible = "samsung,exynos5433-cmu-isp";
422 reg = <0x146d0000 0x0b0c>;
423 #clock-cells = <1>;
424
425 clock-names = "oscclk",
426 "aclk_isp_dis_400",
427 "aclk_isp_400";
428 clocks = <&xxti>,
429 <&cmu_top CLK_ACLK_ISP_DIS_400>,
430 <&cmu_top CLK_ACLK_ISP_400>;
431 power-domains = <&pd_isp>;
432 };
433
434 cmu_cam0: clock-controller@120d0000 {
435 compatible = "samsung,exynos5433-cmu-cam0";
436 reg = <0x120d0000 0x0b0c>;
437 #clock-cells = <1>;
438
439 clock-names = "oscclk",
440 "aclk_cam0_333",
441 "aclk_cam0_400",
442 "aclk_cam0_552";
443 clocks = <&xxti>,
444 <&cmu_top CLK_ACLK_CAM0_333>,
445 <&cmu_top CLK_ACLK_CAM0_400>,
446 <&cmu_top CLK_ACLK_CAM0_552>;
447 power-domains = <&pd_cam0>;
448 };
449
450 cmu_cam1: clock-controller@145d0000 {
451 compatible = "samsung,exynos5433-cmu-cam1";
452 reg = <0x145d0000 0x0b08>;
453 #clock-cells = <1>;
454
455 clock-names = "oscclk",
456 "sclk_isp_uart_cam1",
457 "sclk_isp_spi1_cam1",
458 "sclk_isp_spi0_cam1",
459 "aclk_cam1_333",
460 "aclk_cam1_400",
461 "aclk_cam1_552";
462 clocks = <&xxti>,
463 <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
464 <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
465 <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
466 <&cmu_top CLK_ACLK_CAM1_333>,
467 <&cmu_top CLK_ACLK_CAM1_400>,
468 <&cmu_top CLK_ACLK_CAM1_552>;
469 power-domains = <&pd_cam1>;
470 };
471
472Example 3: UART controller node that consumes the clock generated by the clock
473 controller.
474
475 serial_0: serial@14c10000 {
476 compatible = "samsung,exynos5433-uart";
477 reg = <0x14C10000 0x100>;
478 interrupts = <0 421 0>;
479 clocks = <&cmu_peric CLK_PCLK_UART0>,
480 <&cmu_peric CLK_SCLK_UART0>;
481 clock-names = "uart", "clk_uart_baud0";
482 pinctrl-names = "default";
483 pinctrl-0 = <&uart0_bus>;
484 };