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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Xilinx Zynq MPSoC Firmware layer
4 *
5 * Copyright (C) 2014-2018 Xilinx
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 * Davorin Mista <davorin.mista@aggios.com>
9 * Jolly Shah <jollys@xilinx.com>
10 * Rajan Vaja <rajanv@xilinx.com>
11 */
12
13#ifndef __FIRMWARE_ZYNQMP_H__
14#define __FIRMWARE_ZYNQMP_H__
15
16#define ZYNQMP_PM_VERSION_MAJOR 1
17#define ZYNQMP_PM_VERSION_MINOR 0
18
19#define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
20 ZYNQMP_PM_VERSION_MINOR)
21
22#define ZYNQMP_TZ_VERSION_MAJOR 1
23#define ZYNQMP_TZ_VERSION_MINOR 0
24
25#define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
26 ZYNQMP_TZ_VERSION_MINOR)
27
28/* SMC SIP service Call Function Identifier Prefix */
29#define PM_SIP_SVC 0xC2000000
30#define PM_GET_TRUSTZONE_VERSION 0xa03
31
32/* Number of 32bits values in payload */
33#define PAYLOAD_ARG_CNT 4U
34
35enum pm_api_id {
36 PM_GET_API_VERSION = 1,
37 PM_IOCTL = 34,
38 PM_QUERY_DATA,
39 PM_CLOCK_ENABLE,
40 PM_CLOCK_DISABLE,
41 PM_CLOCK_GETSTATE,
42 PM_CLOCK_SETDIVIDER,
43 PM_CLOCK_GETDIVIDER,
44 PM_CLOCK_SETRATE,
45 PM_CLOCK_GETRATE,
46 PM_CLOCK_SETPARENT,
47 PM_CLOCK_GETPARENT,
48};
49
50/* PMU-FW return status codes */
51enum pm_ret_status {
52 XST_PM_SUCCESS = 0,
53 XST_PM_INTERNAL = 2000,
54 XST_PM_CONFLICT,
55 XST_PM_NO_ACCESS,
56 XST_PM_INVALID_NODE,
57 XST_PM_DOUBLE_REQ,
58 XST_PM_ABORT_SUSPEND,
59};
60
61enum pm_ioctl_id {
62 IOCTL_SET_PLL_FRAC_MODE = 8,
63 IOCTL_GET_PLL_FRAC_MODE,
64 IOCTL_SET_PLL_FRAC_DATA,
65 IOCTL_GET_PLL_FRAC_DATA,
66};
67
68enum pm_query_id {
69 PM_QID_INVALID,
70 PM_QID_CLOCK_GET_NAME,
71 PM_QID_CLOCK_GET_TOPOLOGY,
72 PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
73 PM_QID_CLOCK_GET_PARENTS,
74 PM_QID_CLOCK_GET_ATTRIBUTES,
75 PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
76};
77
78/**
79 * struct zynqmp_pm_query_data - PM query data
80 * @qid: query ID
81 * @arg1: Argument 1 of query data
82 * @arg2: Argument 2 of query data
83 * @arg3: Argument 3 of query data
84 */
85struct zynqmp_pm_query_data {
86 u32 qid;
87 u32 arg1;
88 u32 arg2;
89 u32 arg3;
90};
91
92struct zynqmp_eemi_ops {
93 int (*get_api_version)(u32 *version);
94 int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
95 int (*clock_enable)(u32 clock_id);
96 int (*clock_disable)(u32 clock_id);
97 int (*clock_getstate)(u32 clock_id, u32 *state);
98 int (*clock_setdivider)(u32 clock_id, u32 divider);
99 int (*clock_getdivider)(u32 clock_id, u32 *divider);
100 int (*clock_setrate)(u32 clock_id, u64 rate);
101 int (*clock_getrate)(u32 clock_id, u64 *rate);
102 int (*clock_setparent)(u32 clock_id, u32 parent_id);
103 int (*clock_getparent)(u32 clock_id, u32 *parent_id);
104 int (*ioctl)(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, u32 *out);
105};
106
107#if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
108const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void);
109#else
110static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
111{
112 return NULL;
113}
114#endif
115
116#endif /* __FIRMWARE_ZYNQMP_H__ */