tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Broadcom Starfighter2 private context
3 *
4 * Copyright (C) 2014, Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#ifndef __BCM_SF2_H
13#define __BCM_SF2_H
14
15#include <linux/platform_device.h>
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <linux/spinlock.h>
19#include <linux/mutex.h>
20#include <linux/mii.h>
21#include <linux/ethtool.h>
22#include <linux/types.h>
23#include <linux/bitops.h>
24#include <linux/if_vlan.h>
25
26#include <net/dsa.h>
27
28#include "bcm_sf2_regs.h"
29#include "b53/b53_priv.h"
30
31struct bcm_sf2_hw_params {
32 u16 top_rev;
33 u16 core_rev;
34 u16 gphy_rev;
35 u32 num_gphy;
36 u8 num_acb_queue;
37 u8 num_rgmii;
38 u8 num_ports;
39 u8 fcb_pause_override:1;
40 u8 acb_packets_inflight:1;
41};
42
43#define BCM_SF2_REGS_NAME {\
44 "core", "reg", "intrl2_0", "intrl2_1", "fcb", "acb" \
45}
46
47#define BCM_SF2_REGS_NUM 6
48
49struct bcm_sf2_port_status {
50 unsigned int link;
51};
52
53struct bcm_sf2_cfp_priv {
54 /* Mutex protecting concurrent accesses to the CFP registers */
55 struct mutex lock;
56 DECLARE_BITMAP(used, CFP_NUM_RULES);
57 DECLARE_BITMAP(unique, CFP_NUM_RULES);
58 unsigned int rules_cnt;
59 struct list_head rules_list;
60};
61
62struct bcm_sf2_priv {
63 /* Base registers, keep those in order with BCM_SF2_REGS_NAME */
64 void __iomem *core;
65 void __iomem *reg;
66 void __iomem *intrl2_0;
67 void __iomem *intrl2_1;
68 void __iomem *fcb;
69 void __iomem *acb;
70
71 /* Register offsets indirection tables */
72 u32 type;
73 const u16 *reg_offsets;
74 unsigned int core_reg_align;
75 unsigned int num_cfp_rules;
76
77 /* spinlock protecting access to the indirect registers */
78 spinlock_t indir_lock;
79
80 int irq0;
81 int irq1;
82 u32 irq0_stat;
83 u32 irq0_mask;
84 u32 irq1_stat;
85 u32 irq1_mask;
86
87 /* Backing b53_device */
88 struct b53_device *dev;
89
90 /* Mutex protecting access to the MIB counters */
91 struct mutex stats_mutex;
92
93 struct bcm_sf2_hw_params hw_params;
94
95 struct bcm_sf2_port_status port_sts[DSA_MAX_PORTS];
96
97 /* Mask of ports enabled for Wake-on-LAN */
98 u32 wol_ports_mask;
99
100 /* MoCA port location */
101 int moca_port;
102
103 /* Bitmask of ports having an integrated PHY */
104 unsigned int int_phy_mask;
105
106 /* Master and slave MDIO bus controller */
107 unsigned int indir_phy_mask;
108 struct device_node *master_mii_dn;
109 struct mii_bus *slave_mii_bus;
110 struct mii_bus *master_mii_bus;
111
112 /* Bitmask of ports needing BRCM tags */
113 unsigned int brcm_tag_mask;
114
115 /* CFP rules context */
116 struct bcm_sf2_cfp_priv cfp;
117};
118
119static inline struct bcm_sf2_priv *bcm_sf2_to_priv(struct dsa_switch *ds)
120{
121 struct b53_device *dev = ds->priv;
122
123 return dev->priv;
124}
125
126static inline u32 bcm_sf2_mangle_addr(struct bcm_sf2_priv *priv, u32 off)
127{
128 return off << priv->core_reg_align;
129}
130
131#define SF2_IO_MACRO(name) \
132static inline u32 name##_readl(struct bcm_sf2_priv *priv, u32 off) \
133{ \
134 return readl_relaxed(priv->name + off); \
135} \
136static inline void name##_writel(struct bcm_sf2_priv *priv, \
137 u32 val, u32 off) \
138{ \
139 writel_relaxed(val, priv->name + off); \
140} \
141
142/* Accesses to 64-bits register requires us to latch the hi/lo pairs
143 * using the REG_DIR_DATA_{READ,WRITE} ancillary registers. The 'indir_lock'
144 * spinlock is automatically grabbed and released to provide relative
145 * atomiticy with latched reads/writes.
146 */
147#define SF2_IO64_MACRO(name) \
148static inline u64 name##_readq(struct bcm_sf2_priv *priv, u32 off) \
149{ \
150 u32 indir, dir; \
151 spin_lock(&priv->indir_lock); \
152 dir = name##_readl(priv, off); \
153 indir = reg_readl(priv, REG_DIR_DATA_READ); \
154 spin_unlock(&priv->indir_lock); \
155 return (u64)indir << 32 | dir; \
156} \
157static inline void name##_writeq(struct bcm_sf2_priv *priv, u64 val, \
158 u32 off) \
159{ \
160 spin_lock(&priv->indir_lock); \
161 reg_writel(priv, upper_32_bits(val), REG_DIR_DATA_WRITE); \
162 name##_writel(priv, lower_32_bits(val), off); \
163 spin_unlock(&priv->indir_lock); \
164}
165
166#define SWITCH_INTR_L2(which) \
167static inline void intrl2_##which##_mask_clear(struct bcm_sf2_priv *priv, \
168 u32 mask) \
169{ \
170 priv->irq##which##_mask &= ~(mask); \
171 intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \
172} \
173static inline void intrl2_##which##_mask_set(struct bcm_sf2_priv *priv, \
174 u32 mask) \
175{ \
176 intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \
177 priv->irq##which##_mask |= (mask); \
178} \
179
180static inline u32 core_readl(struct bcm_sf2_priv *priv, u32 off)
181{
182 u32 tmp = bcm_sf2_mangle_addr(priv, off);
183 return readl_relaxed(priv->core + tmp);
184}
185
186static inline void core_writel(struct bcm_sf2_priv *priv, u32 val, u32 off)
187{
188 u32 tmp = bcm_sf2_mangle_addr(priv, off);
189 writel_relaxed(val, priv->core + tmp);
190}
191
192static inline u32 reg_readl(struct bcm_sf2_priv *priv, u16 off)
193{
194 return readl_relaxed(priv->reg + priv->reg_offsets[off]);
195}
196
197static inline void reg_writel(struct bcm_sf2_priv *priv, u32 val, u16 off)
198{
199 writel_relaxed(val, priv->reg + priv->reg_offsets[off]);
200}
201
202SF2_IO64_MACRO(core);
203SF2_IO_MACRO(intrl2_0);
204SF2_IO_MACRO(intrl2_1);
205SF2_IO_MACRO(fcb);
206SF2_IO_MACRO(acb);
207
208SWITCH_INTR_L2(0);
209SWITCH_INTR_L2(1);
210
211/* RXNFC */
212int bcm_sf2_get_rxnfc(struct dsa_switch *ds, int port,
213 struct ethtool_rxnfc *nfc, u32 *rule_locs);
214int bcm_sf2_set_rxnfc(struct dsa_switch *ds, int port,
215 struct ethtool_rxnfc *nfc);
216int bcm_sf2_cfp_rst(struct bcm_sf2_priv *priv);
217void bcm_sf2_cfp_exit(struct dsa_switch *ds);
218int bcm_sf2_cfp_resume(struct dsa_switch *ds);
219
220#endif /* __BCM_SF2_H */