tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __TILCDC_REGS_H__
19#define __TILCDC_REGS_H__
20
21/* LCDC register definitions, based on da8xx-fb */
22
23#include <linux/bitops.h>
24
25#include "tilcdc_drv.h"
26
27/* LCDC Status Register */
28#define LCDC_END_OF_FRAME1 BIT(9)
29#define LCDC_END_OF_FRAME0 BIT(8)
30#define LCDC_PL_LOAD_DONE BIT(6)
31#define LCDC_FIFO_UNDERFLOW BIT(5)
32#define LCDC_SYNC_LOST BIT(2)
33#define LCDC_FRAME_DONE BIT(0)
34
35/* LCDC DMA Control Register */
36#define LCDC_DMA_BURST_SIZE(x) ((x) << 4)
37#define LCDC_DMA_BURST_SIZE_MASK ((0x7) << 4)
38#define LCDC_DMA_BURST_1 0x0
39#define LCDC_DMA_BURST_2 0x1
40#define LCDC_DMA_BURST_4 0x2
41#define LCDC_DMA_BURST_8 0x3
42#define LCDC_DMA_BURST_16 0x4
43#define LCDC_DMA_FIFO_THRESHOLD(x) ((x) << 8)
44#define LCDC_DMA_FIFO_THRESHOLD_MASK ((0x3) << 8)
45#define LCDC_V1_END_OF_FRAME_INT_ENA BIT(2)
46#define LCDC_V2_END_OF_FRAME0_INT_ENA BIT(8)
47#define LCDC_V2_END_OF_FRAME1_INT_ENA BIT(9)
48#define LCDC_DUAL_FRAME_BUFFER_ENABLE BIT(0)
49
50/* LCDC Control Register */
51#define LCDC_CLK_DIVISOR(x) ((x) << 8)
52#define LCDC_CLK_DIVISOR_MASK ((0xFF) << 8)
53#define LCDC_RASTER_MODE 0x01
54
55/* LCDC Raster Control Register */
56#define LCDC_PALETTE_LOAD_MODE(x) ((x) << 20)
57#define LCDC_PALETTE_LOAD_MODE_MASK ((0x3) << 20)
58#define PALETTE_AND_DATA 0x00
59#define PALETTE_ONLY 0x01
60#define DATA_ONLY 0x02
61
62#define LCDC_MONO_8BIT_MODE BIT(9)
63#define LCDC_RASTER_ORDER BIT(8)
64#define LCDC_TFT_MODE BIT(7)
65#define LCDC_V1_UNDERFLOW_INT_ENA BIT(6)
66#define LCDC_V2_UNDERFLOW_INT_ENA BIT(5)
67#define LCDC_V1_PL_INT_ENA BIT(4)
68#define LCDC_V2_PL_INT_ENA BIT(6)
69#define LCDC_V1_SYNC_LOST_INT_ENA BIT(5)
70#define LCDC_V1_FRAME_DONE_INT_ENA BIT(3)
71#define LCDC_MONOCHROME_MODE BIT(1)
72#define LCDC_RASTER_ENABLE BIT(0)
73#define LCDC_TFT_ALT_ENABLE BIT(23)
74#define LCDC_STN_565_ENABLE BIT(24)
75#define LCDC_V2_DMA_CLK_EN BIT(2)
76#define LCDC_V2_LIDD_CLK_EN BIT(1)
77#define LCDC_V2_CORE_CLK_EN BIT(0)
78#define LCDC_V2_LPP_B10 26
79#define LCDC_V2_TFT_24BPP_MODE BIT(25)
80#define LCDC_V2_TFT_24BPP_UNPACK BIT(26)
81
82/* LCDC Raster Timing 2 Register */
83#define LCDC_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
84#define LCDC_AC_BIAS_TRANSITIONS_PER_INT_MASK ((0xF) << 16)
85#define LCDC_AC_BIAS_FREQUENCY(x) ((x) << 8)
86#define LCDC_AC_BIAS_FREQUENCY_MASK ((0xFF) << 8)
87#define LCDC_SYNC_CTRL BIT(25)
88#define LCDC_SYNC_EDGE BIT(24)
89#define LCDC_INVERT_PIXEL_CLOCK BIT(22)
90#define LCDC_INVERT_HSYNC BIT(21)
91#define LCDC_INVERT_VSYNC BIT(20)
92#define LCDC_LPP_B10 BIT(26)
93
94/* LCDC Block */
95#define LCDC_PID_REG 0x0
96#define LCDC_CTRL_REG 0x4
97#define LCDC_STAT_REG 0x8
98#define LCDC_RASTER_CTRL_REG 0x28
99#define LCDC_RASTER_TIMING_0_REG 0x2c
100#define LCDC_RASTER_TIMING_1_REG 0x30
101#define LCDC_RASTER_TIMING_2_REG 0x34
102#define LCDC_DMA_CTRL_REG 0x40
103#define LCDC_DMA_FB_BASE_ADDR_0_REG 0x44
104#define LCDC_DMA_FB_CEILING_ADDR_0_REG 0x48
105#define LCDC_DMA_FB_BASE_ADDR_1_REG 0x4c
106#define LCDC_DMA_FB_CEILING_ADDR_1_REG 0x50
107
108/* Interrupt Registers available only in Version 2 */
109#define LCDC_RAW_STAT_REG 0x58
110#define LCDC_MASKED_STAT_REG 0x5c
111#define LCDC_INT_ENABLE_SET_REG 0x60
112#define LCDC_INT_ENABLE_CLR_REG 0x64
113#define LCDC_END_OF_INT_IND_REG 0x68
114
115/* Clock registers available only on Version 2 */
116#define LCDC_CLK_ENABLE_REG 0x6c
117#define LCDC_CLK_RESET_REG 0x70
118#define LCDC_CLK_MAIN_RESET BIT(3)
119
120
121/*
122 * Helpers:
123 */
124
125static inline void tilcdc_write(struct drm_device *dev, u32 reg, u32 data)
126{
127 struct tilcdc_drm_private *priv = dev->dev_private;
128 iowrite32(data, priv->mmio + reg);
129}
130
131static inline void tilcdc_write64(struct drm_device *dev, u32 reg, u64 data)
132{
133 struct tilcdc_drm_private *priv = dev->dev_private;
134 volatile void __iomem *addr = priv->mmio + reg;
135
136#if defined(iowrite64) && !defined(iowrite64_is_nonatomic)
137 iowrite64(data, addr);
138#else
139 __iowmb();
140 /* This compiles to strd (=64-bit write) on ARM7 */
141 *(volatile u64 __force *)addr = __cpu_to_le64(data);
142#endif
143}
144
145static inline u32 tilcdc_read(struct drm_device *dev, u32 reg)
146{
147 struct tilcdc_drm_private *priv = dev->dev_private;
148 return ioread32(priv->mmio + reg);
149}
150
151static inline void tilcdc_write_mask(struct drm_device *dev, u32 reg,
152 u32 val, u32 mask)
153{
154 tilcdc_write(dev, reg, (tilcdc_read(dev, reg) & ~mask) | (val & mask));
155}
156
157static inline void tilcdc_set(struct drm_device *dev, u32 reg, u32 mask)
158{
159 tilcdc_write(dev, reg, tilcdc_read(dev, reg) | mask);
160}
161
162static inline void tilcdc_clear(struct drm_device *dev, u32 reg, u32 mask)
163{
164 tilcdc_write(dev, reg, tilcdc_read(dev, reg) & ~mask);
165}
166
167/* the register to read/clear irqstatus differs between v1 and v2 of the IP */
168static inline u32 tilcdc_irqstatus_reg(struct drm_device *dev)
169{
170 struct tilcdc_drm_private *priv = dev->dev_private;
171 return (priv->rev == 2) ? LCDC_MASKED_STAT_REG : LCDC_STAT_REG;
172}
173
174static inline u32 tilcdc_read_irqstatus(struct drm_device *dev)
175{
176 return tilcdc_read(dev, tilcdc_irqstatus_reg(dev));
177}
178
179static inline void tilcdc_clear_irqstatus(struct drm_device *dev, u32 mask)
180{
181 tilcdc_write(dev, tilcdc_irqstatus_reg(dev), mask);
182}
183
184#endif /* __TILCDC_REGS_H__ */