tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom
kernel / arch / powerpc / include / asm / ppc-opcode.h
at v5.0-rc4 587 lines 20 kB view raw
1/* 2 * Copyright 2009 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 * 9 * provides masks and opcode images for use by code generation, emulation 10 * and for instructions that older assemblers might not know about 11 */ 12#ifndef _ASM_POWERPC_PPC_OPCODE_H 13#define _ASM_POWERPC_PPC_OPCODE_H 14 15#include <asm/asm-const.h> 16 17#define __REG_R0 0 18#define __REG_R1 1 19#define __REG_R2 2 20#define __REG_R3 3 21#define __REG_R4 4 22#define __REG_R5 5 23#define __REG_R6 6 24#define __REG_R7 7 25#define __REG_R8 8 26#define __REG_R9 9 27#define __REG_R10 10 28#define __REG_R11 11 29#define __REG_R12 12 30#define __REG_R13 13 31#define __REG_R14 14 32#define __REG_R15 15 33#define __REG_R16 16 34#define __REG_R17 17 35#define __REG_R18 18 36#define __REG_R19 19 37#define __REG_R20 20 38#define __REG_R21 21 39#define __REG_R22 22 40#define __REG_R23 23 41#define __REG_R24 24 42#define __REG_R25 25 43#define __REG_R26 26 44#define __REG_R27 27 45#define __REG_R28 28 46#define __REG_R29 29 47#define __REG_R30 30 48#define __REG_R31 31 49 50#define __REGA0_0 0 51#define __REGA0_R1 1 52#define __REGA0_R2 2 53#define __REGA0_R3 3 54#define __REGA0_R4 4 55#define __REGA0_R5 5 56#define __REGA0_R6 6 57#define __REGA0_R7 7 58#define __REGA0_R8 8 59#define __REGA0_R9 9 60#define __REGA0_R10 10 61#define __REGA0_R11 11 62#define __REGA0_R12 12 63#define __REGA0_R13 13 64#define __REGA0_R14 14 65#define __REGA0_R15 15 66#define __REGA0_R16 16 67#define __REGA0_R17 17 68#define __REGA0_R18 18 69#define __REGA0_R19 19 70#define __REGA0_R20 20 71#define __REGA0_R21 21 72#define __REGA0_R22 22 73#define __REGA0_R23 23 74#define __REGA0_R24 24 75#define __REGA0_R25 25 76#define __REGA0_R26 26 77#define __REGA0_R27 27 78#define __REGA0_R28 28 79#define __REGA0_R29 29 80#define __REGA0_R30 30 81#define __REGA0_R31 31 82 83/* opcode and xopcode for instructions */ 84#define OP_TRAP 3 85#define OP_TRAP_64 2 86 87#define OP_31_XOP_TRAP 4 88#define OP_31_XOP_LDX 21 89#define OP_31_XOP_LWZX 23 90#define OP_31_XOP_LDUX 53 91#define OP_31_XOP_DCBST 54 92#define OP_31_XOP_LWZUX 55 93#define OP_31_XOP_TRAP_64 68 94#define OP_31_XOP_DCBF 86 95#define OP_31_XOP_LBZX 87 96#define OP_31_XOP_STDX 149 97#define OP_31_XOP_STWX 151 98#define OP_31_XOP_STDUX 181 99#define OP_31_XOP_STWUX 183 100#define OP_31_XOP_STBX 215 101#define OP_31_XOP_LBZUX 119 102#define OP_31_XOP_STBUX 247 103#define OP_31_XOP_LHZX 279 104#define OP_31_XOP_LHZUX 311 105#define OP_31_XOP_MSGSNDP 142 106#define OP_31_XOP_MSGCLRP 174 107#define OP_31_XOP_TLBIE 306 108#define OP_31_XOP_MFSPR 339 109#define OP_31_XOP_LWAX 341 110#define OP_31_XOP_LHAX 343 111#define OP_31_XOP_LWAUX 373 112#define OP_31_XOP_LHAUX 375 113#define OP_31_XOP_STHX 407 114#define OP_31_XOP_STHUX 439 115#define OP_31_XOP_MTSPR 467 116#define OP_31_XOP_DCBI 470 117#define OP_31_XOP_LDBRX 532 118#define OP_31_XOP_LWBRX 534 119#define OP_31_XOP_TLBSYNC 566 120#define OP_31_XOP_STDBRX 660 121#define OP_31_XOP_STWBRX 662 122#define OP_31_XOP_STFSX 663 123#define OP_31_XOP_STFSUX 695 124#define OP_31_XOP_STFDX 727 125#define OP_31_XOP_STFDUX 759 126#define OP_31_XOP_LHBRX 790 127#define OP_31_XOP_LFIWAX 855 128#define OP_31_XOP_LFIWZX 887 129#define OP_31_XOP_STHBRX 918 130#define OP_31_XOP_STFIWX 983 131 132/* VSX Scalar Load Instructions */ 133#define OP_31_XOP_LXSDX 588 134#define OP_31_XOP_LXSSPX 524 135#define OP_31_XOP_LXSIWAX 76 136#define OP_31_XOP_LXSIWZX 12 137 138/* VSX Scalar Store Instructions */ 139#define OP_31_XOP_STXSDX 716 140#define OP_31_XOP_STXSSPX 652 141#define OP_31_XOP_STXSIWX 140 142 143/* VSX Vector Load Instructions */ 144#define OP_31_XOP_LXVD2X 844 145#define OP_31_XOP_LXVW4X 780 146 147/* VSX Vector Load and Splat Instruction */ 148#define OP_31_XOP_LXVDSX 332 149 150/* VSX Vector Store Instructions */ 151#define OP_31_XOP_STXVD2X 972 152#define OP_31_XOP_STXVW4X 908 153 154#define OP_31_XOP_LFSX 535 155#define OP_31_XOP_LFSUX 567 156#define OP_31_XOP_LFDX 599 157#define OP_31_XOP_LFDUX 631 158 159/* VMX Vector Load Instructions */ 160#define OP_31_XOP_LVX 103 161 162/* VMX Vector Store Instructions */ 163#define OP_31_XOP_STVX 231 164 165#define OP_31 31 166#define OP_LWZ 32 167#define OP_STFS 52 168#define OP_STFSU 53 169#define OP_STFD 54 170#define OP_STFDU 55 171#define OP_LD 58 172#define OP_LWZU 33 173#define OP_LBZ 34 174#define OP_LBZU 35 175#define OP_STW 36 176#define OP_STWU 37 177#define OP_STD 62 178#define OP_STB 38 179#define OP_STBU 39 180#define OP_LHZ 40 181#define OP_LHZU 41 182#define OP_LHA 42 183#define OP_LHAU 43 184#define OP_STH 44 185#define OP_STHU 45 186#define OP_LMW 46 187#define OP_STMW 47 188#define OP_LFS 48 189#define OP_LFSU 49 190#define OP_LFD 50 191#define OP_LFDU 51 192#define OP_STFS 52 193#define OP_STFSU 53 194#define OP_STFD 54 195#define OP_STFDU 55 196#define OP_LQ 56 197 198/* sorted alphabetically */ 199#define PPC_INST_BHRBE 0x7c00025c 200#define PPC_INST_CLRBHRB 0x7c00035c 201#define PPC_INST_COPY 0x7c20060c 202#define PPC_INST_CP_ABORT 0x7c00068c 203#define PPC_INST_DARN 0x7c0005e6 204#define PPC_INST_DCBA 0x7c0005ec 205#define PPC_INST_DCBA_MASK 0xfc0007fe 206#define PPC_INST_DCBAL 0x7c2005ec 207#define PPC_INST_DCBZL 0x7c2007ec 208#define PPC_INST_ICBT 0x7c00002c 209#define PPC_INST_ICSWX 0x7c00032d 210#define PPC_INST_ICSWEPX 0x7c00076d 211#define PPC_INST_ISEL 0x7c00001e 212#define PPC_INST_ISEL_MASK 0xfc00003e 213#define PPC_INST_LDARX 0x7c0000a8 214#define PPC_INST_STDCX 0x7c0001ad 215#define PPC_INST_LQARX 0x7c000228 216#define PPC_INST_STQCX 0x7c00016d 217#define PPC_INST_LSWI 0x7c0004aa 218#define PPC_INST_LSWX 0x7c00042a 219#define PPC_INST_LWARX 0x7c000028 220#define PPC_INST_STWCX 0x7c00012d 221#define PPC_INST_LWSYNC 0x7c2004ac 222#define PPC_INST_SYNC 0x7c0004ac 223#define PPC_INST_SYNC_MASK 0xfc0007fe 224#define PPC_INST_ISYNC 0x4c00012c 225#define PPC_INST_LXVD2X 0x7c000698 226#define PPC_INST_MCRXR 0x7c000400 227#define PPC_INST_MCRXR_MASK 0xfc0007fe 228#define PPC_INST_MFSPR_PVR 0x7c1f42a6 229#define PPC_INST_MFSPR_PVR_MASK 0xfc1ffffe 230#define PPC_INST_MFTMR 0x7c0002dc 231#define PPC_INST_MSGSND 0x7c00019c 232#define PPC_INST_MSGCLR 0x7c0001dc 233#define PPC_INST_MSGSYNC 0x7c0006ec 234#define PPC_INST_MSGSNDP 0x7c00011c 235#define PPC_INST_MSGCLRP 0x7c00015c 236#define PPC_INST_MTMSRD 0x7c000164 237#define PPC_INST_MTTMR 0x7c0003dc 238#define PPC_INST_NOP 0x60000000 239#define PPC_INST_PASTE 0x7c20070d 240#define PPC_INST_POPCNTB 0x7c0000f4 241#define PPC_INST_POPCNTB_MASK 0xfc0007fe 242#define PPC_INST_POPCNTD 0x7c0003f4 243#define PPC_INST_POPCNTW 0x7c0002f4 244#define PPC_INST_RFEBB 0x4c000124 245#define PPC_INST_RFCI 0x4c000066 246#define PPC_INST_RFDI 0x4c00004e 247#define PPC_INST_RFID 0x4c000024 248#define PPC_INST_RFMCI 0x4c00004c 249#define PPC_INST_MFSPR 0x7c0002a6 250#define PPC_INST_MFSPR_DSCR 0x7c1102a6 251#define PPC_INST_MFSPR_DSCR_MASK 0xfc1ffffe 252#define PPC_INST_MTSPR_DSCR 0x7c1103a6 253#define PPC_INST_MTSPR_DSCR_MASK 0xfc1ffffe 254#define PPC_INST_MFSPR_DSCR_USER 0x7c0302a6 255#define PPC_INST_MFSPR_DSCR_USER_MASK 0xfc1ffffe 256#define PPC_INST_MTSPR_DSCR_USER 0x7c0303a6 257#define PPC_INST_MTSPR_DSCR_USER_MASK 0xfc1ffffe 258#define PPC_INST_MFVSRD 0x7c000066 259#define PPC_INST_MTVSRD 0x7c000166 260#define PPC_INST_SC 0x44000002 261#define PPC_INST_SLBFEE 0x7c0007a7 262#define PPC_INST_SLBIA 0x7c0003e4 263 264#define PPC_INST_STRING 0x7c00042a 265#define PPC_INST_STRING_MASK 0xfc0007fe 266#define PPC_INST_STRING_GEN_MASK 0xfc00067e 267 268#define PPC_INST_STSWI 0x7c0005aa 269#define PPC_INST_STSWX 0x7c00052a 270#define PPC_INST_STXVD2X 0x7c000798 271#define PPC_INST_TLBIE 0x7c000264 272#define PPC_INST_TLBIEL 0x7c000224 273#define PPC_INST_TLBILX 0x7c000024 274#define PPC_INST_WAIT 0x7c00007c 275#define PPC_INST_TLBIVAX 0x7c000624 276#define PPC_INST_TLBSRX_DOT 0x7c0006a5 277#define PPC_INST_VPMSUMW 0x10000488 278#define PPC_INST_VPMSUMD 0x100004c8 279#define PPC_INST_VPERMXOR 0x1000002d 280#define PPC_INST_XXLOR 0xf0000490 281#define PPC_INST_XXSWAPD 0xf0000250 282#define PPC_INST_XVCPSGNDP 0xf0000780 283#define PPC_INST_TRECHKPT 0x7c0007dd 284#define PPC_INST_TRECLAIM 0x7c00075d 285#define PPC_INST_TABORT 0x7c00071d 286#define PPC_INST_TSR 0x7c0005dd 287 288#define PPC_INST_NAP 0x4c000364 289#define PPC_INST_SLEEP 0x4c0003a4 290#define PPC_INST_WINKLE 0x4c0003e4 291 292#define PPC_INST_STOP 0x4c0002e4 293 294/* A2 specific instructions */ 295#define PPC_INST_ERATWE 0x7c0001a6 296#define PPC_INST_ERATRE 0x7c000166 297#define PPC_INST_ERATILX 0x7c000066 298#define PPC_INST_ERATIVAX 0x7c000666 299#define PPC_INST_ERATSX 0x7c000126 300#define PPC_INST_ERATSX_DOT 0x7c000127 301 302/* Misc instructions for BPF compiler */ 303#define PPC_INST_LBZ 0x88000000 304#define PPC_INST_LD 0xe8000000 305#define PPC_INST_LHZ 0xa0000000 306#define PPC_INST_LWZ 0x80000000 307#define PPC_INST_LHBRX 0x7c00062c 308#define PPC_INST_LDBRX 0x7c000428 309#define PPC_INST_STB 0x98000000 310#define PPC_INST_STH 0xb0000000 311#define PPC_INST_STD 0xf8000000 312#define PPC_INST_STDU 0xf8000001 313#define PPC_INST_STW 0x90000000 314#define PPC_INST_STWU 0x94000000 315#define PPC_INST_MFLR 0x7c0802a6 316#define PPC_INST_MTLR 0x7c0803a6 317#define PPC_INST_MTCTR 0x7c0903a6 318#define PPC_INST_CMPWI 0x2c000000 319#define PPC_INST_CMPDI 0x2c200000 320#define PPC_INST_CMPW 0x7c000000 321#define PPC_INST_CMPD 0x7c200000 322#define PPC_INST_CMPLW 0x7c000040 323#define PPC_INST_CMPLD 0x7c200040 324#define PPC_INST_CMPLWI 0x28000000 325#define PPC_INST_CMPLDI 0x28200000 326#define PPC_INST_ADDI 0x38000000 327#define PPC_INST_ADDIS 0x3c000000 328#define PPC_INST_ADD 0x7c000214 329#define PPC_INST_SUB 0x7c000050 330#define PPC_INST_BLR 0x4e800020 331#define PPC_INST_BLRL 0x4e800021 332#define PPC_INST_BCTR 0x4e800420 333#define PPC_INST_MULLD 0x7c0001d2 334#define PPC_INST_MULLW 0x7c0001d6 335#define PPC_INST_MULHWU 0x7c000016 336#define PPC_INST_MULLI 0x1c000000 337#define PPC_INST_DIVWU 0x7c000396 338#define PPC_INST_DIVD 0x7c0003d2 339#define PPC_INST_RLWINM 0x54000000 340#define PPC_INST_RLWIMI 0x50000000 341#define PPC_INST_RLDICL 0x78000000 342#define PPC_INST_RLDICR 0x78000004 343#define PPC_INST_SLW 0x7c000030 344#define PPC_INST_SLD 0x7c000036 345#define PPC_INST_SRW 0x7c000430 346#define PPC_INST_SRAW 0x7c000630 347#define PPC_INST_SRAWI 0x7c000670 348#define PPC_INST_SRD 0x7c000436 349#define PPC_INST_SRAD 0x7c000634 350#define PPC_INST_SRADI 0x7c000674 351#define PPC_INST_AND 0x7c000038 352#define PPC_INST_ANDDOT 0x7c000039 353#define PPC_INST_OR 0x7c000378 354#define PPC_INST_XOR 0x7c000278 355#define PPC_INST_ANDI 0x70000000 356#define PPC_INST_ORI 0x60000000 357#define PPC_INST_ORIS 0x64000000 358#define PPC_INST_XORI 0x68000000 359#define PPC_INST_XORIS 0x6c000000 360#define PPC_INST_NEG 0x7c0000d0 361#define PPC_INST_EXTSW 0x7c0007b4 362#define PPC_INST_BRANCH 0x48000000 363#define PPC_INST_BRANCH_COND 0x40800000 364#define PPC_INST_LBZCIX 0x7c0006aa 365#define PPC_INST_STBCIX 0x7c0007aa 366#define PPC_INST_LWZX 0x7c00002e 367#define PPC_INST_LFSX 0x7c00042e 368#define PPC_INST_STFSX 0x7c00052e 369#define PPC_INST_LFDX 0x7c0004ae 370#define PPC_INST_STFDX 0x7c0005ae 371#define PPC_INST_LVX 0x7c0000ce 372#define PPC_INST_STVX 0x7c0001ce 373#define PPC_INST_VCMPEQUD 0x100000c7 374#define PPC_INST_VCMPEQUB 0x10000006 375 376/* macros to insert fields into opcodes */ 377#define ___PPC_RA(a) (((a) & 0x1f) << 16) 378#define ___PPC_RB(b) (((b) & 0x1f) << 11) 379#define ___PPC_RS(s) (((s) & 0x1f) << 21) 380#define ___PPC_RT(t) ___PPC_RS(t) 381#define ___PPC_R(r) (((r) & 0x1) << 16) 382#define ___PPC_PRS(prs) (((prs) & 0x1) << 17) 383#define ___PPC_RIC(ric) (((ric) & 0x3) << 18) 384#define __PPC_RA(a) ___PPC_RA(__REG_##a) 385#define __PPC_RA0(a) ___PPC_RA(__REGA0_##a) 386#define __PPC_RB(b) ___PPC_RB(__REG_##b) 387#define __PPC_RS(s) ___PPC_RS(__REG_##s) 388#define __PPC_RT(t) ___PPC_RT(__REG_##t) 389#define __PPC_XA(a) ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3)) 390#define __PPC_XB(b) ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4)) 391#define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5)) 392#define __PPC_XT(s) __PPC_XS(s) 393#define __PPC_T_TLB(t) (((t) & 0x3) << 21) 394#define __PPC_WC(w) (((w) & 0x3) << 21) 395#define __PPC_WS(w) (((w) & 0x1f) << 11) 396#define __PPC_SH(s) __PPC_WS(s) 397#define __PPC_SH64(s) (__PPC_SH(s) | (((s) & 0x20) >> 4)) 398#define __PPC_MB(s) (((s) & 0x1f) << 6) 399#define __PPC_ME(s) (((s) & 0x1f) << 1) 400#define __PPC_MB64(s) (__PPC_MB(s) | ((s) & 0x20)) 401#define __PPC_ME64(s) __PPC_MB64(s) 402#define __PPC_BI(s) (((s) & 0x1f) << 16) 403#define __PPC_CT(t) (((t) & 0x0f) << 21) 404#define __PPC_SPR(r) ((((r) & 0x1f) << 16) | ((((r) >> 5) & 0x1f) << 11)) 405#define __PPC_RC21 (0x1 << 10) 406 407/* 408 * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a 409 * larx with EH set as an illegal instruction. 410 */ 411#ifdef CONFIG_PPC64 412#define __PPC_EH(eh) (((eh) & 0x1) << 0) 413#else 414#define __PPC_EH(eh) 0 415#endif 416 417/* Deal with instructions that older assemblers aren't aware of */ 418#define PPC_CP_ABORT stringify_in_c(.long PPC_INST_CP_ABORT) 419#define PPC_COPY(a, b) stringify_in_c(.long PPC_INST_COPY | \ 420 ___PPC_RA(a) | ___PPC_RB(b)) 421#define PPC_DARN(t, l) stringify_in_c(.long PPC_INST_DARN | \ 422 ___PPC_RT(t) | \ 423 (((l) & 0x3) << 16)) 424#define PPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \ 425 __PPC_RA(a) | __PPC_RB(b)) 426#define PPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \ 427 __PPC_RA(a) | __PPC_RB(b)) 428#define PPC_LQARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LQARX | \ 429 ___PPC_RT(t) | ___PPC_RA(a) | \ 430 ___PPC_RB(b) | __PPC_EH(eh)) 431#define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LDARX | \ 432 ___PPC_RT(t) | ___PPC_RA(a) | \ 433 ___PPC_RB(b) | __PPC_EH(eh)) 434#define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LWARX | \ 435 ___PPC_RT(t) | ___PPC_RA(a) | \ 436 ___PPC_RB(b) | __PPC_EH(eh)) 437#define PPC_STQCX(t, a, b) stringify_in_c(.long PPC_INST_STQCX | \ 438 ___PPC_RT(t) | ___PPC_RA(a) | \ 439 ___PPC_RB(b)) 440#define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \ 441 ___PPC_RB(b)) 442#define PPC_MSGSYNC stringify_in_c(.long PPC_INST_MSGSYNC) 443#define PPC_MSGCLR(b) stringify_in_c(.long PPC_INST_MSGCLR | \ 444 ___PPC_RB(b)) 445#define PPC_MSGSNDP(b) stringify_in_c(.long PPC_INST_MSGSNDP | \ 446 ___PPC_RB(b)) 447#define PPC_MSGCLRP(b) stringify_in_c(.long PPC_INST_MSGCLRP | \ 448 ___PPC_RB(b)) 449#define PPC_PASTE(a, b) stringify_in_c(.long PPC_INST_PASTE | \ 450 ___PPC_RA(a) | ___PPC_RB(b)) 451#define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_INST_POPCNTB | \ 452 __PPC_RA(a) | __PPC_RS(s)) 453#define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_INST_POPCNTD | \ 454 __PPC_RA(a) | __PPC_RS(s)) 455#define PPC_POPCNTW(a, s) stringify_in_c(.long PPC_INST_POPCNTW | \ 456 __PPC_RA(a) | __PPC_RS(s)) 457#define PPC_RFCI stringify_in_c(.long PPC_INST_RFCI) 458#define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI) 459#define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI) 460#define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \ 461 __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b)) 462#define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b) 463#define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b) 464#define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b) 465#define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \ 466 __PPC_WC(w)) 467#define PPC_TLBIE(lp,a) stringify_in_c(.long PPC_INST_TLBIE | \ 468 ___PPC_RB(a) | ___PPC_RS(lp)) 469#define PPC_TLBIE_5(rb,rs,ric,prs,r) \ 470 stringify_in_c(.long PPC_INST_TLBIE | \ 471 ___PPC_RB(rb) | ___PPC_RS(rs) | \ 472 ___PPC_RIC(ric) | ___PPC_PRS(prs) | \ 473 ___PPC_R(r)) 474#define PPC_TLBIEL(rb,rs,ric,prs,r) \ 475 stringify_in_c(.long PPC_INST_TLBIEL | \ 476 ___PPC_RB(rb) | ___PPC_RS(rs) | \ 477 ___PPC_RIC(ric) | ___PPC_PRS(prs) | \ 478 ___PPC_R(r)) 479#define PPC_TLBSRX_DOT(a,b) stringify_in_c(.long PPC_INST_TLBSRX_DOT | \ 480 __PPC_RA0(a) | __PPC_RB(b)) 481#define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX | \ 482 __PPC_RA0(a) | __PPC_RB(b)) 483 484#define PPC_ERATWE(s, a, w) stringify_in_c(.long PPC_INST_ERATWE | \ 485 __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w)) 486#define PPC_ERATRE(s, a, w) stringify_in_c(.long PPC_INST_ERATRE | \ 487 __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w)) 488#define PPC_ERATILX(t, a, b) stringify_in_c(.long PPC_INST_ERATILX | \ 489 __PPC_T_TLB(t) | __PPC_RA0(a) | \ 490 __PPC_RB(b)) 491#define PPC_ERATIVAX(s, a, b) stringify_in_c(.long PPC_INST_ERATIVAX | \ 492 __PPC_RS(s) | __PPC_RA0(a) | __PPC_RB(b)) 493#define PPC_ERATSX(t, a, w) stringify_in_c(.long PPC_INST_ERATSX | \ 494 __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b)) 495#define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_INST_ERATSX_DOT | \ 496 __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b)) 497#define PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_INST_SLBFEE | \ 498 __PPC_RT(t) | __PPC_RB(b)) 499#define __PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_INST_SLBFEE | \ 500 ___PPC_RT(t) | ___PPC_RB(b)) 501#define PPC_ICBT(c,a,b) stringify_in_c(.long PPC_INST_ICBT | \ 502 __PPC_CT(c) | __PPC_RA0(a) | __PPC_RB(b)) 503/* PASemi instructions */ 504#define LBZCIX(t,a,b) stringify_in_c(.long PPC_INST_LBZCIX | \ 505 __PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b)) 506#define STBCIX(s,a,b) stringify_in_c(.long PPC_INST_STBCIX | \ 507 __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b)) 508 509/* 510 * Define what the VSX XX1 form instructions will look like, then add 511 * the 128 bit load store instructions based on that. 512 */ 513#define VSX_XX1(s, a, b) (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b)) 514#define VSX_XX3(t, a, b) (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b)) 515#define STXVD2X(s, a, b) stringify_in_c(.long PPC_INST_STXVD2X | \ 516 VSX_XX1((s), a, b)) 517#define LXVD2X(s, a, b) stringify_in_c(.long PPC_INST_LXVD2X | \ 518 VSX_XX1((s), a, b)) 519#define MFVRD(a, t) stringify_in_c(.long PPC_INST_MFVSRD | \ 520 VSX_XX1((t)+32, a, R0)) 521#define MTVRD(t, a) stringify_in_c(.long PPC_INST_MTVSRD | \ 522 VSX_XX1((t)+32, a, R0)) 523#define VPMSUMW(t, a, b) stringify_in_c(.long PPC_INST_VPMSUMW | \ 524 VSX_XX3((t), a, b)) 525#define VPMSUMD(t, a, b) stringify_in_c(.long PPC_INST_VPMSUMD | \ 526 VSX_XX3((t), a, b)) 527#define XXLOR(t, a, b) stringify_in_c(.long PPC_INST_XXLOR | \ 528 VSX_XX3((t), a, b)) 529#define XXSWAPD(t, a) stringify_in_c(.long PPC_INST_XXSWAPD | \ 530 VSX_XX3((t), a, a)) 531#define XVCPSGNDP(t, a, b) stringify_in_c(.long (PPC_INST_XVCPSGNDP | \ 532 VSX_XX3((t), (a), (b)))) 533 534#define VPERMXOR(vrt, vra, vrb, vrc) \ 535 stringify_in_c(.long (PPC_INST_VPERMXOR | \ 536 ___PPC_RT(vrt) | ___PPC_RA(vra) | \ 537 ___PPC_RB(vrb) | (((vrc) & 0x1f) << 6))) 538 539#define PPC_NAP stringify_in_c(.long PPC_INST_NAP) 540#define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP) 541#define PPC_WINKLE stringify_in_c(.long PPC_INST_WINKLE) 542 543#define PPC_STOP stringify_in_c(.long PPC_INST_STOP) 544 545/* BHRB instructions */ 546#define PPC_CLRBHRB stringify_in_c(.long PPC_INST_CLRBHRB) 547#define PPC_MFBHRBE(r, n) stringify_in_c(.long PPC_INST_BHRBE | \ 548 __PPC_RT(r) | \ 549 (((n) & 0x3ff) << 11)) 550 551/* Transactional memory instructions */ 552#define TRECHKPT stringify_in_c(.long PPC_INST_TRECHKPT) 553#define TRECLAIM(r) stringify_in_c(.long PPC_INST_TRECLAIM \ 554 | __PPC_RA(r)) 555#define TABORT(r) stringify_in_c(.long PPC_INST_TABORT \ 556 | __PPC_RA(r)) 557 558/* book3e thread control instructions */ 559#define TMRN(x) ((((x) & 0x1f) << 16) | (((x) & 0x3e0) << 6)) 560#define MTTMR(tmr, r) stringify_in_c(.long PPC_INST_MTTMR | \ 561 TMRN(tmr) | ___PPC_RS(r)) 562#define MFTMR(tmr, r) stringify_in_c(.long PPC_INST_MFTMR | \ 563 TMRN(tmr) | ___PPC_RT(r)) 564 565/* Coprocessor instructions */ 566#define PPC_ICSWX(s, a, b) stringify_in_c(.long PPC_INST_ICSWX | \ 567 ___PPC_RS(s) | \ 568 ___PPC_RA(a) | \ 569 ___PPC_RB(b)) 570#define PPC_ICSWEPX(s, a, b) stringify_in_c(.long PPC_INST_ICSWEPX | \ 571 ___PPC_RS(s) | \ 572 ___PPC_RA(a) | \ 573 ___PPC_RB(b)) 574 575#define PPC_SLBIA(IH) stringify_in_c(.long PPC_INST_SLBIA | \ 576 ((IH & 0x7) << 21)) 577#define PPC_INVALIDATE_ERAT PPC_SLBIA(7) 578 579#define VCMPEQUD_RC(vrt, vra, vrb) stringify_in_c(.long PPC_INST_VCMPEQUD | \ 580 ___PPC_RT(vrt) | ___PPC_RA(vra) | \ 581 ___PPC_RB(vrb) | __PPC_RC21) 582 583#define VCMPEQUB_RC(vrt, vra, vrb) stringify_in_c(.long PPC_INST_VCMPEQUB | \ 584 ___PPC_RT(vrt) | ___PPC_RA(vra) | \ 585 ___PPC_RB(vrb) | __PPC_RC21) 586 587#endif /* _ASM_POWERPC_PPC_OPCODE_H */