tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Jie Qiu <jie.qiu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/io.h>
17#include <linux/interrupt.h>
18#include <linux/mod_devicetable.h>
19#include <linux/platform_device.h>
20
21#include "mtk_cec.h"
22
23#define TR_CONFIG 0x00
24#define CLEAR_CEC_IRQ BIT(15)
25
26#define CEC_CKGEN 0x04
27#define CEC_32K_PDN BIT(19)
28#define PDN BIT(16)
29
30#define RX_EVENT 0x54
31#define HDMI_PORD BIT(25)
32#define HDMI_HTPLG BIT(24)
33#define HDMI_PORD_INT_EN BIT(9)
34#define HDMI_HTPLG_INT_EN BIT(8)
35
36#define RX_GEN_WD 0x58
37#define HDMI_PORD_INT_32K_STATUS BIT(26)
38#define RX_RISC_INT_32K_STATUS BIT(25)
39#define HDMI_HTPLG_INT_32K_STATUS BIT(24)
40#define HDMI_PORD_INT_32K_CLR BIT(18)
41#define RX_INT_32K_CLR BIT(17)
42#define HDMI_HTPLG_INT_32K_CLR BIT(16)
43#define HDMI_PORD_INT_32K_STA_MASK BIT(10)
44#define RX_RISC_INT_32K_STA_MASK BIT(9)
45#define HDMI_HTPLG_INT_32K_STA_MASK BIT(8)
46#define HDMI_PORD_INT_32K_EN BIT(2)
47#define RX_INT_32K_EN BIT(1)
48#define HDMI_HTPLG_INT_32K_EN BIT(0)
49
50#define NORMAL_INT_CTRL 0x5C
51#define HDMI_HTPLG_INT_STA BIT(0)
52#define HDMI_PORD_INT_STA BIT(1)
53#define HDMI_HTPLG_INT_CLR BIT(16)
54#define HDMI_PORD_INT_CLR BIT(17)
55#define HDMI_FULL_INT_CLR BIT(20)
56
57struct mtk_cec {
58 void __iomem *regs;
59 struct clk *clk;
60 int irq;
61 bool hpd;
62 void (*hpd_event)(bool hpd, struct device *dev);
63 struct device *hdmi_dev;
64 spinlock_t lock;
65};
66
67static void mtk_cec_clear_bits(struct mtk_cec *cec, unsigned int offset,
68 unsigned int bits)
69{
70 void __iomem *reg = cec->regs + offset;
71 u32 tmp;
72
73 tmp = readl(reg);
74 tmp &= ~bits;
75 writel(tmp, reg);
76}
77
78static void mtk_cec_set_bits(struct mtk_cec *cec, unsigned int offset,
79 unsigned int bits)
80{
81 void __iomem *reg = cec->regs + offset;
82 u32 tmp;
83
84 tmp = readl(reg);
85 tmp |= bits;
86 writel(tmp, reg);
87}
88
89static void mtk_cec_mask(struct mtk_cec *cec, unsigned int offset,
90 unsigned int val, unsigned int mask)
91{
92 u32 tmp = readl(cec->regs + offset) & ~mask;
93
94 tmp |= val & mask;
95 writel(val, cec->regs + offset);
96}
97
98void mtk_cec_set_hpd_event(struct device *dev,
99 void (*hpd_event)(bool hpd, struct device *dev),
100 struct device *hdmi_dev)
101{
102 struct mtk_cec *cec = dev_get_drvdata(dev);
103 unsigned long flags;
104
105 spin_lock_irqsave(&cec->lock, flags);
106 cec->hdmi_dev = hdmi_dev;
107 cec->hpd_event = hpd_event;
108 spin_unlock_irqrestore(&cec->lock, flags);
109}
110
111bool mtk_cec_hpd_high(struct device *dev)
112{
113 struct mtk_cec *cec = dev_get_drvdata(dev);
114 unsigned int status;
115
116 status = readl(cec->regs + RX_EVENT);
117
118 return (status & (HDMI_PORD | HDMI_HTPLG)) == (HDMI_PORD | HDMI_HTPLG);
119}
120
121static void mtk_cec_htplg_irq_init(struct mtk_cec *cec)
122{
123 mtk_cec_mask(cec, CEC_CKGEN, 0 | CEC_32K_PDN, PDN | CEC_32K_PDN);
124 mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
125 RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
126 mtk_cec_mask(cec, RX_GEN_WD, 0, HDMI_PORD_INT_32K_CLR | RX_INT_32K_CLR |
127 HDMI_HTPLG_INT_32K_CLR | HDMI_PORD_INT_32K_EN |
128 RX_INT_32K_EN | HDMI_HTPLG_INT_32K_EN);
129}
130
131static void mtk_cec_htplg_irq_enable(struct mtk_cec *cec)
132{
133 mtk_cec_set_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN);
134}
135
136static void mtk_cec_htplg_irq_disable(struct mtk_cec *cec)
137{
138 mtk_cec_clear_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN);
139}
140
141static void mtk_cec_clear_htplg_irq(struct mtk_cec *cec)
142{
143 mtk_cec_set_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ);
144 mtk_cec_set_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR |
145 HDMI_PORD_INT_CLR | HDMI_FULL_INT_CLR);
146 mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
147 RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
148 usleep_range(5, 10);
149 mtk_cec_clear_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR |
150 HDMI_PORD_INT_CLR | HDMI_FULL_INT_CLR);
151 mtk_cec_clear_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ);
152 mtk_cec_clear_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
153 RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
154}
155
156static void mtk_cec_hpd_event(struct mtk_cec *cec, bool hpd)
157{
158 void (*hpd_event)(bool hpd, struct device *dev);
159 struct device *hdmi_dev;
160 unsigned long flags;
161
162 spin_lock_irqsave(&cec->lock, flags);
163 hpd_event = cec->hpd_event;
164 hdmi_dev = cec->hdmi_dev;
165 spin_unlock_irqrestore(&cec->lock, flags);
166
167 if (hpd_event)
168 hpd_event(hpd, hdmi_dev);
169}
170
171static irqreturn_t mtk_cec_htplg_isr_thread(int irq, void *arg)
172{
173 struct device *dev = arg;
174 struct mtk_cec *cec = dev_get_drvdata(dev);
175 bool hpd;
176
177 mtk_cec_clear_htplg_irq(cec);
178 hpd = mtk_cec_hpd_high(dev);
179
180 if (cec->hpd != hpd) {
181 dev_dbg(dev, "hotplug event! cur hpd = %d, hpd = %d\n",
182 cec->hpd, hpd);
183 cec->hpd = hpd;
184 mtk_cec_hpd_event(cec, hpd);
185 }
186 return IRQ_HANDLED;
187}
188
189static int mtk_cec_probe(struct platform_device *pdev)
190{
191 struct device *dev = &pdev->dev;
192 struct mtk_cec *cec;
193 struct resource *res;
194 int ret;
195
196 cec = devm_kzalloc(dev, sizeof(*cec), GFP_KERNEL);
197 if (!cec)
198 return -ENOMEM;
199
200 platform_set_drvdata(pdev, cec);
201 spin_lock_init(&cec->lock);
202
203 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
204 cec->regs = devm_ioremap_resource(dev, res);
205 if (IS_ERR(cec->regs)) {
206 ret = PTR_ERR(cec->regs);
207 dev_err(dev, "Failed to ioremap cec: %d\n", ret);
208 return ret;
209 }
210
211 cec->clk = devm_clk_get(dev, NULL);
212 if (IS_ERR(cec->clk)) {
213 ret = PTR_ERR(cec->clk);
214 dev_err(dev, "Failed to get cec clock: %d\n", ret);
215 return ret;
216 }
217
218 cec->irq = platform_get_irq(pdev, 0);
219 if (cec->irq < 0) {
220 dev_err(dev, "Failed to get cec irq: %d\n", cec->irq);
221 return cec->irq;
222 }
223
224 ret = devm_request_threaded_irq(dev, cec->irq, NULL,
225 mtk_cec_htplg_isr_thread,
226 IRQF_SHARED | IRQF_TRIGGER_LOW |
227 IRQF_ONESHOT, "hdmi hpd", dev);
228 if (ret) {
229 dev_err(dev, "Failed to register cec irq: %d\n", ret);
230 return ret;
231 }
232
233 ret = clk_prepare_enable(cec->clk);
234 if (ret) {
235 dev_err(dev, "Failed to enable cec clock: %d\n", ret);
236 return ret;
237 }
238
239 mtk_cec_htplg_irq_init(cec);
240 mtk_cec_htplg_irq_enable(cec);
241
242 return 0;
243}
244
245static int mtk_cec_remove(struct platform_device *pdev)
246{
247 struct mtk_cec *cec = platform_get_drvdata(pdev);
248
249 mtk_cec_htplg_irq_disable(cec);
250 clk_disable_unprepare(cec->clk);
251 return 0;
252}
253
254static const struct of_device_id mtk_cec_of_ids[] = {
255 { .compatible = "mediatek,mt8173-cec", },
256 {}
257};
258
259struct platform_driver mtk_cec_driver = {
260 .probe = mtk_cec_probe,
261 .remove = mtk_cec_remove,
262 .driver = {
263 .name = "mediatek-cec",
264 .of_match_table = mtk_cec_of_ids,
265 },
266};