Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
3 *
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
6 * this source tree.
7 */
8
9#ifndef __ETH_COMMON__
10#define __ETH_COMMON__
11
12/********************/
13/* ETH FW CONSTANTS */
14/********************/
15#define ETH_HSI_VER_MAJOR 3
16#define ETH_HSI_VER_MINOR 10
17
18#define ETH_HSI_VER_NO_PKT_LEN_TUNN 5
19
20#define ETH_CACHE_LINE_SIZE 64
21#define ETH_RX_CQE_GAP 32
22#define ETH_MAX_RAMROD_PER_CON 8
23#define ETH_TX_BD_PAGE_SIZE_BYTES 4096
24#define ETH_RX_BD_PAGE_SIZE_BYTES 4096
25#define ETH_RX_CQE_PAGE_SIZE_BYTES 4096
26#define ETH_RX_NUM_NEXT_PAGE_BDS 2
27
28#define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1
29#define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18
30#define ETH_TX_MAX_BDS_PER_LSO_PACKET 255
31#define ETH_TX_MAX_LSO_HDR_NBD 4
32#define ETH_TX_MIN_BDS_PER_LSO_PKT 3
33#define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3
34#define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2
35#define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2
36#define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 4 + 12 + 8))
37#define ETH_TX_MAX_LSO_HDR_BYTES 510
38#define ETH_TX_LSO_WINDOW_BDS_NUM (18 - 1)
39#define ETH_TX_LSO_WINDOW_MIN_LEN 9700
40#define ETH_TX_MAX_LSO_PAYLOAD_LEN 0xFE000
41#define ETH_TX_NUM_SAME_AS_LAST_ENTRIES 320
42#define ETH_TX_INACTIVE_SAME_AS_LAST 0xFFFF
43
44#define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
45#define ETH_NUM_STATISTIC_COUNTERS_DOUBLE_VF_ZONE \
46 (ETH_NUM_STATISTIC_COUNTERS - MAX_NUM_VFS / 2)
47#define ETH_NUM_STATISTIC_COUNTERS_QUAD_VF_ZONE \
48 (ETH_NUM_STATISTIC_COUNTERS - 3 * MAX_NUM_VFS / 4)
49
50/* Maximum number of buffers, used for RX packet placement */
51#define ETH_RX_MAX_BUFF_PER_PKT 5
52
53/* num of MAC/VLAN filters */
54#define ETH_NUM_MAC_FILTERS 512
55#define ETH_NUM_VLAN_FILTERS 512
56
57/* approx. multicast constants */
58#define ETH_MULTICAST_BIN_FROM_MAC_SEED 0
59#define ETH_MULTICAST_MAC_BINS 256
60#define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32)
61
62/* ethernet vport update constants */
63#define ETH_FILTER_RULES_COUNT 10
64#define ETH_RSS_IND_TABLE_ENTRIES_NUM 128
65#define ETH_RSS_KEY_SIZE_REGS 10
66#define ETH_RSS_ENGINE_NUM_K2 207
67#define ETH_RSS_ENGINE_NUM_BB 127
68
69/* TPA constants */
70#define ETH_TPA_MAX_AGGS_NUM 64
71#define ETH_TPA_CQE_START_LEN_LIST_SIZE ETH_RX_MAX_BUFF_PER_PKT
72#define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6
73#define ETH_TPA_CQE_END_LEN_LIST_SIZE 4
74
75/* Control frame check constants */
76#define ETH_CTL_FRAME_ETH_TYPE_NUM 4
77
78struct eth_tx_1st_bd_flags {
79 u8 bitfields;
80#define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1
81#define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT 0
82#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1
83#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 1
84#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1
85#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT 2
86#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1
87#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT 3
88#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1
89#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT 4
90#define ETH_TX_1ST_BD_FLAGS_LSO_MASK 0x1
91#define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT 5
92#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK 0x1
93#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6
94#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1
95#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7
96};
97
98/* The parsing information data fo rthe first tx bd of a given packet. */
99struct eth_tx_data_1st_bd {
100 __le16 vlan;
101 u8 nbds;
102 struct eth_tx_1st_bd_flags bd_flags;
103 __le16 bitfields;
104#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK 0x1
105#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT 0
106#define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1
107#define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1
108#define ETH_TX_DATA_1ST_BD_PKT_LEN_MASK 0x3FFF
109#define ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT 2
110};
111
112/* The parsing information data for the second tx bd of a given packet. */
113struct eth_tx_data_2nd_bd {
114 __le16 tunn_ip_size;
115 __le16 bitfields1;
116#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF
117#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0
118#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK 0x3
119#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT 4
120#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_MASK 0x3
121#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_SHIFT 6
122#define ETH_TX_DATA_2ND_BD_START_BD_MASK 0x1
123#define ETH_TX_DATA_2ND_BD_START_BD_SHIFT 8
124#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK 0x3
125#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT 9
126#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK 0x1
127#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT 11
128#define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK 0x1
129#define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT 12
130#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK 0x1
131#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT 13
132#define ETH_TX_DATA_2ND_BD_L4_UDP_MASK 0x1
133#define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT 14
134#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK 0x1
135#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT 15
136 __le16 bitfields2;
137#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK 0x1FFF
138#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT 0
139#define ETH_TX_DATA_2ND_BD_RESERVED0_MASK 0x7
140#define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13
141};
142
143/* Firmware data for L2-EDPM packet. */
144struct eth_edpm_fw_data {
145 struct eth_tx_data_1st_bd data_1st_bd;
146 struct eth_tx_data_2nd_bd data_2nd_bd;
147 __le32 reserved;
148};
149
150struct eth_fast_path_cqe_fw_debug {
151 __le16 reserved2;
152};
153
154/* tunneling parsing flags */
155struct eth_tunnel_parsing_flags {
156 u8 flags;
157#define ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK 0x3
158#define ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT 0
159#define ETH_TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_MASK 0x1
160#define ETH_TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_SHIFT 2
161#define ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK 0x3
162#define ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT 3
163#define ETH_TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_MASK 0x1
164#define ETH_TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_SHIFT 5
165#define ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_MASK 0x1
166#define ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_SHIFT 6
167#define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_MASK 0x1
168#define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_SHIFT 7
169};
170
171/* PMD flow control bits */
172struct eth_pmd_flow_flags {
173 u8 flags;
174#define ETH_PMD_FLOW_FLAGS_VALID_MASK 0x1
175#define ETH_PMD_FLOW_FLAGS_VALID_SHIFT 0
176#define ETH_PMD_FLOW_FLAGS_TOGGLE_MASK 0x1
177#define ETH_PMD_FLOW_FLAGS_TOGGLE_SHIFT 1
178#define ETH_PMD_FLOW_FLAGS_RESERVED_MASK 0x3F
179#define ETH_PMD_FLOW_FLAGS_RESERVED_SHIFT 2
180};
181
182/* Regular ETH Rx FP CQE. */
183struct eth_fast_path_rx_reg_cqe {
184 u8 type;
185 u8 bitfields;
186#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK 0x7
187#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0
188#define ETH_FAST_PATH_RX_REG_CQE_TC_MASK 0xF
189#define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT 3
190#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK 0x1
191#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT 7
192 __le16 pkt_len;
193 struct parsing_and_err_flags pars_flags;
194 __le16 vlan_tag;
195 __le32 rss_hash;
196 __le16 len_on_first_bd;
197 u8 placement_offset;
198 struct eth_tunnel_parsing_flags tunnel_pars_flags;
199 u8 bd_num;
200 u8 reserved[9];
201 struct eth_fast_path_cqe_fw_debug fw_debug;
202 u8 reserved1[3];
203 struct eth_pmd_flow_flags pmd_flags;
204};
205
206/* TPA-continue ETH Rx FP CQE. */
207struct eth_fast_path_rx_tpa_cont_cqe {
208 u8 type;
209 u8 tpa_agg_index;
210 __le16 len_list[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
211 u8 reserved;
212 u8 reserved1;
213 __le16 reserved2[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
214 u8 reserved3[3];
215 struct eth_pmd_flow_flags pmd_flags;
216};
217
218/* TPA-end ETH Rx FP CQE. */
219struct eth_fast_path_rx_tpa_end_cqe {
220 u8 type;
221 u8 tpa_agg_index;
222 __le16 total_packet_len;
223 u8 num_of_bds;
224 u8 end_reason;
225 __le16 num_of_coalesced_segs;
226 __le32 ts_delta;
227 __le16 len_list[ETH_TPA_CQE_END_LEN_LIST_SIZE];
228 __le16 reserved3[ETH_TPA_CQE_END_LEN_LIST_SIZE];
229 __le16 reserved1;
230 u8 reserved2;
231 struct eth_pmd_flow_flags pmd_flags;
232};
233
234/* TPA-start ETH Rx FP CQE. */
235struct eth_fast_path_rx_tpa_start_cqe {
236 u8 type;
237 u8 bitfields;
238#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK 0x7
239#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0
240#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK 0xF
241#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT 3
242#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK 0x1
243#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT 7
244 __le16 seg_len;
245 struct parsing_and_err_flags pars_flags;
246 __le16 vlan_tag;
247 __le32 rss_hash;
248 __le16 len_on_first_bd;
249 u8 placement_offset;
250 struct eth_tunnel_parsing_flags tunnel_pars_flags;
251 u8 tpa_agg_index;
252 u8 header_len;
253 __le16 ext_bd_len_list[ETH_TPA_CQE_START_LEN_LIST_SIZE];
254 struct eth_fast_path_cqe_fw_debug fw_debug;
255 u8 reserved;
256 struct eth_pmd_flow_flags pmd_flags;
257};
258
259/* The L4 pseudo checksum mode for Ethernet */
260enum eth_l4_pseudo_checksum_mode {
261 ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH,
262 ETH_L4_PSEUDO_CSUM_ZERO_LENGTH,
263 MAX_ETH_L4_PSEUDO_CHECKSUM_MODE
264};
265
266struct eth_rx_bd {
267 struct regpair addr;
268};
269
270/* regular ETH Rx SP CQE */
271struct eth_slow_path_rx_cqe {
272 u8 type;
273 u8 ramrod_cmd_id;
274 u8 error_flag;
275 u8 reserved[25];
276 __le16 echo;
277 u8 reserved1;
278 struct eth_pmd_flow_flags pmd_flags;
279};
280
281/* union for all ETH Rx CQE types */
282union eth_rx_cqe {
283 struct eth_fast_path_rx_reg_cqe fast_path_regular;
284 struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start;
285 struct eth_fast_path_rx_tpa_cont_cqe fast_path_tpa_cont;
286 struct eth_fast_path_rx_tpa_end_cqe fast_path_tpa_end;
287 struct eth_slow_path_rx_cqe slow_path;
288};
289
290/* ETH Rx CQE type */
291enum eth_rx_cqe_type {
292 ETH_RX_CQE_TYPE_UNUSED,
293 ETH_RX_CQE_TYPE_REGULAR,
294 ETH_RX_CQE_TYPE_SLOW_PATH,
295 ETH_RX_CQE_TYPE_TPA_START,
296 ETH_RX_CQE_TYPE_TPA_CONT,
297 ETH_RX_CQE_TYPE_TPA_END,
298 MAX_ETH_RX_CQE_TYPE
299};
300
301struct eth_rx_pmd_cqe {
302 union eth_rx_cqe cqe;
303 u8 reserved[ETH_RX_CQE_GAP];
304};
305
306enum eth_rx_tunn_type {
307 ETH_RX_NO_TUNN,
308 ETH_RX_TUNN_GENEVE,
309 ETH_RX_TUNN_GRE,
310 ETH_RX_TUNN_VXLAN,
311 MAX_ETH_RX_TUNN_TYPE
312};
313
314/* Aggregation end reason. */
315enum eth_tpa_end_reason {
316 ETH_AGG_END_UNUSED,
317 ETH_AGG_END_SP_UPDATE,
318 ETH_AGG_END_MAX_LEN,
319 ETH_AGG_END_LAST_SEG,
320 ETH_AGG_END_TIMEOUT,
321 ETH_AGG_END_NOT_CONSISTENT,
322 ETH_AGG_END_OUT_OF_ORDER,
323 ETH_AGG_END_NON_TPA_SEG,
324 MAX_ETH_TPA_END_REASON
325};
326
327/* The first tx bd of a given packet */
328struct eth_tx_1st_bd {
329 struct regpair addr;
330 __le16 nbytes;
331 struct eth_tx_data_1st_bd data;
332};
333
334/* The second tx bd of a given packet */
335struct eth_tx_2nd_bd {
336 struct regpair addr;
337 __le16 nbytes;
338 struct eth_tx_data_2nd_bd data;
339};
340
341/* The parsing information data for the third tx bd of a given packet. */
342struct eth_tx_data_3rd_bd {
343 __le16 lso_mss;
344 __le16 bitfields;
345#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF
346#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0
347#define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF
348#define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT 4
349#define ETH_TX_DATA_3RD_BD_START_BD_MASK 0x1
350#define ETH_TX_DATA_3RD_BD_START_BD_SHIFT 8
351#define ETH_TX_DATA_3RD_BD_RESERVED0_MASK 0x7F
352#define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT 9
353 u8 tunn_l4_hdr_start_offset_w;
354 u8 tunn_hdr_size_w;
355};
356
357/* The third tx bd of a given packet */
358struct eth_tx_3rd_bd {
359 struct regpair addr;
360 __le16 nbytes;
361 struct eth_tx_data_3rd_bd data;
362};
363
364/* Complementary information for the regular tx bd of a given packet. */
365struct eth_tx_data_bd {
366 __le16 reserved0;
367 __le16 bitfields;
368#define ETH_TX_DATA_BD_RESERVED1_MASK 0xFF
369#define ETH_TX_DATA_BD_RESERVED1_SHIFT 0
370#define ETH_TX_DATA_BD_START_BD_MASK 0x1
371#define ETH_TX_DATA_BD_START_BD_SHIFT 8
372#define ETH_TX_DATA_BD_RESERVED2_MASK 0x7F
373#define ETH_TX_DATA_BD_RESERVED2_SHIFT 9
374 __le16 reserved3;
375};
376
377/* The common non-special TX BD ring element */
378struct eth_tx_bd {
379 struct regpair addr;
380 __le16 nbytes;
381 struct eth_tx_data_bd data;
382};
383
384union eth_tx_bd_types {
385 struct eth_tx_1st_bd first_bd;
386 struct eth_tx_2nd_bd second_bd;
387 struct eth_tx_3rd_bd third_bd;
388 struct eth_tx_bd reg_bd;
389};
390
391/* Mstorm Queue Zone */
392enum eth_tx_tunn_type {
393 ETH_TX_TUNN_GENEVE,
394 ETH_TX_TUNN_TTAG,
395 ETH_TX_TUNN_GRE,
396 ETH_TX_TUNN_VXLAN,
397 MAX_ETH_TX_TUNN_TYPE
398};
399
400/* Ystorm Queue Zone */
401struct xstorm_eth_queue_zone {
402 struct coalescing_timeset int_coalescing_timeset;
403 u8 reserved[7];
404};
405
406/* ETH doorbell data */
407struct eth_db_data {
408 u8 params;
409#define ETH_DB_DATA_DEST_MASK 0x3
410#define ETH_DB_DATA_DEST_SHIFT 0
411#define ETH_DB_DATA_AGG_CMD_MASK 0x3
412#define ETH_DB_DATA_AGG_CMD_SHIFT 2
413#define ETH_DB_DATA_BYPASS_EN_MASK 0x1
414#define ETH_DB_DATA_BYPASS_EN_SHIFT 4
415#define ETH_DB_DATA_RESERVED_MASK 0x1
416#define ETH_DB_DATA_RESERVED_SHIFT 5
417#define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3
418#define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6
419 u8 agg_flags;
420 __le16 bd_prod;
421};
422
423#endif /* __ETH_COMMON__ */