tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Universal Flash Storage Host controller driver
3 *
4 * This code is based on drivers/scsi/ufs/ufshci.h
5 * Copyright (C) 2011-2013 Samsung India Software Operations
6 *
7 * Authors:
8 * Santosh Yaraganavi <santosh.sy@samsung.com>
9 * Vinayak Holikatti <h.vinayak@samsung.com>
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version 2
14 * of the License, or (at your option) any later version.
15 * See the COPYING file in the top-level directory or visit
16 * <http://www.gnu.org/licenses/gpl-2.0.html>
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * This program is provided "AS IS" and "WITH ALL FAULTS" and
24 * without warranty of any kind. You are solely responsible for
25 * determining the appropriateness of using and distributing
26 * the program and assume all risks associated with your exercise
27 * of rights with respect to the program, including but not limited
28 * to infringement of third party rights, the risks and costs of
29 * program errors, damage to or loss of data, programs or equipment,
30 * and unavailability or interruption of operations. Under no
31 * circumstances will the contributor of this Program be liable for
32 * any damages of any kind arising from your use or distribution of
33 * this program.
34 */
35
36#ifndef _UFSHCI_H
37#define _UFSHCI_H
38
39enum {
40 TASK_REQ_UPIU_SIZE_DWORDS = 8,
41 TASK_RSP_UPIU_SIZE_DWORDS = 8,
42 ALIGNED_UPIU_SIZE = 512,
43};
44
45/* UFSHCI Registers */
46enum {
47 REG_CONTROLLER_CAPABILITIES = 0x00,
48 REG_UFS_VERSION = 0x08,
49 REG_CONTROLLER_DEV_ID = 0x10,
50 REG_CONTROLLER_PROD_ID = 0x14,
51 REG_INTERRUPT_STATUS = 0x20,
52 REG_INTERRUPT_ENABLE = 0x24,
53 REG_CONTROLLER_STATUS = 0x30,
54 REG_CONTROLLER_ENABLE = 0x34,
55 REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
56 REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
57 REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
58 REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
59 REG_UIC_ERROR_CODE_DME = 0x48,
60 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
61 REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
62 REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
63 REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
64 REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
65 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
66 REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
67 REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
68 REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
69 REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
70 REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
71 REG_UIC_COMMAND = 0x90,
72 REG_UIC_COMMAND_ARG_1 = 0x94,
73 REG_UIC_COMMAND_ARG_2 = 0x98,
74 REG_UIC_COMMAND_ARG_3 = 0x9C,
75};
76
77/* Controller capability masks */
78enum {
79 MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
80 MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
81 MASK_64_ADDRESSING_SUPPORT = 0x01000000,
82 MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
83 MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
84};
85
86/* UFS Version 08h */
87#define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0)
88#define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16)
89
90/* Controller UFSHCI version */
91enum {
92 UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */
93 UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */
94 UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */
95 UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */
96};
97
98/*
99 * HCDDID - Host Controller Identification Descriptor
100 * - Device ID and Device Class 10h
101 */
102#define DEVICE_CLASS UFS_MASK(0xFFFF, 0)
103#define DEVICE_ID UFS_MASK(0xFF, 24)
104
105/*
106 * HCPMID - Host Controller Identification Descriptor
107 * - Product/Manufacturer ID 14h
108 */
109#define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0)
110#define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16)
111
112#define UFS_BIT(x) (1L << (x))
113
114#define UTP_TRANSFER_REQ_COMPL UFS_BIT(0)
115#define UIC_DME_END_PT_RESET UFS_BIT(1)
116#define UIC_ERROR UFS_BIT(2)
117#define UIC_TEST_MODE UFS_BIT(3)
118#define UIC_POWER_MODE UFS_BIT(4)
119#define UIC_HIBERNATE_EXIT UFS_BIT(5)
120#define UIC_HIBERNATE_ENTER UFS_BIT(6)
121#define UIC_LINK_LOST UFS_BIT(7)
122#define UIC_LINK_STARTUP UFS_BIT(8)
123#define UTP_TASK_REQ_COMPL UFS_BIT(9)
124#define UIC_COMMAND_COMPL UFS_BIT(10)
125#define DEVICE_FATAL_ERROR UFS_BIT(11)
126#define CONTROLLER_FATAL_ERROR UFS_BIT(16)
127#define SYSTEM_BUS_FATAL_ERROR UFS_BIT(17)
128
129#define UFSHCD_UIC_PWR_MASK (UIC_HIBERNATE_ENTER |\
130 UIC_HIBERNATE_EXIT |\
131 UIC_POWER_MODE)
132
133#define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)
134
135#define UFSHCD_ERROR_MASK (UIC_ERROR |\
136 DEVICE_FATAL_ERROR |\
137 CONTROLLER_FATAL_ERROR |\
138 SYSTEM_BUS_FATAL_ERROR)
139
140#define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
141 CONTROLLER_FATAL_ERROR |\
142 SYSTEM_BUS_FATAL_ERROR)
143
144/* HCS - Host Controller Status 30h */
145#define DEVICE_PRESENT UFS_BIT(0)
146#define UTP_TRANSFER_REQ_LIST_READY UFS_BIT(1)
147#define UTP_TASK_REQ_LIST_READY UFS_BIT(2)
148#define UIC_COMMAND_READY UFS_BIT(3)
149#define HOST_ERROR_INDICATOR UFS_BIT(4)
150#define DEVICE_ERROR_INDICATOR UFS_BIT(5)
151#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
152
153enum {
154 PWR_OK = 0x0,
155 PWR_LOCAL = 0x01,
156 PWR_REMOTE = 0x02,
157 PWR_BUSY = 0x03,
158 PWR_ERROR_CAP = 0x04,
159 PWR_FATAL_ERROR = 0x05,
160};
161
162/* HCE - Host Controller Enable 34h */
163#define CONTROLLER_ENABLE UFS_BIT(0)
164#define CONTROLLER_DISABLE 0x0
165
166/* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
167#define UIC_PHY_ADAPTER_LAYER_ERROR UFS_BIT(31)
168#define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F
169
170/* UECDL - Host UIC Error Code Data Link Layer 3Ch */
171#define UIC_DATA_LINK_LAYER_ERROR UFS_BIT(31)
172#define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0x7FFF
173#define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000
174#define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001
175#define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
176
177/* UECN - Host UIC Error Code Network Layer 40h */
178#define UIC_NETWORK_LAYER_ERROR UFS_BIT(31)
179#define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7
180
181/* UECT - Host UIC Error Code Transport Layer 44h */
182#define UIC_TRANSPORT_LAYER_ERROR UFS_BIT(31)
183#define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F
184
185/* UECDME - Host UIC Error Code DME 48h */
186#define UIC_DME_ERROR UFS_BIT(31)
187#define UIC_DME_ERROR_CODE_MASK 0x1
188
189#define INT_AGGR_TIMEOUT_VAL_MASK 0xFF
190#define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8)
191#define INT_AGGR_COUNTER_AND_TIMER_RESET UFS_BIT(16)
192#define INT_AGGR_STATUS_BIT UFS_BIT(20)
193#define INT_AGGR_PARAM_WRITE UFS_BIT(24)
194#define INT_AGGR_ENABLE UFS_BIT(31)
195
196/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
197#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT UFS_BIT(0)
198
199/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
200#define UTP_TASK_REQ_LIST_RUN_STOP_BIT UFS_BIT(0)
201
202/* UICCMD - UIC Command */
203#define COMMAND_OPCODE_MASK 0xFF
204#define GEN_SELECTOR_INDEX_MASK 0xFFFF
205
206#define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
207#define RESET_LEVEL 0xFF
208
209#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
210#define CONFIG_RESULT_CODE_MASK 0xFF
211#define GENERIC_ERROR_CODE_MASK 0xFF
212
213/* GenSelectorIndex calculation macros for M-PHY attributes */
214#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
215#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
216
217#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
218 ((sel) & 0xFFFF))
219#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
220#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
221#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
222
223/* Link Status*/
224enum link_status {
225 UFSHCD_LINK_IS_DOWN = 1,
226 UFSHCD_LINK_IS_UP = 2,
227};
228
229/* UIC Commands */
230enum uic_cmd_dme {
231 UIC_CMD_DME_GET = 0x01,
232 UIC_CMD_DME_SET = 0x02,
233 UIC_CMD_DME_PEER_GET = 0x03,
234 UIC_CMD_DME_PEER_SET = 0x04,
235 UIC_CMD_DME_POWERON = 0x10,
236 UIC_CMD_DME_POWEROFF = 0x11,
237 UIC_CMD_DME_ENABLE = 0x12,
238 UIC_CMD_DME_RESET = 0x14,
239 UIC_CMD_DME_END_PT_RST = 0x15,
240 UIC_CMD_DME_LINK_STARTUP = 0x16,
241 UIC_CMD_DME_HIBER_ENTER = 0x17,
242 UIC_CMD_DME_HIBER_EXIT = 0x18,
243 UIC_CMD_DME_TEST_MODE = 0x1A,
244};
245
246/* UIC Config result code / Generic error code */
247enum {
248 UIC_CMD_RESULT_SUCCESS = 0x00,
249 UIC_CMD_RESULT_INVALID_ATTR = 0x01,
250 UIC_CMD_RESULT_FAILURE = 0x01,
251 UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
252 UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
253 UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
254 UIC_CMD_RESULT_BAD_INDEX = 0x05,
255 UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
256 UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
257 UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
258 UIC_CMD_RESULT_BUSY = 0x09,
259 UIC_CMD_RESULT_DME_FAILURE = 0x0A,
260};
261
262#define MASK_UIC_COMMAND_RESULT 0xFF
263
264#define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8)
265#define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0)
266
267/* Interrupt disable masks */
268enum {
269 /* Interrupt disable mask for UFSHCI v1.0 */
270 INTERRUPT_MASK_ALL_VER_10 = 0x30FFF,
271 INTERRUPT_MASK_RW_VER_10 = 0x30000,
272
273 /* Interrupt disable mask for UFSHCI v1.1 */
274 INTERRUPT_MASK_ALL_VER_11 = 0x31FFF,
275};
276
277/*
278 * Request Descriptor Definitions
279 */
280
281/* Transfer request command type */
282enum {
283 UTP_CMD_TYPE_SCSI = 0x0,
284 UTP_CMD_TYPE_UFS = 0x1,
285 UTP_CMD_TYPE_DEV_MANAGE = 0x2,
286};
287
288/* To accommodate UFS2.0 required Command type */
289enum {
290 UTP_CMD_TYPE_UFS_STORAGE = 0x1,
291};
292
293enum {
294 UTP_SCSI_COMMAND = 0x00000000,
295 UTP_NATIVE_UFS_COMMAND = 0x10000000,
296 UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
297 UTP_REQ_DESC_INT_CMD = 0x01000000,
298};
299
300/* UTP Transfer Request Data Direction (DD) */
301enum {
302 UTP_NO_DATA_TRANSFER = 0x00000000,
303 UTP_HOST_TO_DEVICE = 0x02000000,
304 UTP_DEVICE_TO_HOST = 0x04000000,
305};
306
307/* Overall command status values */
308enum {
309 OCS_SUCCESS = 0x0,
310 OCS_INVALID_CMD_TABLE_ATTR = 0x1,
311 OCS_INVALID_PRDT_ATTR = 0x2,
312 OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
313 OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
314 OCS_PEER_COMM_FAILURE = 0x5,
315 OCS_ABORTED = 0x6,
316 OCS_FATAL_ERROR = 0x7,
317 OCS_INVALID_COMMAND_STATUS = 0x0F,
318 MASK_OCS = 0x0F,
319};
320
321/* The maximum length of the data byte count field in the PRDT is 256KB */
322#define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024)
323/* The granularity of the data byte count field in the PRDT is 32-bit */
324#define PRDT_DATA_BYTE_COUNT_PAD 4
325
326/**
327 * struct ufshcd_sg_entry - UFSHCI PRD Entry
328 * @base_addr: Lower 32bit physical address DW-0
329 * @upper_addr: Upper 32bit physical address DW-1
330 * @reserved: Reserved for future use DW-2
331 * @size: size of physical segment DW-3
332 */
333struct ufshcd_sg_entry {
334 __le32 base_addr;
335 __le32 upper_addr;
336 __le32 reserved;
337 __le32 size;
338};
339
340/**
341 * struct utp_transfer_cmd_desc - UFS Command Descriptor structure
342 * @command_upiu: Command UPIU Frame address
343 * @response_upiu: Response UPIU Frame address
344 * @prd_table: Physical Region Descriptor
345 */
346struct utp_transfer_cmd_desc {
347 u8 command_upiu[ALIGNED_UPIU_SIZE];
348 u8 response_upiu[ALIGNED_UPIU_SIZE];
349 struct ufshcd_sg_entry prd_table[SG_ALL];
350};
351
352/**
353 * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
354 * @dword0: Descriptor Header DW0
355 * @dword1: Descriptor Header DW1
356 * @dword2: Descriptor Header DW2
357 * @dword3: Descriptor Header DW3
358 */
359struct request_desc_header {
360 __le32 dword_0;
361 __le32 dword_1;
362 __le32 dword_2;
363 __le32 dword_3;
364};
365
366/**
367 * struct utp_transfer_req_desc - UTRD structure
368 * @header: UTRD header DW-0 to DW-3
369 * @command_desc_base_addr_lo: UCD base address low DW-4
370 * @command_desc_base_addr_hi: UCD base address high DW-5
371 * @response_upiu_length: response UPIU length DW-6
372 * @response_upiu_offset: response UPIU offset DW-6
373 * @prd_table_length: Physical region descriptor length DW-7
374 * @prd_table_offset: Physical region descriptor offset DW-7
375 */
376struct utp_transfer_req_desc {
377
378 /* DW 0-3 */
379 struct request_desc_header header;
380
381 /* DW 4-5*/
382 __le32 command_desc_base_addr_lo;
383 __le32 command_desc_base_addr_hi;
384
385 /* DW 6 */
386 __le16 response_upiu_length;
387 __le16 response_upiu_offset;
388
389 /* DW 7 */
390 __le16 prd_table_length;
391 __le16 prd_table_offset;
392};
393
394/**
395 * struct utp_task_req_desc - UTMRD structure
396 * @header: UTMRD header DW-0 to DW-3
397 * @task_req_upiu: Pointer to task request UPIU DW-4 to DW-11
398 * @task_rsp_upiu: Pointer to task response UPIU DW12 to DW-19
399 */
400struct utp_task_req_desc {
401
402 /* DW 0-3 */
403 struct request_desc_header header;
404
405 /* DW 4-11 */
406 __le32 task_req_upiu[TASK_REQ_UPIU_SIZE_DWORDS];
407
408 /* DW 12-19 */
409 __le32 task_rsp_upiu[TASK_RSP_UPIU_SIZE_DWORDS];
410};
411
412#endif /* End of Header */