tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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kernel / drivers / pinctrl / sunxi / pinctrl-gr8.c
at v4.9 541 lines 21 kB view raw
1/* 2 * NextThing GR8 SoCs pinctrl driver. 3 * 4 * Copyright (C) 2016 Mylene Josserand 5 * 6 * Based on pinctrl-sun5i-a13.c 7 * 8 * Mylene Josserand <mylene.josserand@free-electrons.com> 9 * 10 * This file is licensed under the terms of the GNU General Public 11 * License version 2. This program is licensed "as is" without any 12 * warranty of any kind, whether express or implied. 13 */ 14 15#include <linux/module.h> 16#include <linux/platform_device.h> 17#include <linux/of.h> 18#include <linux/of_device.h> 19#include <linux/pinctrl/pinctrl.h> 20 21#include "pinctrl-sunxi.h" 22 23static const struct sunxi_desc_pin sun5i_gr8_pins[] = { 24 /* Hole */ 25 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), 26 SUNXI_FUNCTION(0x0, "gpio_in"), 27 SUNXI_FUNCTION(0x1, "gpio_out"), 28 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ 29 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), 30 SUNXI_FUNCTION(0x0, "gpio_in"), 31 SUNXI_FUNCTION(0x1, "gpio_out"), 32 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ 33 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), 34 SUNXI_FUNCTION(0x0, "gpio_in"), 35 SUNXI_FUNCTION(0x1, "gpio_out"), 36 SUNXI_FUNCTION(0x2, "pwm0"), 37 SUNXI_FUNCTION(0x3, "spdif"), /* DO */ 38 SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */ 39 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), 40 SUNXI_FUNCTION(0x0, "gpio_in"), 41 SUNXI_FUNCTION(0x1, "gpio_out"), 42 SUNXI_FUNCTION(0x2, "ir0"), /* TX */ 43 SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */ 44 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), 45 SUNXI_FUNCTION(0x0, "gpio_in"), 46 SUNXI_FUNCTION(0x1, "gpio_out"), 47 SUNXI_FUNCTION(0x2, "ir0"), /* RX */ 48 SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */ 49 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), 50 SUNXI_FUNCTION(0x0, "gpio_in"), 51 SUNXI_FUNCTION(0x1, "gpio_out"), 52 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */ 53 SUNXI_FUNCTION_IRQ(0x6, 19)), /* EINT19 */ 54 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), 55 SUNXI_FUNCTION(0x0, "gpio_in"), 56 SUNXI_FUNCTION(0x1, "gpio_out"), 57 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */ 58 SUNXI_FUNCTION_IRQ(0x6, 20)), /* EINT20 */ 59 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), 60 SUNXI_FUNCTION(0x0, "gpio_in"), 61 SUNXI_FUNCTION(0x1, "gpio_out"), 62 SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */ 63 SUNXI_FUNCTION_IRQ(0x6, 21)), /* EINT21 */ 64 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), 65 SUNXI_FUNCTION(0x0, "gpio_in"), 66 SUNXI_FUNCTION(0x1, "gpio_out"), 67 SUNXI_FUNCTION(0x2, "i2s0"), /* DO */ 68 SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */ 69 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9), 70 SUNXI_FUNCTION(0x0, "gpio_in"), 71 SUNXI_FUNCTION(0x1, "gpio_out"), 72 SUNXI_FUNCTION(0x2, "i2s0"), /* DI */ 73 SUNXI_FUNCTION(0x3, "spdif"), /* DI */ 74 SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */ 75 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), 76 SUNXI_FUNCTION(0x0, "gpio_in"), 77 SUNXI_FUNCTION(0x1, "gpio_out"), 78 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */ 79 SUNXI_FUNCTION(0x3, "spdif"), /* DO */ 80 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */ 81 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11), 82 SUNXI_FUNCTION(0x0, "gpio_in"), 83 SUNXI_FUNCTION(0x1, "gpio_out"), 84 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */ 85 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */ 86 SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */ 87 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12), 88 SUNXI_FUNCTION(0x0, "gpio_in"), 89 SUNXI_FUNCTION(0x1, "gpio_out"), 90 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */ 91 SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */ 92 SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */ 93 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13), 94 SUNXI_FUNCTION(0x0, "gpio_in"), 95 SUNXI_FUNCTION(0x1, "gpio_out"), 96 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */ 97 SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */ 98 SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */ 99 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14), 100 SUNXI_FUNCTION(0x0, "gpio_in"), 101 SUNXI_FUNCTION(0x1, "gpio_out"), 102 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */ 103 SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */ 104 SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */ 105 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15), 106 SUNXI_FUNCTION(0x0, "gpio_in"), 107 SUNXI_FUNCTION(0x1, "gpio_out"), 108 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ 109 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16), 110 SUNXI_FUNCTION(0x0, "gpio_in"), 111 SUNXI_FUNCTION(0x1, "gpio_out"), 112 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ 113 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17), 114 SUNXI_FUNCTION(0x0, "gpio_in"), 115 SUNXI_FUNCTION(0x1, "gpio_out"), 116 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ 117 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18), 118 SUNXI_FUNCTION(0x0, "gpio_in"), 119 SUNXI_FUNCTION(0x1, "gpio_out"), 120 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ 121 /* Hole */ 122 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), 123 SUNXI_FUNCTION(0x0, "gpio_in"), 124 SUNXI_FUNCTION(0x1, "gpio_out"), 125 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ 126 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ 127 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), 128 SUNXI_FUNCTION(0x0, "gpio_in"), 129 SUNXI_FUNCTION(0x1, "gpio_out"), 130 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ 131 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ 132 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), 133 SUNXI_FUNCTION(0x0, "gpio_in"), 134 SUNXI_FUNCTION(0x1, "gpio_out"), 135 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ 136 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ 137 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), 138 SUNXI_FUNCTION(0x0, "gpio_in"), 139 SUNXI_FUNCTION(0x1, "gpio_out"), 140 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */ 141 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ 142 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), 143 SUNXI_FUNCTION(0x0, "gpio_in"), 144 SUNXI_FUNCTION(0x1, "gpio_out"), 145 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ 146 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), 147 SUNXI_FUNCTION(0x0, "gpio_in"), 148 SUNXI_FUNCTION(0x1, "gpio_out"), 149 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */ 150 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), 151 SUNXI_FUNCTION(0x0, "gpio_in"), 152 SUNXI_FUNCTION(0x1, "gpio_out"), 153 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ 154 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ 155 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), 156 SUNXI_FUNCTION(0x0, "gpio_in"), 157 SUNXI_FUNCTION(0x1, "gpio_out"), 158 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ 159 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ 160 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), 161 SUNXI_FUNCTION(0x0, "gpio_in"), 162 SUNXI_FUNCTION(0x1, "gpio_out"), 163 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ 164 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ 165 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), 166 SUNXI_FUNCTION(0x0, "gpio_in"), 167 SUNXI_FUNCTION(0x1, "gpio_out"), 168 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ 169 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ 170 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), 171 SUNXI_FUNCTION(0x0, "gpio_in"), 172 SUNXI_FUNCTION(0x1, "gpio_out"), 173 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ 174 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ 175 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), 176 SUNXI_FUNCTION(0x0, "gpio_in"), 177 SUNXI_FUNCTION(0x1, "gpio_out"), 178 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ 179 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ 180 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), 181 SUNXI_FUNCTION(0x0, "gpio_in"), 182 SUNXI_FUNCTION(0x1, "gpio_out"), 183 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */ 184 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ 185 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), 186 SUNXI_FUNCTION(0x0, "gpio_in"), 187 SUNXI_FUNCTION(0x1, "gpio_out"), 188 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */ 189 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ 190 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), 191 SUNXI_FUNCTION(0x0, "gpio_in"), 192 SUNXI_FUNCTION(0x1, "gpio_out"), 193 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */ 194 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ 195 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), 196 SUNXI_FUNCTION(0x0, "gpio_in"), 197 SUNXI_FUNCTION(0x1, "gpio_out"), 198 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */ 199 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ 200 /* Hole */ 201 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19), 202 SUNXI_FUNCTION(0x0, "gpio_in"), 203 SUNXI_FUNCTION(0x1, "gpio_out"), 204 SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */ 205 SUNXI_FUNCTION(0x3, "uart2"), /* RX */ 206 SUNXI_FUNCTION(0x4, "uart3")), /* RTS */ 207 /* Hole */ 208 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), 209 SUNXI_FUNCTION(0x0, "gpio_in"), 210 SUNXI_FUNCTION(0x1, "gpio_out"), 211 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ 212 SUNXI_FUNCTION(0x3, "uart2")), /* TX */ 213 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), 214 SUNXI_FUNCTION(0x0, "gpio_in"), 215 SUNXI_FUNCTION(0x1, "gpio_out"), 216 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ 217 SUNXI_FUNCTION(0x3, "uart2")), /* RX */ 218 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), 219 SUNXI_FUNCTION(0x0, "gpio_in"), 220 SUNXI_FUNCTION(0x1, "gpio_out"), 221 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ 222 SUNXI_FUNCTION(0x3, "uart2")), /* CTS */ 223 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), 224 SUNXI_FUNCTION(0x0, "gpio_in"), 225 SUNXI_FUNCTION(0x1, "gpio_out"), 226 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ 227 SUNXI_FUNCTION(0x3, "uart2")), /* RTS */ 228 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), 229 SUNXI_FUNCTION(0x0, "gpio_in"), 230 SUNXI_FUNCTION(0x1, "gpio_out"), 231 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ 232 SUNXI_FUNCTION(0x3, "emac")), /* ECRS */ 233 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), 234 SUNXI_FUNCTION(0x0, "gpio_in"), 235 SUNXI_FUNCTION(0x1, "gpio_out"), 236 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ 237 SUNXI_FUNCTION(0x3, "emac")), /* ECOL */ 238 /* Hole */ 239 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), 240 SUNXI_FUNCTION(0x0, "gpio_in"), 241 SUNXI_FUNCTION(0x1, "gpio_out"), 242 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ 243 SUNXI_FUNCTION(0x3, "emac")), /* ERXD0 */ 244 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), 245 SUNXI_FUNCTION(0x0, "gpio_in"), 246 SUNXI_FUNCTION(0x1, "gpio_out"), 247 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ 248 SUNXI_FUNCTION(0x3, "emac")), /* ERXD1 */ 249 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), 250 SUNXI_FUNCTION(0x0, "gpio_in"), 251 SUNXI_FUNCTION(0x1, "gpio_out"), 252 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ 253 SUNXI_FUNCTION(0x3, "emac")), /* ERXD2 */ 254 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), 255 SUNXI_FUNCTION(0x0, "gpio_in"), 256 SUNXI_FUNCTION(0x1, "gpio_out"), 257 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ 258 SUNXI_FUNCTION(0x3, "emac")), /* ERXD3 */ 259 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), 260 SUNXI_FUNCTION(0x0, "gpio_in"), 261 SUNXI_FUNCTION(0x1, "gpio_out"), 262 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ 263 SUNXI_FUNCTION(0x3, "emac")), /* ERXCK */ 264 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), 265 SUNXI_FUNCTION(0x0, "gpio_in"), 266 SUNXI_FUNCTION(0x1, "gpio_out"), 267 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ 268 SUNXI_FUNCTION(0x3, "emac")), /* ERXERR */ 269 /* Hole */ 270 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), 271 SUNXI_FUNCTION(0x0, "gpio_in"), 272 SUNXI_FUNCTION(0x1, "gpio_out"), 273 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ 274 SUNXI_FUNCTION(0x3, "emac")), /* ERXDV */ 275 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), 276 SUNXI_FUNCTION(0x0, "gpio_in"), 277 SUNXI_FUNCTION(0x1, "gpio_out"), 278 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ 279 SUNXI_FUNCTION(0x3, "emac")), /* ETXD0 */ 280 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), 281 SUNXI_FUNCTION(0x0, "gpio_in"), 282 SUNXI_FUNCTION(0x1, "gpio_out"), 283 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ 284 SUNXI_FUNCTION(0x3, "emac")), /* ETXD1 */ 285 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), 286 SUNXI_FUNCTION(0x0, "gpio_in"), 287 SUNXI_FUNCTION(0x1, "gpio_out"), 288 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ 289 SUNXI_FUNCTION(0x3, "emac")), /* ETXD2 */ 290 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), 291 SUNXI_FUNCTION(0x0, "gpio_in"), 292 SUNXI_FUNCTION(0x1, "gpio_out"), 293 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ 294 SUNXI_FUNCTION(0x3, "emac")), /* ETXD3 */ 295 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), 296 SUNXI_FUNCTION(0x0, "gpio_in"), 297 SUNXI_FUNCTION(0x1, "gpio_out"), 298 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ 299 SUNXI_FUNCTION(0x3, "emac")), /* ETXEN */ 300 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), 301 SUNXI_FUNCTION(0x0, "gpio_in"), 302 SUNXI_FUNCTION(0x1, "gpio_out"), 303 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ 304 SUNXI_FUNCTION(0x3, "emac")), /* ETXCK */ 305 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), 306 SUNXI_FUNCTION(0x0, "gpio_in"), 307 SUNXI_FUNCTION(0x1, "gpio_out"), 308 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ 309 SUNXI_FUNCTION(0x3, "emac")), /* ETXERR*/ 310 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), 311 SUNXI_FUNCTION(0x0, "gpio_in"), 312 SUNXI_FUNCTION(0x1, "gpio_out"), 313 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ 314 SUNXI_FUNCTION(0x3, "emac")), /* EMDC */ 315 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), 316 SUNXI_FUNCTION(0x0, "gpio_in"), 317 SUNXI_FUNCTION(0x1, "gpio_out"), 318 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ 319 SUNXI_FUNCTION(0x3, "emac")), /* EMDIO */ 320 /* Hole */ 321 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), 322 SUNXI_FUNCTION(0x0, "gpio_in"), 323 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */ 324 SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */ 325 SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */ 326 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */ 327 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), 328 SUNXI_FUNCTION(0x0, "gpio_in"), 329 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */ 330 SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */ 331 SUNXI_FUNCTION(0x4, "spi2"), /* CLK */ 332 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */ 333 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), 334 SUNXI_FUNCTION(0x0, "gpio_in"), 335 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */ 336 SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */ 337 SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */ 338 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), 339 SUNXI_FUNCTION(0x0, "gpio_in"), 340 SUNXI_FUNCTION(0x1, "gpio_out"), 341 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */ 342 SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */ 343 SUNXI_FUNCTION(0x4, "spi2")), /* MISO */ 344 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), 345 SUNXI_FUNCTION(0x0, "gpio_in"), 346 SUNXI_FUNCTION(0x1, "gpio_out"), 347 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */ 348 SUNXI_FUNCTION(0x3, "csi0"), /* D0 */ 349 SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */ 350 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), 351 SUNXI_FUNCTION(0x0, "gpio_in"), 352 SUNXI_FUNCTION(0x1, "gpio_out"), 353 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */ 354 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ 355 SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */ 356 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), 357 SUNXI_FUNCTION(0x0, "gpio_in"), 358 SUNXI_FUNCTION(0x1, "gpio_out"), 359 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */ 360 SUNXI_FUNCTION(0x3, "csi0"), /* D2 */ 361 SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */ 362 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), 363 SUNXI_FUNCTION(0x0, "gpio_in"), 364 SUNXI_FUNCTION(0x1, "gpio_out"), 365 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */ 366 SUNXI_FUNCTION(0x3, "csi0"), /* D3 */ 367 SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */ 368 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), 369 SUNXI_FUNCTION(0x0, "gpio_in"), 370 SUNXI_FUNCTION(0x1, "gpio_out"), 371 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */ 372 SUNXI_FUNCTION(0x3, "csi0"), /* D4 */ 373 SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */ 374 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), 375 SUNXI_FUNCTION(0x0, "gpio_in"), 376 SUNXI_FUNCTION(0x1, "gpio_out"), 377 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */ 378 SUNXI_FUNCTION(0x3, "csi0"), /* D5 */ 379 SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */ 380 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), 381 SUNXI_FUNCTION(0x0, "gpio_in"), 382 SUNXI_FUNCTION(0x1, "gpio_out"), 383 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */ 384 SUNXI_FUNCTION(0x3, "csi0"), /* D6 */ 385 SUNXI_FUNCTION(0x4, "uart1")), /* TX */ 386 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), 387 SUNXI_FUNCTION(0x0, "gpio_in"), 388 SUNXI_FUNCTION(0x1, "gpio_out"), 389 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */ 390 SUNXI_FUNCTION(0x3, "csi0"), /* D7 */ 391 SUNXI_FUNCTION(0x4, "uart1")), /* RX */ 392 /* Hole */ 393 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), 394 SUNXI_FUNCTION(0x0, "gpio_in"), 395 SUNXI_FUNCTION(0x1, "gpio_out"), 396 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ 397 SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */ 398 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), 399 SUNXI_FUNCTION(0x0, "gpio_in"), 400 SUNXI_FUNCTION(0x1, "gpio_out"), 401 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ 402 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */ 403 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), 404 SUNXI_FUNCTION(0x0, "gpio_in"), 405 SUNXI_FUNCTION(0x1, "gpio_out"), 406 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ 407 SUNXI_FUNCTION(0x4, "uart0")), /* TX */ 408 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), 409 SUNXI_FUNCTION(0x0, "gpio_in"), 410 SUNXI_FUNCTION(0x1, "gpio_out"), 411 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ 412 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */ 413 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), 414 SUNXI_FUNCTION(0x0, "gpio_in"), 415 SUNXI_FUNCTION(0x1, "gpio_out"), 416 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ 417 SUNXI_FUNCTION(0x4, "uart0")), /* RX */ 418 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), 419 SUNXI_FUNCTION(0x0, "gpio_in"), 420 SUNXI_FUNCTION(0x1, "gpio_out"), 421 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ 422 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */ 423 /* Hole */ 424 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), 425 SUNXI_FUNCTION(0x0, "gpio_in"), 426 SUNXI_FUNCTION(0x2, "gps"), /* CLK */ 427 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */ 428 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), 429 SUNXI_FUNCTION(0x0, "gpio_in"), 430 SUNXI_FUNCTION(0x2, "gps"), /* SIGN */ 431 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */ 432 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), 433 SUNXI_FUNCTION(0x0, "gpio_in"), 434 SUNXI_FUNCTION(0x2, "gps"), /* MAG */ 435 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */ 436 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), 437 SUNXI_FUNCTION(0x0, "gpio_in"), 438 SUNXI_FUNCTION(0x1, "gpio_out"), 439 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ 440 SUNXI_FUNCTION(0x3, "ms"), /* BS */ 441 SUNXI_FUNCTION(0x4, "uart1"), /* TX */ 442 SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */ 443 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), 444 SUNXI_FUNCTION(0x0, "gpio_in"), 445 SUNXI_FUNCTION(0x1, "gpio_out"), 446 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ 447 SUNXI_FUNCTION(0x3, "ms"), /* CLK */ 448 SUNXI_FUNCTION(0x4, "uart1"), /* RX */ 449 SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */ 450 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), 451 SUNXI_FUNCTION(0x0, "gpio_in"), 452 SUNXI_FUNCTION(0x1, "gpio_out"), 453 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ 454 SUNXI_FUNCTION(0x3, "ms"), /* D0 */ 455 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */ 456 SUNXI_FUNCTION_IRQ(0x6, 5)), /* EINT5 */ 457 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), 458 SUNXI_FUNCTION(0x0, "gpio_in"), 459 SUNXI_FUNCTION(0x1, "gpio_out"), 460 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ 461 SUNXI_FUNCTION(0x3, "ms"), /* D1 */ 462 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */ 463 SUNXI_FUNCTION(0x5, "uart2"), /* RTS */ 464 SUNXI_FUNCTION_IRQ(0x6, 6)), /* EINT6 */ 465 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), 466 SUNXI_FUNCTION(0x0, "gpio_in"), 467 SUNXI_FUNCTION(0x1, "gpio_out"), 468 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ 469 SUNXI_FUNCTION(0x3, "ms"), /* D2 */ 470 SUNXI_FUNCTION(0x5, "uart2"), /* TX */ 471 SUNXI_FUNCTION_IRQ(0x6, 7)), /* EINT7 */ 472 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), 473 SUNXI_FUNCTION(0x0, "gpio_in"), 474 SUNXI_FUNCTION(0x1, "gpio_out"), 475 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ 476 SUNXI_FUNCTION(0x3, "ms"), /* D3 */ 477 SUNXI_FUNCTION(0x5, "uart2"), /* RX */ 478 SUNXI_FUNCTION_IRQ(0x6, 8)), /* EINT8 */ 479 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), 480 SUNXI_FUNCTION(0x0, "gpio_in"), 481 SUNXI_FUNCTION(0x1, "gpio_out"), 482 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ 483 SUNXI_FUNCTION(0x3, "uart3"), /* TX */ 484 SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */ 485 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), 486 SUNXI_FUNCTION(0x0, "gpio_in"), 487 SUNXI_FUNCTION(0x1, "gpio_out"), 488 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ 489 SUNXI_FUNCTION(0x3, "uart3"), /* RX */ 490 SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */ 491 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), 492 SUNXI_FUNCTION(0x0, "gpio_in"), 493 SUNXI_FUNCTION(0x1, "gpio_out"), 494 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ 495 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ 496 SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */ 497 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), 498 SUNXI_FUNCTION(0x0, "gpio_in"), 499 SUNXI_FUNCTION(0x1, "gpio_out"), 500 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ 501 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ 502 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */ 503 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), 504 SUNXI_FUNCTION(0x0, "gpio_in"), 505 SUNXI_FUNCTION(0x1, "gpio_out"), 506 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ 507 SUNXI_FUNCTION(0x3, "pwm1"), 508 SUNXI_FUNCTION(0x5, "uart2"), /* CTS */ 509 SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */ 510}; 511 512static const struct sunxi_pinctrl_desc sun5i_gr8_pinctrl_data = { 513 .pins = sun5i_gr8_pins, 514 .npins = ARRAY_SIZE(sun5i_gr8_pins), 515 .irq_banks = 1, 516}; 517 518static int sun5i_gr8_pinctrl_probe(struct platform_device *pdev) 519{ 520 return sunxi_pinctrl_init(pdev, 521 &sun5i_gr8_pinctrl_data); 522} 523 524static const struct of_device_id sun5i_gr8_pinctrl_match[] = { 525 { .compatible = "nextthing,gr8-pinctrl", }, 526 {} 527}; 528MODULE_DEVICE_TABLE(of, sun5i_gr8_pinctrl_match); 529 530static struct platform_driver sun5i_gr8_pinctrl_driver = { 531 .probe = sun5i_gr8_pinctrl_probe, 532 .driver = { 533 .name = "gr8-pinctrl", 534 .of_match_table = sun5i_gr8_pinctrl_match, 535 }, 536}; 537module_platform_driver(sun5i_gr8_pinctrl_driver); 538 539MODULE_AUTHOR("Mylene Josserand <mylene.josserand@free-electrons.com"); 540MODULE_DESCRIPTION("NextThing GR8 pinctrl driver"); 541MODULE_LICENSE("GPL");