tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * linux/arch/h8300/kernel/cpu/timer/timer8.c
3 *
4 * Yoshinori Sato <ysato@users.sourcefoge.jp>
5 *
6 * 8bit Timer driver
7 *
8 */
9
10#include <linux/errno.h>
11#include <linux/kernel.h>
12#include <linux/interrupt.h>
13#include <linux/init.h>
14#include <linux/clockchips.h>
15#include <linux/clk.h>
16#include <linux/io.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <linux/of_irq.h>
20
21#define _8TCR 0
22#define _8TCSR 2
23#define TCORA 4
24#define TCORB 6
25#define _8TCNT 8
26
27#define CMIEA 6
28#define CMFA 6
29
30#define FLAG_STARTED (1 << 3)
31
32#define SCALE 64
33
34#define bset(b, a) iowrite8(ioread8(a) | (1 << (b)), (a))
35#define bclr(b, a) iowrite8(ioread8(a) & ~(1 << (b)), (a))
36
37struct timer8_priv {
38 struct clock_event_device ced;
39 void __iomem *mapbase;
40 unsigned long flags;
41 unsigned int rate;
42};
43
44static irqreturn_t timer8_interrupt(int irq, void *dev_id)
45{
46 struct timer8_priv *p = dev_id;
47
48 if (clockevent_state_oneshot(&p->ced))
49 iowrite16be(0x0000, p->mapbase + _8TCR);
50
51 p->ced.event_handler(&p->ced);
52
53 bclr(CMFA, p->mapbase + _8TCSR);
54
55 return IRQ_HANDLED;
56}
57
58static void timer8_set_next(struct timer8_priv *p, unsigned long delta)
59{
60 if (delta >= 0x10000)
61 pr_warn("delta out of range\n");
62 bclr(CMIEA, p->mapbase + _8TCR);
63 iowrite16be(delta, p->mapbase + TCORA);
64 iowrite16be(0x0000, p->mapbase + _8TCNT);
65 bclr(CMFA, p->mapbase + _8TCSR);
66 bset(CMIEA, p->mapbase + _8TCR);
67}
68
69static int timer8_enable(struct timer8_priv *p)
70{
71 iowrite16be(0xffff, p->mapbase + TCORA);
72 iowrite16be(0x0000, p->mapbase + _8TCNT);
73 iowrite16be(0x0c02, p->mapbase + _8TCR);
74
75 return 0;
76}
77
78static int timer8_start(struct timer8_priv *p)
79{
80 int ret;
81
82 if ((p->flags & FLAG_STARTED))
83 return 0;
84
85 ret = timer8_enable(p);
86 if (!ret)
87 p->flags |= FLAG_STARTED;
88
89 return ret;
90}
91
92static void timer8_stop(struct timer8_priv *p)
93{
94 iowrite16be(0x0000, p->mapbase + _8TCR);
95}
96
97static inline struct timer8_priv *ced_to_priv(struct clock_event_device *ced)
98{
99 return container_of(ced, struct timer8_priv, ced);
100}
101
102static void timer8_clock_event_start(struct timer8_priv *p, unsigned long delta)
103{
104 struct clock_event_device *ced = &p->ced;
105
106 timer8_start(p);
107
108 ced->shift = 32;
109 ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
110 ced->max_delta_ns = clockevent_delta2ns(0xffff, ced);
111 ced->min_delta_ns = clockevent_delta2ns(0x0001, ced);
112
113 timer8_set_next(p, delta);
114}
115
116static int timer8_clock_event_shutdown(struct clock_event_device *ced)
117{
118 timer8_stop(ced_to_priv(ced));
119 return 0;
120}
121
122static int timer8_clock_event_periodic(struct clock_event_device *ced)
123{
124 struct timer8_priv *p = ced_to_priv(ced);
125
126 pr_info("%s: used for periodic clock events\n", ced->name);
127 timer8_stop(p);
128 timer8_clock_event_start(p, (p->rate + HZ/2) / HZ);
129
130 return 0;
131}
132
133static int timer8_clock_event_oneshot(struct clock_event_device *ced)
134{
135 struct timer8_priv *p = ced_to_priv(ced);
136
137 pr_info("%s: used for oneshot clock events\n", ced->name);
138 timer8_stop(p);
139 timer8_clock_event_start(p, 0x10000);
140
141 return 0;
142}
143
144static int timer8_clock_event_next(unsigned long delta,
145 struct clock_event_device *ced)
146{
147 struct timer8_priv *p = ced_to_priv(ced);
148
149 BUG_ON(!clockevent_state_oneshot(ced));
150 timer8_set_next(p, delta - 1);
151
152 return 0;
153}
154
155static struct timer8_priv timer8_priv = {
156 .ced = {
157 .name = "h8300_8timer",
158 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
159 .rating = 200,
160 .set_next_event = timer8_clock_event_next,
161 .set_state_shutdown = timer8_clock_event_shutdown,
162 .set_state_periodic = timer8_clock_event_periodic,
163 .set_state_oneshot = timer8_clock_event_oneshot,
164 },
165};
166
167static int __init h8300_8timer_init(struct device_node *node)
168{
169 void __iomem *base;
170 int irq, ret;
171 struct clk *clk;
172
173 clk = of_clk_get(node, 0);
174 if (IS_ERR(clk)) {
175 pr_err("failed to get clock for clockevent\n");
176 return PTR_ERR(clk);
177 }
178
179 ret = ENXIO;
180 base = of_iomap(node, 0);
181 if (!base) {
182 pr_err("failed to map registers for clockevent\n");
183 goto free_clk;
184 }
185
186 ret = -EINVAL;
187 irq = irq_of_parse_and_map(node, 0);
188 if (!irq) {
189 pr_err("failed to get irq for clockevent\n");
190 goto unmap_reg;
191 }
192
193 timer8_priv.mapbase = base;
194
195 timer8_priv.rate = clk_get_rate(clk) / SCALE;
196 if (!timer8_priv.rate) {
197 pr_err("Failed to get rate for the clocksource\n");
198 goto unmap_reg;
199 }
200
201 if (request_irq(irq, timer8_interrupt, IRQF_TIMER,
202 timer8_priv.ced.name, &timer8_priv) < 0) {
203 pr_err("failed to request irq %d for clockevent\n", irq);
204 goto unmap_reg;
205 }
206
207 clockevents_config_and_register(&timer8_priv.ced,
208 timer8_priv.rate, 1, 0x0000ffff);
209
210 return 0;
211unmap_reg:
212 iounmap(base);
213free_clk:
214 clk_put(clk);
215 return ret;
216}
217
218CLOCKSOURCE_OF_DECLARE(h8300_8bit, "renesas,8bit-timer", h8300_8timer_init);