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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/*
2 * arch/arm64/include/asm/arch_gicv3.h
3 *
4 * Copyright (C) 2015 ARM Ltd.
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18#ifndef __ASM_ARCH_GICV3_H
19#define __ASM_ARCH_GICV3_H
20
21#include <asm/sysreg.h>
22
23#define ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
24#define ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
25#define ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
26#define ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
27#define ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
28#define ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
29#define ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
30#define ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
31#define ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
32
33#define ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
34
35/*
36 * System register definitions
37 */
38#define ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
39#define ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
40#define ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
41#define ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
42#define ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
43#define ICH_ELSR_EL2 sys_reg(3, 4, 12, 11, 5)
44#define ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
45
46#define __LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
47#define __LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
48
49#define ICH_LR0_EL2 __LR0_EL2(0)
50#define ICH_LR1_EL2 __LR0_EL2(1)
51#define ICH_LR2_EL2 __LR0_EL2(2)
52#define ICH_LR3_EL2 __LR0_EL2(3)
53#define ICH_LR4_EL2 __LR0_EL2(4)
54#define ICH_LR5_EL2 __LR0_EL2(5)
55#define ICH_LR6_EL2 __LR0_EL2(6)
56#define ICH_LR7_EL2 __LR0_EL2(7)
57#define ICH_LR8_EL2 __LR8_EL2(0)
58#define ICH_LR9_EL2 __LR8_EL2(1)
59#define ICH_LR10_EL2 __LR8_EL2(2)
60#define ICH_LR11_EL2 __LR8_EL2(3)
61#define ICH_LR12_EL2 __LR8_EL2(4)
62#define ICH_LR13_EL2 __LR8_EL2(5)
63#define ICH_LR14_EL2 __LR8_EL2(6)
64#define ICH_LR15_EL2 __LR8_EL2(7)
65
66#define __AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
67#define ICH_AP0R0_EL2 __AP0Rx_EL2(0)
68#define ICH_AP0R1_EL2 __AP0Rx_EL2(1)
69#define ICH_AP0R2_EL2 __AP0Rx_EL2(2)
70#define ICH_AP0R3_EL2 __AP0Rx_EL2(3)
71
72#define __AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
73#define ICH_AP1R0_EL2 __AP1Rx_EL2(0)
74#define ICH_AP1R1_EL2 __AP1Rx_EL2(1)
75#define ICH_AP1R2_EL2 __AP1Rx_EL2(2)
76#define ICH_AP1R3_EL2 __AP1Rx_EL2(3)
77
78#ifndef __ASSEMBLY__
79
80#include <linux/stringify.h>
81#include <asm/barrier.h>
82
83#define read_gicreg(r) \
84 ({ \
85 u64 reg; \
86 asm volatile("mrs_s %0, " __stringify(r) : "=r" (reg)); \
87 reg; \
88 })
89
90#define write_gicreg(v,r) \
91 do { \
92 u64 __val = (v); \
93 asm volatile("msr_s " __stringify(r) ", %0" : : "r" (__val));\
94 } while (0)
95
96/*
97 * Low-level accessors
98 *
99 * These system registers are 32 bits, but we make sure that the compiler
100 * sets the GP register's most significant bits to 0 with an explicit cast.
101 */
102
103static inline void gic_write_eoir(u32 irq)
104{
105 asm volatile("msr_s " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" ((u64)irq));
106 isb();
107}
108
109static inline void gic_write_dir(u32 irq)
110{
111 asm volatile("msr_s " __stringify(ICC_DIR_EL1) ", %0" : : "r" ((u64)irq));
112 isb();
113}
114
115static inline u64 gic_read_iar_common(void)
116{
117 u64 irqstat;
118
119 asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
120 dsb(sy);
121 return irqstat;
122}
123
124/*
125 * Cavium ThunderX erratum 23154
126 *
127 * The gicv3 of ThunderX requires a modified version for reading the
128 * IAR status to ensure data synchronization (access to icc_iar1_el1
129 * is not sync'ed before and after).
130 */
131static inline u64 gic_read_iar_cavium_thunderx(void)
132{
133 u64 irqstat;
134
135 asm volatile(
136 "nop;nop;nop;nop\n\t"
137 "nop;nop;nop;nop\n\t"
138 "mrs_s %0, " __stringify(ICC_IAR1_EL1) "\n\t"
139 "nop;nop;nop;nop"
140 : "=r" (irqstat));
141 mb();
142
143 return irqstat;
144}
145
146static inline void gic_write_pmr(u32 val)
147{
148 asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" ((u64)val));
149}
150
151static inline void gic_write_ctlr(u32 val)
152{
153 asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" ((u64)val));
154 isb();
155}
156
157static inline void gic_write_grpen1(u32 val)
158{
159 asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" ((u64)val));
160 isb();
161}
162
163static inline void gic_write_sgi1r(u64 val)
164{
165 asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));
166}
167
168static inline u32 gic_read_sre(void)
169{
170 u64 val;
171
172 asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
173 return val;
174}
175
176static inline void gic_write_sre(u32 val)
177{
178 asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" ((u64)val));
179 isb();
180}
181
182static inline void gic_write_bpr1(u32 val)
183{
184 asm volatile("msr_s " __stringify(ICC_BPR1_EL1) ", %0" : : "r" (val));
185}
186
187#define gic_read_typer(c) readq_relaxed(c)
188#define gic_write_irouter(v, c) writeq_relaxed(v, c)
189
190#endif /* __ASSEMBLY__ */
191#endif /* __ASM_ARCH_GICV3_H */