drivers/pinctrl/sh-pfc/pfc-r8a7790.c at v4.9-rc7

tjh.dev / kernel
fork
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork
kernel / drivers / pinctrl / sh-pfc / pfc-r8a7790.c
at v4.9-rc7 5729 lines 187 kB view raw
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   1/*
   2 * R8A7790 processor support
   3 *
   4 * Copyright (C) 2013  Renesas Electronics Corporation
   5 * Copyright (C) 2013  Magnus Damm
   6 * Copyright (C) 2012  Renesas Solutions Corp.
   7 * Copyright (C) 2012  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License as
  11 * published by the Free Software Foundation; version 2 of the
  12 * License.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  22 */
  23
  24#include <linux/io.h>
  25#include <linux/kernel.h>
  26
  27#include "sh_pfc.h"
  28
  29/*
  30 * All pins assigned to GPIO bank 3 can be used for SD interfaces in
  31 * which case they support both 3.3V and 1.8V signalling.
  32 */
  33#define CPU_ALL_PORT(fn, sfx)						\
  34	PORT_GP_32(0, fn, sfx),						\
  35	PORT_GP_30(1, fn, sfx),						\
  36	PORT_GP_30(2, fn, sfx),						\
  37	PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),		\
  38	PORT_GP_32(4, fn, sfx),						\
  39	PORT_GP_32(5, fn, sfx)
  40
  41enum {
  42	PINMUX_RESERVED = 0,
  43
  44	PINMUX_DATA_BEGIN,
  45	GP_ALL(DATA),
  46	PINMUX_DATA_END,
  47
  48	PINMUX_FUNCTION_BEGIN,
  49	GP_ALL(FN),
  50
  51	/* GPSR0 */
  52	FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
  53	FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
  54	FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
  55	FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
  56	FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
  57	FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
  58	FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
  59	FN_IP3_14_12, FN_IP3_17_15,
  60
  61	/* GPSR1 */
  62	FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
  63	FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
  64	FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
  65	FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
  66	FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
  67	FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
  68	FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
  69
  70	/* GPSR2 */
  71	FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
  72	FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
  73	FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
  74	FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
  75	FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
  76	FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
  77	FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
  78
  79	/* GPSR3 */
  80	FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
  81	FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
  82	FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
  83	FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
  84	FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
  85	FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
  86	FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
  87
  88	/* GPSR4 */
  89	FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
  90	FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
  91	FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
  92	FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
  93	FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
  94	FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
  95	FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
  96	FN_IP14_15_12, FN_IP14_18_16,
  97
  98	/* GPSR5 */
  99	FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
 100	FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
 101	FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
 102	FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
 103	FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
 104	FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
 105	FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
 106
 107	/* IPSR0 */
 108	FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
 109	FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5,
 110	FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2,
 111	FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B,
 112	FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4,
 113	FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
 114	FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5,
 115	FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
 116	FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6,
 117	FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
 118	FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
 119	FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1,
 120	FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0,
 121	FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
 122
 123	/* IPSR1 */
 124	FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1,
 125	FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,
 126	FN_SCIFA1_TXD_C, FN_AVB_TXD2,
 127	FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,
 128	FN_SCIFA1_CTS_N_C, FN_AVB_TXD3,
 129	FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
 130	FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
 131	FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
 132	FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
 133	FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14,
 134	FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
 135	FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
 136	FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
 137	FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
 138	FN_A0, FN_PWM3, FN_A1, FN_PWM4,
 139
 140	/* IPSR2 */
 141	FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3,
 142	FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B,
 143	FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1,
 144	FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7,
 145	FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
 146	FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
 147	FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
 148	FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
 149	FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
 150	FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
 151	FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B,
 152
 153	/* IPSR3 */
 154	FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
 155	FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B,
 156	FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
 157	FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
 158	FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
 159	FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
 160	FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B,
 161	FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B,
 162	FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N,
 163	FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18,
 164	FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B,
 165	FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK,
 166	FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
 167
 168	/* IPSR4 */
 169	FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5,
 170	FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B,
 171	FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7,
 172	FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3,
 173	FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
 174	FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6,
 175	FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N,
 176	FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
 177	FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
 178	FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B,
 179	FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B,
 180	FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK,
 181	FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B,
 182	FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
 183	FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2,
 184
 185	/* IPSR5 */
 186	FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
 187	FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
 188	FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
 189	FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX,
 190	FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2,
 191	FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
 192	FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B,
 193	FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
 194	FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
 195	FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
 196	FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,
 197	FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
 198	FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
 199	FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
 200	FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
 201	FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
 202	FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
 203	FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
 204	FN_SSI_WS78_B,
 205
 206	/* IPSR6 */
 207	FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
 208	FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
 209	FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
 210	FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
 211	FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
 212	FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
 213	FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
 214	FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
 215	FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,
 216	FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
 217	FN_I2C2_SCL_E, FN_ETH_RX_ER,
 218	FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
 219	FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0,
 220	FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
 221	FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
 222	FN_HRX0_E, FN_STP_ISSYNC_0_B,
 223	FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
 224	FN_RX1_E, FN_ETH_LINK, FN_HTX0_E,
 225	FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
 226	FN_ETH_REF_CLK, FN_HCTS0_N_E,
 227	FN_STP_IVCXO27_1_B, FN_HRX0_F,
 228
 229	/* IPSR7 */
 230	FN_ETH_MDIO, FN_HRTS0_N_E,
 231	FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
 232	FN_HTX0_F, FN_BPFCLK_G,
 233	FN_ETH_TX_EN, FN_SIM0_CLK_C,
 234	FN_HRTS0_N_F, FN_ETH_MAGIC,
 235	FN_SIM0_RST_C, FN_ETH_TXD0,
 236	FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
 237	FN_ETH_MDC, FN_STP_ISD_1_B,
 238	FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
 239	FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
 240	FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
 241	FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
 242	FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
 243	FN_PCMWE_N, FN_IECLK_C, FN_DU_DOTCLKIN1,
 244	FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
 245	FN_ATACS00_N, FN_AVB_RXD1,
 246	FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
 247
 248	/* IPSR8 */
 249	FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
 250	FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
 251	FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
 252	FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
 253	FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
 254	FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
 255	FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
 256	FN_VI1_CLK, FN_AVB_RX_DV,
 257	FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
 258	FN_AVB_CRS, FN_VI1_DATA1_VI1_B1,
 259	FN_SCIFA1_RXD_D, FN_AVB_MDC,
 260	FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
 261	FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
 262	FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
 263	FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5,
 264	FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
 265	FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
 266	FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
 267
 268	/* IPSR9 */
 269	FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
 270	FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
 271	FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
 272	FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
 273	FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
 274	FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
 275	FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
 276	FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
 277	FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
 278	FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
 279	FN_AVB_TX_EN, FN_SD1_CMD,
 280	FN_AVB_TX_ER, FN_SCIFB0_SCK_B,
 281	FN_SD1_DAT0, FN_AVB_TX_CLK,
 282	FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
 283	FN_SCIFB0_TXD_B, FN_SD1_DAT2,
 284	FN_AVB_COL, FN_SCIFB0_CTS_N_B,
 285	FN_SD1_DAT3, FN_AVB_RXD0,
 286	FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
 287	FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
 288	FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B,
 289	FN_VI3_CLK_B,
 290
 291	/* IPSR10 */
 292	FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
 293	FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
 294	FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
 295	FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
 296	FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
 297	FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
 298	FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
 299	FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
 300	FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
 301	FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
 302	FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B,
 303	FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
 304	FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
 305	FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B,
 306	FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
 307	FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
 308	FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
 309	FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
 310	FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
 311	FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
 312	FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
 313	FN_GLO_I0_B, FN_VI3_DATA6_B,
 314
 315	/* IPSR11 */
 316	FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
 317	FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
 318	FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
 319	FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
 320	FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
 321	FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
 322	FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
 323	FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
 324	FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
 325	FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
 326	FN_FMIN_E, FN_FMIN_F,
 327	FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B,
 328	FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B,
 329	FN_I2C2_SDA_B, FN_MLB_DAT,
 330	FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
 331	FN_SSI_SCK0129, FN_CAN_CLK_B,
 332	FN_MOUT0,
 333
 334	/* IPSR12 */
 335	FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1,
 336	FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2,
 337	FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5,
 338	FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
 339	FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
 340	FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34,
 341	FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
 342	FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0,
 343	FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK,
 344	FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
 345	FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0,
 346	FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
 347	FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1,
 348	FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
 349	FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK,
 350	FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
 351	FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD,
 352	FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
 353	FN_CAN_DEBUGOUT4,
 354
 355	/* IPSR13 */
 356	FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
 357	FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
 358	FN_SCIFB1_CTS_N, FN_BPFCLK_D,
 359	FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
 360	FN_BPFCLK_F, FN_SSI_WS6,
 361	FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
 362	FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
 363	FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5,
 364	FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
 365	FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
 366	FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
 367	FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7,
 368	FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
 369	FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
 370	FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
 371	FN_BPFCLK_E, FN_SSI_SDATA7_B,
 372	FN_FMIN_G, FN_SSI_SDATA8,
 373	FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
 374	FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
 375	FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
 376	FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA,
 377	FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14,
 378
 379	/* IPSR14 */
 380	FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
 381	FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
 382	FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0,
 383	FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C,
 384	FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
 385	FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1,
 386	FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N,
 387	FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3,
 388	FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
 389	FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
 390	FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B,
 391	FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
 392	FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE,
 393	FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
 394	FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK,
 395	FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK,
 396	FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
 397	FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
 398	FN_HRTS0_N_C,
 399
 400	/* IPSR15 */
 401	FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
 402	FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN,
 403	FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL,
 404	FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
 405	FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0,
 406	FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0,
 407	FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3,
 408	FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4,
 409	FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5,
 410	FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
 411	FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0,
 412	FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23,
 413	FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0,
 414	FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1,
 415	FN_DU2_DG6, FN_LCDOUT14,
 416
 417	/* IPSR16 */
 418	FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
 419	FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B,
 420	FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
 421	FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B,
 422	FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC,
 423	FN_TCLK1_B,
 424
 425	FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
 426	FN_SEL_SCIF1_4,
 427	FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
 428	FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
 429	FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
 430	FN_SEL_SCIFB1_4,
 431	FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
 432	FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
 433	FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
 434	FN_SEL_SCFA_0, FN_SEL_SCFA_1,
 435	FN_SEL_SOF1_0, FN_SEL_SOF1_1,
 436	FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
 437	FN_SEL_SSI6_0, FN_SEL_SSI6_1,
 438	FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
 439	FN_SEL_VI3_0, FN_SEL_VI3_1,
 440	FN_SEL_VI2_0, FN_SEL_VI2_1,
 441	FN_SEL_VI1_0, FN_SEL_VI1_1,
 442	FN_SEL_VI0_0, FN_SEL_VI0_1,
 443	FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
 444	FN_SEL_LBS_0, FN_SEL_LBS_1,
 445	FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
 446	FN_SEL_SOF3_0, FN_SEL_SOF3_1,
 447	FN_SEL_SOF0_0, FN_SEL_SOF0_1,
 448
 449	FN_SEL_TMU1_0, FN_SEL_TMU1_1,
 450	FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
 451	FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
 452	FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
 453	FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
 454	FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
 455	FN_SEL_CAN1_0, FN_SEL_CAN1_1,
 456	FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
 457	FN_SEL_ADI_0, FN_SEL_ADI_1,
 458	FN_SEL_SSP_0, FN_SEL_SSP_1,
 459	FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
 460	FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
 461	FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
 462	FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
 463	FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
 464	FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
 465	FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
 466
 467	FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
 468	FN_SEL_IIC0_0, FN_SEL_IIC0_1,
 469	FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
 470	FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
 471	FN_SEL_IIC2_4,
 472	FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
 473	FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
 474	FN_SEL_I2C2_4,
 475	FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
 476	PINMUX_FUNCTION_END,
 477
 478	PINMUX_MARK_BEGIN,
 479
 480	VI1_DATA7_VI1_B7_MARK,
 481
 482	USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
 483	USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
 484	DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
 485
 486	D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
 487	D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
 488	VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
 489	VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
 490	VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
 491	SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
 492	VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
 493	SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
 494	VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
 495	IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
 496	I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK,
 497	VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK,
 498	D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK,
 499	VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
 500
 501	D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK,
 502	VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
 503	SCIFA1_TXD_C_MARK, AVB_TXD2_MARK,
 504	VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
 505	SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK,
 506	VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
 507	D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
 508	VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
 509	D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
 510	VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
 511	SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
 512	VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
 513	D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
 514	VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
 515	A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
 516
 517	A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
 518	PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
 519	TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
 520	A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
 521	SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
 522	A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
 523	VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK,
 524	A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
 525	VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK,
 526	A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
 527	VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
 528
 529	A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
 530	VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
 531	A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
 532	VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
 533	A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
 534	MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
 535	VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
 536	ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
 537	ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
 538	A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
 539	AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
 540	ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
 541	VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
 542
 543	A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
 544	A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
 545	VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
 546	VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
 547	VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
 548	VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
 549	VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
 550	VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
 551	CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
 552	VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
 553	VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
 554	MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
 555	HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
 556	VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
 557	VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
 558
 559	EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
 560	VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
 561	EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
 562	VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK,
 563	INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
 564	MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
 565	VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK,
 566	I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
 567	CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
 568	CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
 569	VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
 570	INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
 571	VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
 572	WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
 573	VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
 574	IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
 575	VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
 576	MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
 577	VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
 578	SSI_WS78_B_MARK,
 579
 580	DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
 581	VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
 582	DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
 583	SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
 584	INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
 585	DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
 586	MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
 587	SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
 588	ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
 589	TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,
 590	I2C2_SCL_E_MARK, ETH_RX_ER_MARK,
 591	STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
 592	IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK,
 593	STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
 594	SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
 595	HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
 596	TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
 597	RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK,
 598	STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
 599	ETH_REF_CLK_MARK, HCTS0_N_E_MARK,
 600	STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
 601
 602	ETH_MDIO_MARK, HRTS0_N_E_MARK,
 603	SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
 604	HTX0_F_MARK, BPFCLK_G_MARK,
 605	ETH_TX_EN_MARK, SIM0_CLK_C_MARK,
 606	HRTS0_N_F_MARK, ETH_MAGIC_MARK,
 607	SIM0_RST_C_MARK, ETH_TXD0_MARK,
 608	STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
 609	ETH_MDC_MARK, STP_ISD_1_B_MARK,
 610	TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
 611	SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
 612	GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
 613	STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
 614	PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
 615	PCMWE_N_MARK, IECLK_C_MARK, DU_DOTCLKIN1_MARK,
 616	AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
 617	ATACS00_N_MARK, AVB_RXD1_MARK,
 618	VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
 619
 620	VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
 621	VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
 622	AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
 623	AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
 624	AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
 625	AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
 626	VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
 627	VI1_CLK_MARK, AVB_RX_DV_MARK,
 628	VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
 629	AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
 630	SCIFA1_RXD_D_MARK, AVB_MDC_MARK,
 631	VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
 632	VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
 633	AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
 634	AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
 635	AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
 636	SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
 637	SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
 638
 639	SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
 640	SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
 641	SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
 642	SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
 643	SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
 644	GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK,
 645	I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
 646	MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
 647	GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK,
 648	I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
 649	AVB_TX_EN_MARK, SD1_CMD_MARK,
 650	AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK,
 651	SD1_DAT0_MARK, AVB_TX_CLK_MARK,
 652	SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
 653	SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
 654	AVB_COL_MARK, SCIFB0_CTS_N_B_MARK,
 655	SD1_DAT3_MARK, AVB_RXD0_MARK,
 656	SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
 657	TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
 658	IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK,
 659	VI3_CLK_B_MARK,
 660
 661	SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
 662	GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK,
 663	SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
 664	VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
 665	VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
 666	VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
 667	TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
 668	SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
 669	VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
 670	TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
 671	SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK,
 672	VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
 673	TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
 674	SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK,
 675	VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
 676	GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
 677	MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
 678	HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
 679	VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
 680	TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
 681	VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
 682	GLO_I0_B_MARK, VI3_DATA6_B_MARK,
 683
 684	SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
 685	GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
 686	TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
 687	SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
 688	MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
 689	SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
 690	MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
 691	SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
 692	VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
 693	MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
 694	FMIN_E_MARK, FMIN_F_MARK,
 695	MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK,
 696	MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK,
 697	I2C2_SDA_B_MARK, MLB_DAT_MARK,
 698	SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
 699	SSI_SCK0129_MARK, CAN_CLK_B_MARK,
 700	MOUT0_MARK,
 701
 702	SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
 703	SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
 704	SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
 705	SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
 706	SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
 707	MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
 708	STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
 709	CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
 710	SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
 711	SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
 712	MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
 713	SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
 714	MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
 715	SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
 716	CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
 717	IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
 718	CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
 719	IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
 720	CAN_DEBUGOUT4_MARK,
 721
 722	SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
 723	LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
 724	SCIFB1_CTS_N_MARK, BPFCLK_D_MARK,
 725	DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
 726	BPFCLK_F_MARK, SSI_WS6_MARK,
 727	SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
 728	LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
 729	FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
 730	CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
 731	SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
 732	CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
 733	SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
 734	LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
 735	STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
 736	TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
 737	BPFCLK_E_MARK, SSI_SDATA7_B_MARK,
 738	FMIN_G_MARK, SSI_SDATA8_MARK,
 739	STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
 740	CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
 741	STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
 742	SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
 743	SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
 744
 745	AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
 746	DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
 747	REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
 748	MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK,
 749	I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
 750	DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
 751	TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
 752	HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
 753	LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK,
 754	SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK,
 755	MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
 756	SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
 757	DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
 758	SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
 759	LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
 760	CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
 761	SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK,
 762	MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
 763	HRTS0_N_C_MARK,
 764
 765	SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
 766	LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
 767	TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK,
 768	SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
 769	IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK,
 770	DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
 771	DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
 772	LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
 773	LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
 774	LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
 775	DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
 776	SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
 777	HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
 778	DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
 779	DU2_DG6_MARK, LCDOUT14_MARK,
 780
 781	MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
 782	DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
 783	MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
 784	ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK,
 785	USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
 786	TCLK1_B_MARK,
 787
 788	IIC0_SCL_MARK, IIC0_SDA_MARK, I2C0_SCL_MARK, I2C0_SDA_MARK,
 789	IIC3_SCL_MARK, IIC3_SDA_MARK, I2C3_SCL_MARK, I2C3_SDA_MARK,
 790	PINMUX_MARK_END,
 791};
 792
 793static const u16 pinmux_data[] = {
 794	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 795
 796	PINMUX_SINGLE(VI1_DATA7_VI1_B7),
 797	PINMUX_SINGLE(USB0_PWEN),
 798	PINMUX_SINGLE(USB0_OVC_VBUS),
 799	PINMUX_SINGLE(USB2_PWEN),
 800	PINMUX_SINGLE(USB2_OVC),
 801	PINMUX_SINGLE(AVS1),
 802	PINMUX_SINGLE(AVS2),
 803	PINMUX_SINGLE(DU_DOTCLKIN0),
 804	PINMUX_SINGLE(DU_DOTCLKIN2),
 805
 806	PINMUX_IPSR_GPSR(IP0_2_0, D0),
 807	PINMUX_IPSR_MSEL(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
 808	PINMUX_IPSR_MSEL(IP0_2_0, VI3_DATA0, SEL_VI3_0),
 809	PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4, SEL_VI0_0),
 810	PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4_B, SEL_VI0_1),
 811	PINMUX_IPSR_GPSR(IP0_5_3, D1),
 812	PINMUX_IPSR_MSEL(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
 813	PINMUX_IPSR_MSEL(IP0_5_3, VI3_DATA1, SEL_VI3_0),
 814	PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5, SEL_VI0_0),
 815	PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5_B, SEL_VI0_1),
 816	PINMUX_IPSR_GPSR(IP0_8_6, D2),
 817	PINMUX_IPSR_MSEL(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
 818	PINMUX_IPSR_MSEL(IP0_8_6, VI3_DATA2, SEL_VI3_0),
 819	PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6, SEL_VI0_0),
 820	PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6_B, SEL_VI0_1),
 821	PINMUX_IPSR_GPSR(IP0_11_9, D3),
 822	PINMUX_IPSR_MSEL(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
 823	PINMUX_IPSR_MSEL(IP0_11_9, VI3_DATA3, SEL_VI3_0),
 824	PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7, SEL_VI0_0),
 825	PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7_B, SEL_VI0_1),
 826	PINMUX_IPSR_GPSR(IP0_15_12, D4),
 827	PINMUX_IPSR_MSEL(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
 828	PINMUX_IPSR_MSEL(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
 829	PINMUX_IPSR_MSEL(IP0_15_12, VI3_DATA4, SEL_VI3_0),
 830	PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0, SEL_VI0_0),
 831	PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0_B, SEL_VI0_1),
 832	PINMUX_IPSR_MSEL(IP0_15_12, RX0_B, SEL_SCIF0_1),
 833	PINMUX_IPSR_GPSR(IP0_19_16, D5),
 834	PINMUX_IPSR_MSEL(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
 835	PINMUX_IPSR_MSEL(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
 836	PINMUX_IPSR_MSEL(IP0_19_16, VI3_DATA5, SEL_VI3_0),
 837	PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1, SEL_VI0_0),
 838	PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1_B, SEL_VI0_1),
 839	PINMUX_IPSR_MSEL(IP0_19_16, TX0_B, SEL_SCIF0_1),
 840	PINMUX_IPSR_GPSR(IP0_22_20, D6),
 841	PINMUX_IPSR_MSEL(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2),
 842	PINMUX_IPSR_MSEL(IP0_22_20, VI3_DATA6, SEL_VI3_0),
 843	PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2, SEL_VI0_0),
 844	PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2_B, SEL_VI0_1),
 845	PINMUX_IPSR_MSEL(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2),
 846	PINMUX_IPSR_GPSR(IP0_26_23, D7),
 847	PINMUX_IPSR_MSEL(IP0_26_23, AD_DI_B, SEL_ADI_1),
 848	PINMUX_IPSR_MSEL(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2),
 849	PINMUX_IPSR_MSEL(IP0_26_23, VI3_DATA7, SEL_VI3_0),
 850	PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3, SEL_VI0_0),
 851	PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3_B, SEL_VI0_1),
 852	PINMUX_IPSR_MSEL(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2),
 853	PINMUX_IPSR_MSEL(IP0_26_23, TCLK1, SEL_TMU1_0),
 854	PINMUX_IPSR_GPSR(IP0_30_27, D8),
 855	PINMUX_IPSR_MSEL(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
 856	PINMUX_IPSR_GPSR(IP0_30_27, AVB_TXD0),
 857	PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0, SEL_VI0_0),
 858	PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0_B, SEL_VI0_1),
 859	PINMUX_IPSR_MSEL(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
 860
 861	PINMUX_IPSR_GPSR(IP1_3_0, D9),
 862	PINMUX_IPSR_MSEL(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
 863	PINMUX_IPSR_GPSR(IP1_3_0, AVB_TXD1),
 864	PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1, SEL_VI0_0),
 865	PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1_B, SEL_VI0_1),
 866	PINMUX_IPSR_MSEL(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
 867	PINMUX_IPSR_GPSR(IP1_7_4, D10),
 868	PINMUX_IPSR_MSEL(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
 869	PINMUX_IPSR_GPSR(IP1_7_4, AVB_TXD2),
 870	PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2, SEL_VI0_0),
 871	PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2_B, SEL_VI0_1),
 872	PINMUX_IPSR_MSEL(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
 873	PINMUX_IPSR_GPSR(IP1_11_8, D11),
 874	PINMUX_IPSR_MSEL(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
 875	PINMUX_IPSR_GPSR(IP1_11_8, AVB_TXD3),
 876	PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3, SEL_VI0_0),
 877	PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3_B, SEL_VI0_1),
 878	PINMUX_IPSR_MSEL(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
 879	PINMUX_IPSR_GPSR(IP1_14_12, D12),
 880	PINMUX_IPSR_MSEL(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
 881	PINMUX_IPSR_GPSR(IP1_14_12, AVB_TXD4),
 882	PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
 883	PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
 884	PINMUX_IPSR_MSEL(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
 885	PINMUX_IPSR_GPSR(IP1_17_15, D13),
 886	PINMUX_IPSR_GPSR(IP1_17_15, AVB_TXD5),
 887	PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
 888	PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
 889	PINMUX_IPSR_MSEL(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
 890	PINMUX_IPSR_GPSR(IP1_21_18, D14),
 891	PINMUX_IPSR_MSEL(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
 892	PINMUX_IPSR_GPSR(IP1_21_18, AVB_TXD6),
 893	PINMUX_IPSR_MSEL(IP1_21_18, RX1_B, SEL_SCIF1_1),
 894	PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
 895	PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
 896	PINMUX_IPSR_MSEL(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
 897	PINMUX_IPSR_GPSR(IP1_25_22, D15),
 898	PINMUX_IPSR_MSEL(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
 899	PINMUX_IPSR_GPSR(IP1_25_22, AVB_TXD7),
 900	PINMUX_IPSR_MSEL(IP1_25_22, TX1_B, SEL_SCIF1_1),
 901	PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD, SEL_VI0_0),
 902	PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
 903	PINMUX_IPSR_MSEL(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
 904	PINMUX_IPSR_GPSR(IP1_27_26, A0),
 905	PINMUX_IPSR_GPSR(IP1_27_26, PWM3),
 906	PINMUX_IPSR_GPSR(IP1_29_28, A1),
 907	PINMUX_IPSR_GPSR(IP1_29_28, PWM4),
 908
 909	PINMUX_IPSR_GPSR(IP2_2_0, A2),
 910	PINMUX_IPSR_GPSR(IP2_2_0, PWM5),
 911	PINMUX_IPSR_MSEL(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
 912	PINMUX_IPSR_GPSR(IP2_5_3, A3),
 913	PINMUX_IPSR_GPSR(IP2_5_3, PWM6),
 914	PINMUX_IPSR_MSEL(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
 915	PINMUX_IPSR_GPSR(IP2_8_6, A4),
 916	PINMUX_IPSR_MSEL(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
 917	PINMUX_IPSR_GPSR(IP2_8_6, TPU0TO0),
 918	PINMUX_IPSR_GPSR(IP2_11_9, A5),
 919	PINMUX_IPSR_MSEL(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
 920	PINMUX_IPSR_GPSR(IP2_11_9, TPU0TO1),
 921	PINMUX_IPSR_GPSR(IP2_14_12, A6),
 922	PINMUX_IPSR_MSEL(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
 923	PINMUX_IPSR_GPSR(IP2_14_12, TPU0TO2),
 924	PINMUX_IPSR_GPSR(IP2_17_15, A7),
 925	PINMUX_IPSR_MSEL(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
 926	PINMUX_IPSR_GPSR(IP2_17_15, AUDIO_CLKOUT_B),
 927	PINMUX_IPSR_GPSR(IP2_17_15, TPU0TO3),
 928	PINMUX_IPSR_GPSR(IP2_21_18, A8),
 929	PINMUX_IPSR_MSEL(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
 930	PINMUX_IPSR_MSEL(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
 931	PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4, SEL_VI0_0),
 932	PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4_B, SEL_VI0_1),
 933	PINMUX_IPSR_MSEL(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
 934	PINMUX_IPSR_MSEL(IP2_21_18, RX2_B, SEL_SCIF2_1),
 935	PINMUX_IPSR_MSEL(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
 936	PINMUX_IPSR_GPSR(IP2_25_22, A9),
 937	PINMUX_IPSR_MSEL(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
 938	PINMUX_IPSR_MSEL(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
 939	PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5, SEL_VI0_0),
 940	PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5_B, SEL_VI0_1),
 941	PINMUX_IPSR_MSEL(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
 942	PINMUX_IPSR_MSEL(IP2_25_22, TX2_B, SEL_SCIF2_1),
 943	PINMUX_IPSR_MSEL(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
 944	PINMUX_IPSR_GPSR(IP2_28_26, A10),
 945	PINMUX_IPSR_MSEL(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
 946	PINMUX_IPSR_GPSR(IP2_28_26, MSIOF2_SYNC),
 947	PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6, SEL_VI0_0),
 948	PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6_B, SEL_VI0_1),
 949	PINMUX_IPSR_MSEL(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
 950
 951	PINMUX_IPSR_GPSR(IP3_3_0, A11),
 952	PINMUX_IPSR_MSEL(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
 953	PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SCK),
 954	PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0, SEL_VI1_0),
 955	PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0_B, SEL_VI1_1),
 956	PINMUX_IPSR_GPSR(IP3_3_0, VI2_G0),
 957	PINMUX_IPSR_MSEL(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1),
 958	PINMUX_IPSR_GPSR(IP3_7_4, A12),
 959	PINMUX_IPSR_MSEL(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
 960	PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
 961	PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1, SEL_VI1_0),
 962	PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1_B, SEL_VI1_1),
 963	PINMUX_IPSR_GPSR(IP3_7_4, VI2_G1),
 964	PINMUX_IPSR_MSEL(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1),
 965	PINMUX_IPSR_GPSR(IP3_11_8, A13),
 966	PINMUX_IPSR_MSEL(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
 967	PINMUX_IPSR_GPSR(IP3_11_8, EX_WAIT2),
 968	PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_RXD),
 969	PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2, SEL_VI1_0),
 970	PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2_B, SEL_VI1_1),
 971	PINMUX_IPSR_GPSR(IP3_11_8, VI2_G2),
 972	PINMUX_IPSR_MSEL(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1),
 973	PINMUX_IPSR_GPSR(IP3_14_12, A14),
 974	PINMUX_IPSR_MSEL(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
 975	PINMUX_IPSR_GPSR(IP3_14_12, ATACS11_N),
 976	PINMUX_IPSR_GPSR(IP3_14_12, MSIOF2_SS1),
 977	PINMUX_IPSR_GPSR(IP3_17_15, A15),
 978	PINMUX_IPSR_MSEL(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
 979	PINMUX_IPSR_GPSR(IP3_17_15, ATARD1_N),
 980	PINMUX_IPSR_GPSR(IP3_17_15, MSIOF2_SS2),
 981	PINMUX_IPSR_GPSR(IP3_19_18, A16),
 982	PINMUX_IPSR_GPSR(IP3_19_18, ATAWR1_N),
 983	PINMUX_IPSR_GPSR(IP3_22_20, A17),
 984	PINMUX_IPSR_MSEL(IP3_22_20, AD_DO_B, SEL_ADI_1),
 985	PINMUX_IPSR_GPSR(IP3_22_20, ATADIR1_N),
 986	PINMUX_IPSR_GPSR(IP3_25_23, A18),
 987	PINMUX_IPSR_MSEL(IP3_25_23, AD_CLK_B, SEL_ADI_1),
 988	PINMUX_IPSR_GPSR(IP3_25_23, ATAG1_N),
 989	PINMUX_IPSR_GPSR(IP3_28_26, A19),
 990	PINMUX_IPSR_MSEL(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
 991	PINMUX_IPSR_GPSR(IP3_28_26, ATACS01_N),
 992	PINMUX_IPSR_MSEL(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
 993	PINMUX_IPSR_GPSR(IP3_31_29, A20),
 994	PINMUX_IPSR_GPSR(IP3_31_29, SPCLK),
 995	PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3, SEL_VI1_0),
 996	PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3_B, SEL_VI1_1),
 997	PINMUX_IPSR_GPSR(IP3_31_29, VI2_G4),
 998
 999	PINMUX_IPSR_GPSR(IP4_2_0, A21),
1000	PINMUX_IPSR_GPSR(IP4_2_0, MOSI_IO0),
1001	PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4, SEL_VI1_0),
1002	PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4_B, SEL_VI1_1),
1003	PINMUX_IPSR_GPSR(IP4_2_0, VI2_G5),
1004	PINMUX_IPSR_GPSR(IP4_5_3, A22),
1005	PINMUX_IPSR_GPSR(IP4_5_3, MISO_IO1),
1006	PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5, SEL_VI1_0),
1007	PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5_B, SEL_VI1_1),
1008	PINMUX_IPSR_GPSR(IP4_5_3, VI2_G6),
1009	PINMUX_IPSR_GPSR(IP4_8_6, A23),
1010	PINMUX_IPSR_GPSR(IP4_8_6, IO2),
1011	PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7, SEL_VI1_0),
1012	PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7_B, SEL_VI1_1),
1013	PINMUX_IPSR_GPSR(IP4_8_6, VI2_G7),
1014	PINMUX_IPSR_GPSR(IP4_11_9, A24),
1015	PINMUX_IPSR_GPSR(IP4_11_9, IO3),
1016	PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7, SEL_VI1_0),
1017	PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7_B, SEL_VI1_1),
1018	PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
1019	PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
1020	PINMUX_IPSR_GPSR(IP4_14_12, A25),
1021	PINMUX_IPSR_GPSR(IP4_14_12, SSL),
1022	PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6, SEL_VI1_0),
1023	PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6_B, SEL_VI1_1),
1024	PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD, SEL_VI2_0),
1025	PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
1026	PINMUX_IPSR_GPSR(IP4_17_15, CS0_N),
1027	PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6, SEL_VI1_0),
1028	PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6_B, SEL_VI1_1),
1029	PINMUX_IPSR_GPSR(IP4_17_15, VI2_G3),
1030	PINMUX_IPSR_MSEL(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
1031	PINMUX_IPSR_GPSR(IP4_20_18, CS1_N_A26),
1032	PINMUX_IPSR_GPSR(IP4_20_18, SPEEDIN),
1033	PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7, SEL_VI0_0),
1034	PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7_B, SEL_VI0_1),
1035	PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK, SEL_VI2_0),
1036	PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
1037	PINMUX_IPSR_GPSR(IP4_23_21, EX_CS0_N),
1038	PINMUX_IPSR_MSEL(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
1039	PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5, SEL_VI1_0),
1040	PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5_B, SEL_VI1_1),
1041	PINMUX_IPSR_GPSR(IP4_23_21, VI2_R0),
1042	PINMUX_IPSR_MSEL(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
1043	PINMUX_IPSR_MSEL(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
1044	PINMUX_IPSR_GPSR(IP4_26_24, EX_CS1_N),
1045	PINMUX_IPSR_GPSR(IP4_26_24, GPS_CLK),
1046	PINMUX_IPSR_MSEL(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
1047	PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD, SEL_VI1_0),
1048	PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
1049	PINMUX_IPSR_GPSR(IP4_26_24, VI2_R1),
1050	PINMUX_IPSR_GPSR(IP4_29_27, EX_CS2_N),
1051	PINMUX_IPSR_GPSR(IP4_29_27, GPS_SIGN),
1052	PINMUX_IPSR_MSEL(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
1053	PINMUX_IPSR_GPSR(IP4_29_27, VI3_CLKENB),
1054	PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0, SEL_VI1_0),
1055	PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0_B, SEL_VI1_1),
1056	PINMUX_IPSR_GPSR(IP4_29_27, VI2_R2),
1057
1058	PINMUX_IPSR_GPSR(IP5_2_0, EX_CS3_N),
1059	PINMUX_IPSR_GPSR(IP5_2_0, GPS_MAG),
1060	PINMUX_IPSR_GPSR(IP5_2_0, VI3_FIELD),
1061	PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1, SEL_VI1_0),
1062	PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1_B, SEL_VI1_1),
1063	PINMUX_IPSR_GPSR(IP5_2_0, VI2_R3),
1064	PINMUX_IPSR_GPSR(IP5_5_3, EX_CS4_N),
1065	PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
1066	PINMUX_IPSR_GPSR(IP5_5_3, VI3_HSYNC_N),
1067	PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
1068	PINMUX_IPSR_MSEL(IP5_5_3, IIC1_SCL, SEL_IIC1_0),
1069	PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
1070	PINMUX_IPSR_GPSR(IP5_5_3, INTC_EN0_N),
1071	PINMUX_IPSR_MSEL(IP5_5_3, I2C1_SCL, SEL_I2C1_0),
1072	PINMUX_IPSR_GPSR(IP5_9_6, EX_CS5_N),
1073	PINMUX_IPSR_MSEL(IP5_9_6, CAN0_RX, SEL_CAN0_0),
1074	PINMUX_IPSR_MSEL(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
1075	PINMUX_IPSR_GPSR(IP5_9_6, VI3_VSYNC_N),
1076	PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2, SEL_VI1_0),
1077	PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2_B, SEL_VI1_1),
1078	PINMUX_IPSR_GPSR(IP5_9_6, VI2_R4),
1079	PINMUX_IPSR_MSEL(IP5_9_6, IIC1_SDA, SEL_IIC1_0),
1080	PINMUX_IPSR_GPSR(IP5_9_6, INTC_EN1_N),
1081	PINMUX_IPSR_MSEL(IP5_9_6, I2C1_SDA, SEL_I2C1_0),
1082	PINMUX_IPSR_GPSR(IP5_12_10, BS_N),
1083	PINMUX_IPSR_MSEL(IP5_12_10, IETX, SEL_IEB_0),
1084	PINMUX_IPSR_MSEL(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
1085	PINMUX_IPSR_MSEL(IP5_12_10, CAN1_TX, SEL_CAN1_0),
1086	PINMUX_IPSR_GPSR(IP5_12_10, DRACK0),
1087	PINMUX_IPSR_MSEL(IP5_12_10, IETX_C, SEL_IEB_2),
1088	PINMUX_IPSR_GPSR(IP5_14_13, RD_N),
1089	PINMUX_IPSR_MSEL(IP5_14_13, CAN0_TX, SEL_CAN0_0),
1090	PINMUX_IPSR_MSEL(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
1091	PINMUX_IPSR_GPSR(IP5_17_15, RD_WR_N),
1092	PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3, SEL_VI1_0),
1093	PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1),
1094	PINMUX_IPSR_GPSR(IP5_17_15, VI2_R5),
1095	PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
1096	PINMUX_IPSR_GPSR(IP5_17_15, INTC_IRQ4_N),
1097	PINMUX_IPSR_GPSR(IP5_20_18, WE0_N),
1098	PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0),
1099	PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
1100	PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
1101	PINMUX_IPSR_MSEL(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
1102	PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
1103	PINMUX_IPSR_GPSR(IP5_23_21, WE1_N),
1104	PINMUX_IPSR_MSEL(IP5_23_21, IERX, SEL_IEB_0),
1105	PINMUX_IPSR_MSEL(IP5_23_21, CAN1_RX, SEL_CAN1_0),
1106	PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4, SEL_VI1_0),
1107	PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4_B, SEL_VI1_1),
1108	PINMUX_IPSR_GPSR(IP5_23_21, VI2_R6),
1109	PINMUX_IPSR_MSEL(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
1110	PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2),
1111	PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0),
1112	PINMUX_IPSR_GPSR(IP5_26_24, IRQ3),
1113	PINMUX_IPSR_GPSR(IP5_26_24, INTC_IRQ3_N),
1114	PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0),
1115	PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
1116	PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
1117	PINMUX_IPSR_MSEL(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
1118	PINMUX_IPSR_GPSR(IP5_29_27, DREQ0_N),
1119	PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
1120	PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
1121	PINMUX_IPSR_GPSR(IP5_29_27, VI2_R7),
1122	PINMUX_IPSR_MSEL(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
1123	PINMUX_IPSR_MSEL(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
1124
1125	PINMUX_IPSR_GPSR(IP6_2_0, DACK0),
1126	PINMUX_IPSR_GPSR(IP6_2_0, IRQ0),
1127	PINMUX_IPSR_GPSR(IP6_2_0, INTC_IRQ0_N),
1128	PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
1129	PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
1130	PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
1131	PINMUX_IPSR_MSEL(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
1132	PINMUX_IPSR_GPSR(IP6_5_3, DREQ1_N),
1133	PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
1134	PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
1135	PINMUX_IPSR_MSEL(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
1136	PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
1137	PINMUX_IPSR_GPSR(IP6_8_6, DACK1),
1138	PINMUX_IPSR_GPSR(IP6_8_6, IRQ1),
1139	PINMUX_IPSR_GPSR(IP6_8_6, INTC_IRQ1_N),
1140	PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
1141	PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
1142	PINMUX_IPSR_GPSR(IP6_10_9, DREQ2_N),
1143	PINMUX_IPSR_MSEL(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
1144	PINMUX_IPSR_MSEL(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
1145	PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
1146	PINMUX_IPSR_GPSR(IP6_13_11, DACK2),
1147	PINMUX_IPSR_GPSR(IP6_13_11, IRQ2),
1148	PINMUX_IPSR_GPSR(IP6_13_11, INTC_IRQ2_N),
1149	PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
1150	PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
1151	PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
1152	PINMUX_IPSR_GPSR(IP6_16_14, ETH_CRS_DV),
1153	PINMUX_IPSR_MSEL(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
1154	PINMUX_IPSR_MSEL(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
1155	PINMUX_IPSR_MSEL(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
1156	PINMUX_IPSR_MSEL(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4),
1157	PINMUX_IPSR_MSEL(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4),
1158	PINMUX_IPSR_GPSR(IP6_19_17, ETH_RX_ER),
1159	PINMUX_IPSR_MSEL(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
1160	PINMUX_IPSR_MSEL(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
1161	PINMUX_IPSR_MSEL(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
1162	PINMUX_IPSR_MSEL(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4),
1163	PINMUX_IPSR_MSEL(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4),
1164	PINMUX_IPSR_GPSR(IP6_22_20, ETH_RXD0),
1165	PINMUX_IPSR_MSEL(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
1166	PINMUX_IPSR_MSEL(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
1167	PINMUX_IPSR_MSEL(IP6_22_20, GLO_I0_C, SEL_GPS_2),
1168	PINMUX_IPSR_MSEL(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
1169	PINMUX_IPSR_MSEL(IP6_22_20, SCK1_E, SEL_SCIF1_4),
1170	PINMUX_IPSR_GPSR(IP6_25_23, ETH_RXD1),
1171	PINMUX_IPSR_MSEL(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
1172	PINMUX_IPSR_MSEL(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
1173	PINMUX_IPSR_MSEL(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
1174	PINMUX_IPSR_MSEL(IP6_25_23, GLO_I1_C, SEL_GPS_2),
1175	PINMUX_IPSR_MSEL(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
1176	PINMUX_IPSR_MSEL(IP6_25_23, RX1_E, SEL_SCIF1_4),
1177	PINMUX_IPSR_GPSR(IP6_28_26, ETH_LINK),
1178	PINMUX_IPSR_MSEL(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
1179	PINMUX_IPSR_MSEL(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
1180	PINMUX_IPSR_MSEL(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
1181	PINMUX_IPSR_MSEL(IP6_28_26, TX1_E, SEL_SCIF1_4),
1182	PINMUX_IPSR_GPSR(IP6_31_29, ETH_REF_CLK),
1183	PINMUX_IPSR_MSEL(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
1184	PINMUX_IPSR_MSEL(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
1185	PINMUX_IPSR_MSEL(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
1186
1187	PINMUX_IPSR_GPSR(IP7_2_0, ETH_MDIO),
1188	PINMUX_IPSR_MSEL(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
1189	PINMUX_IPSR_MSEL(IP7_2_0, SIM0_D_C, SEL_SIM_2),
1190	PINMUX_IPSR_MSEL(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
1191	PINMUX_IPSR_GPSR(IP7_5_3, ETH_TXD1),
1192	PINMUX_IPSR_MSEL(IP7_5_3, HTX0_F, SEL_HSCIF0_5),
1193	PINMUX_IPSR_MSEL(IP7_5_3, BPFCLK_G, SEL_FM_6),
1194	PINMUX_IPSR_GPSR(IP7_7_6, ETH_TX_EN),
1195	PINMUX_IPSR_MSEL(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
1196	PINMUX_IPSR_MSEL(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
1197	PINMUX_IPSR_GPSR(IP7_9_8, ETH_MAGIC),
1198	PINMUX_IPSR_MSEL(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
1199	PINMUX_IPSR_GPSR(IP7_12_10, ETH_TXD0),
1200	PINMUX_IPSR_MSEL(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
1201	PINMUX_IPSR_MSEL(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
1202	PINMUX_IPSR_MSEL(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
1203	PINMUX_IPSR_GPSR(IP7_15_13, ETH_MDC),
1204	PINMUX_IPSR_MSEL(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
1205	PINMUX_IPSR_MSEL(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
1206	PINMUX_IPSR_MSEL(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
1207	PINMUX_IPSR_GPSR(IP7_18_16, PWM0),
1208	PINMUX_IPSR_MSEL(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
1209	PINMUX_IPSR_MSEL(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
1210	PINMUX_IPSR_MSEL(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
1211	PINMUX_IPSR_MSEL(IP7_18_16, GLO_SS_C, SEL_GPS_2),
1212	PINMUX_IPSR_GPSR(IP7_21_19, PWM1),
1213	PINMUX_IPSR_MSEL(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
1214	PINMUX_IPSR_MSEL(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
1215	PINMUX_IPSR_MSEL(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
1216	PINMUX_IPSR_MSEL(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
1217	PINMUX_IPSR_GPSR(IP7_21_19, PCMOE_N),
1218	PINMUX_IPSR_GPSR(IP7_24_22, PWM2),
1219	PINMUX_IPSR_GPSR(IP7_24_22, PWMFSW0),
1220	PINMUX_IPSR_MSEL(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
1221	PINMUX_IPSR_GPSR(IP7_24_22, PCMWE_N),
1222	PINMUX_IPSR_MSEL(IP7_24_22, IECLK_C, SEL_IEB_2),
1223	PINMUX_IPSR_GPSR(IP7_26_25, DU_DOTCLKIN1),
1224	PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKC),
1225	PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKOUT_C),
1226	PINMUX_IPSR_MSEL(IP7_28_27, VI0_CLK, SEL_VI0_0),
1227	PINMUX_IPSR_GPSR(IP7_28_27, ATACS00_N),
1228	PINMUX_IPSR_GPSR(IP7_28_27, AVB_RXD1),
1229	PINMUX_IPSR_MSEL(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
1230	PINMUX_IPSR_GPSR(IP7_30_29, ATACS10_N),
1231	PINMUX_IPSR_GPSR(IP7_30_29, AVB_RXD2),
1232
1233	PINMUX_IPSR_MSEL(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
1234	PINMUX_IPSR_GPSR(IP8_1_0, ATARD0_N),
1235	PINMUX_IPSR_GPSR(IP8_1_0, AVB_RXD3),
1236	PINMUX_IPSR_MSEL(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
1237	PINMUX_IPSR_GPSR(IP8_3_2, ATAWR0_N),
1238	PINMUX_IPSR_GPSR(IP8_3_2, AVB_RXD4),
1239	PINMUX_IPSR_MSEL(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
1240	PINMUX_IPSR_GPSR(IP8_5_4, ATADIR0_N),
1241	PINMUX_IPSR_GPSR(IP8_5_4, AVB_RXD5),
1242	PINMUX_IPSR_MSEL(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
1243	PINMUX_IPSR_GPSR(IP8_7_6, ATAG0_N),
1244	PINMUX_IPSR_GPSR(IP8_7_6, AVB_RXD6),
1245	PINMUX_IPSR_MSEL(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
1246	PINMUX_IPSR_GPSR(IP8_9_8, EX_WAIT1),
1247	PINMUX_IPSR_GPSR(IP8_9_8, AVB_RXD7),
1248	PINMUX_IPSR_MSEL(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
1249	PINMUX_IPSR_GPSR(IP8_11_10, AVB_RX_ER),
1250	PINMUX_IPSR_MSEL(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
1251	PINMUX_IPSR_GPSR(IP8_13_12, AVB_RX_CLK),
1252	PINMUX_IPSR_MSEL(IP8_15_14, VI1_CLK, SEL_VI1_0),
1253	PINMUX_IPSR_GPSR(IP8_15_14, AVB_RX_DV),
1254	PINMUX_IPSR_MSEL(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
1255	PINMUX_IPSR_MSEL(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
1256	PINMUX_IPSR_GPSR(IP8_17_16, AVB_CRS),
1257	PINMUX_IPSR_MSEL(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
1258	PINMUX_IPSR_MSEL(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
1259	PINMUX_IPSR_GPSR(IP8_19_18, AVB_MDC),
1260	PINMUX_IPSR_MSEL(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
1261	PINMUX_IPSR_MSEL(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
1262	PINMUX_IPSR_GPSR(IP8_21_20, AVB_MDIO),
1263	PINMUX_IPSR_MSEL(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
1264	PINMUX_IPSR_MSEL(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
1265	PINMUX_IPSR_GPSR(IP8_23_22, AVB_GTX_CLK),
1266	PINMUX_IPSR_MSEL(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
1267	PINMUX_IPSR_MSEL(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
1268	PINMUX_IPSR_GPSR(IP8_25_24, AVB_MAGIC),
1269	PINMUX_IPSR_MSEL(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
1270	PINMUX_IPSR_GPSR(IP8_26, AVB_PHY_INT),
1271	PINMUX_IPSR_MSEL(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
1272	PINMUX_IPSR_GPSR(IP8_27, AVB_GTXREFCLK),
1273	PINMUX_IPSR_GPSR(IP8_28, SD0_CLK),
1274	PINMUX_IPSR_MSEL(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
1275	PINMUX_IPSR_GPSR(IP8_30_29, SD0_CMD),
1276	PINMUX_IPSR_MSEL(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
1277	PINMUX_IPSR_MSEL(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
1278
1279	PINMUX_IPSR_GPSR(IP9_1_0, SD0_DAT0),
1280	PINMUX_IPSR_MSEL(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
1281	PINMUX_IPSR_MSEL(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
1282	PINMUX_IPSR_GPSR(IP9_3_2, SD0_DAT1),
1283	PINMUX_IPSR_MSEL(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
1284	PINMUX_IPSR_MSEL(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
1285	PINMUX_IPSR_GPSR(IP9_5_4, SD0_DAT2),
1286	PINMUX_IPSR_MSEL(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
1287	PINMUX_IPSR_MSEL(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
1288	PINMUX_IPSR_GPSR(IP9_7_6, SD0_DAT3),
1289	PINMUX_IPSR_MSEL(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
1290	PINMUX_IPSR_MSEL(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
1291	PINMUX_IPSR_GPSR(IP9_11_8, SD0_CD),
1292	PINMUX_IPSR_GPSR(IP9_11_8, MMC0_D6),
1293	PINMUX_IPSR_MSEL(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
1294	PINMUX_IPSR_GPSR(IP9_11_8, USB0_EXTP),
1295	PINMUX_IPSR_MSEL(IP9_11_8, GLO_SCLK, SEL_GPS_0),
1296	PINMUX_IPSR_MSEL(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
1297	PINMUX_IPSR_MSEL(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1),
1298	PINMUX_IPSR_MSEL(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1),
1299	PINMUX_IPSR_MSEL(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
1300	PINMUX_IPSR_GPSR(IP9_15_12, SD0_WP),
1301	PINMUX_IPSR_GPSR(IP9_15_12, MMC0_D7),
1302	PINMUX_IPSR_MSEL(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
1303	PINMUX_IPSR_GPSR(IP9_15_12, USB0_IDIN),
1304	PINMUX_IPSR_MSEL(IP9_15_12, GLO_SDATA, SEL_GPS_0),
1305	PINMUX_IPSR_MSEL(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
1306	PINMUX_IPSR_MSEL(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1),
1307	PINMUX_IPSR_MSEL(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1),
1308	PINMUX_IPSR_MSEL(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
1309	PINMUX_IPSR_GPSR(IP9_17_16, SD1_CLK),
1310	PINMUX_IPSR_GPSR(IP9_17_16, AVB_TX_EN),
1311	PINMUX_IPSR_GPSR(IP9_19_18, SD1_CMD),
1312	PINMUX_IPSR_GPSR(IP9_19_18, AVB_TX_ER),
1313	PINMUX_IPSR_MSEL(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
1314	PINMUX_IPSR_GPSR(IP9_21_20, SD1_DAT0),
1315	PINMUX_IPSR_GPSR(IP9_21_20, AVB_TX_CLK),
1316	PINMUX_IPSR_MSEL(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
1317	PINMUX_IPSR_GPSR(IP9_23_22, SD1_DAT1),
1318	PINMUX_IPSR_GPSR(IP9_23_22, AVB_LINK),
1319	PINMUX_IPSR_MSEL(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
1320	PINMUX_IPSR_GPSR(IP9_25_24, SD1_DAT2),
1321	PINMUX_IPSR_GPSR(IP9_25_24, AVB_COL),
1322	PINMUX_IPSR_MSEL(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
1323	PINMUX_IPSR_GPSR(IP9_27_26, SD1_DAT3),
1324	PINMUX_IPSR_GPSR(IP9_27_26, AVB_RXD0),
1325	PINMUX_IPSR_MSEL(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
1326	PINMUX_IPSR_GPSR(IP9_31_28, SD1_CD),
1327	PINMUX_IPSR_GPSR(IP9_31_28, MMC1_D6),
1328	PINMUX_IPSR_MSEL(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
1329	PINMUX_IPSR_GPSR(IP9_31_28, USB1_EXTP),
1330	PINMUX_IPSR_MSEL(IP9_31_28, GLO_SS, SEL_GPS_0),
1331	PINMUX_IPSR_MSEL(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
1332	PINMUX_IPSR_MSEL(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3),
1333	PINMUX_IPSR_MSEL(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3),
1334	PINMUX_IPSR_MSEL(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
1335	PINMUX_IPSR_MSEL(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
1336
1337	PINMUX_IPSR_GPSR(IP10_3_0, SD1_WP),
1338	PINMUX_IPSR_GPSR(IP10_3_0, MMC1_D7),
1339	PINMUX_IPSR_MSEL(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
1340	PINMUX_IPSR_GPSR(IP10_3_0, USB1_IDIN),
1341	PINMUX_IPSR_MSEL(IP10_3_0, GLO_RFON, SEL_GPS_0),
1342	PINMUX_IPSR_MSEL(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
1343	PINMUX_IPSR_MSEL(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3),
1344	PINMUX_IPSR_MSEL(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3),
1345	PINMUX_IPSR_MSEL(IP10_3_0, SIM0_D_B, SEL_SIM_1),
1346	PINMUX_IPSR_GPSR(IP10_6_4, SD2_CLK),
1347	PINMUX_IPSR_GPSR(IP10_6_4, MMC0_CLK),
1348	PINMUX_IPSR_MSEL(IP10_6_4, SIM0_CLK, SEL_SIM_0),
1349	PINMUX_IPSR_MSEL(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
1350	PINMUX_IPSR_MSEL(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
1351	PINMUX_IPSR_MSEL(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
1352	PINMUX_IPSR_MSEL(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
1353	PINMUX_IPSR_GPSR(IP10_10_7, SD2_CMD),
1354	PINMUX_IPSR_GPSR(IP10_10_7, MMC0_CMD),
1355	PINMUX_IPSR_MSEL(IP10_10_7, SIM0_D, SEL_SIM_0),
1356	PINMUX_IPSR_MSEL(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
1357	PINMUX_IPSR_MSEL(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
1358	PINMUX_IPSR_MSEL(IP10_10_7, SCK1_D, SEL_SCIF1_3),
1359	PINMUX_IPSR_MSEL(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
1360	PINMUX_IPSR_MSEL(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
1361	PINMUX_IPSR_MSEL(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
1362	PINMUX_IPSR_GPSR(IP10_14_11, SD2_DAT0),
1363	PINMUX_IPSR_GPSR(IP10_14_11, MMC0_D0),
1364	PINMUX_IPSR_MSEL(IP10_14_11, FMCLK_B, SEL_FM_1),
1365	PINMUX_IPSR_MSEL(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
1366	PINMUX_IPSR_MSEL(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
1367	PINMUX_IPSR_MSEL(IP10_14_11, RX1_D, SEL_SCIF1_3),
1368	PINMUX_IPSR_MSEL(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
1369	PINMUX_IPSR_MSEL(IP10_14_11, GLO_SS_B, SEL_GPS_1),
1370	PINMUX_IPSR_MSEL(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
1371	PINMUX_IPSR_GPSR(IP10_18_15, SD2_DAT1),
1372	PINMUX_IPSR_GPSR(IP10_18_15, MMC0_D1),
1373	PINMUX_IPSR_MSEL(IP10_18_15, FMIN_B, SEL_FM_1),
1374	PINMUX_IPSR_MSEL(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
1375	PINMUX_IPSR_MSEL(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
1376	PINMUX_IPSR_MSEL(IP10_18_15, TX1_D, SEL_SCIF1_3),
1377	PINMUX_IPSR_MSEL(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
1378	PINMUX_IPSR_MSEL(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
1379	PINMUX_IPSR_MSEL(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
1380	PINMUX_IPSR_GPSR(IP10_22_19, SD2_DAT2),
1381	PINMUX_IPSR_GPSR(IP10_22_19, MMC0_D2),
1382	PINMUX_IPSR_MSEL(IP10_22_19, BPFCLK_B, SEL_FM_1),
1383	PINMUX_IPSR_MSEL(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
1384	PINMUX_IPSR_MSEL(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
1385	PINMUX_IPSR_MSEL(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
1386	PINMUX_IPSR_MSEL(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
1387	PINMUX_IPSR_MSEL(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
1388	PINMUX_IPSR_GPSR(IP10_25_23, SD2_DAT3),
1389	PINMUX_IPSR_GPSR(IP10_25_23, MMC0_D3),
1390	PINMUX_IPSR_MSEL(IP10_25_23, SIM0_RST, SEL_SIM_0),
1391	PINMUX_IPSR_MSEL(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
1392	PINMUX_IPSR_MSEL(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
1393	PINMUX_IPSR_MSEL(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
1394	PINMUX_IPSR_MSEL(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
1395	PINMUX_IPSR_MSEL(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
1396	PINMUX_IPSR_GPSR(IP10_29_26, SD2_CD),
1397	PINMUX_IPSR_GPSR(IP10_29_26, MMC0_D4),
1398	PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
1399	PINMUX_IPSR_GPSR(IP10_29_26, USB2_EXTP),
1400	PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0, SEL_GPS_0),
1401	PINMUX_IPSR_MSEL(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
1402	PINMUX_IPSR_MSEL(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
1403	PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
1404	PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0_B, SEL_GPS_1),
1405	PINMUX_IPSR_MSEL(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
1406
1407	PINMUX_IPSR_GPSR(IP11_3_0, SD2_WP),
1408	PINMUX_IPSR_GPSR(IP11_3_0, MMC0_D5),
1409	PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
1410	PINMUX_IPSR_GPSR(IP11_3_0, USB2_IDIN),
1411	PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1, SEL_GPS_0),
1412	PINMUX_IPSR_MSEL(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
1413	PINMUX_IPSR_MSEL(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
1414	PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
1415	PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1_B, SEL_GPS_1),
1416	PINMUX_IPSR_MSEL(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
1417	PINMUX_IPSR_GPSR(IP11_4, SD3_CLK),
1418	PINMUX_IPSR_GPSR(IP11_4, MMC1_CLK),
1419	PINMUX_IPSR_GPSR(IP11_6_5, SD3_CMD),
1420	PINMUX_IPSR_GPSR(IP11_6_5, MMC1_CMD),
1421	PINMUX_IPSR_GPSR(IP11_6_5, MTS_N),
1422	PINMUX_IPSR_GPSR(IP11_8_7, SD3_DAT0),
1423	PINMUX_IPSR_GPSR(IP11_8_7, MMC1_D0),
1424	PINMUX_IPSR_GPSR(IP11_8_7, STM_N),
1425	PINMUX_IPSR_GPSR(IP11_10_9, SD3_DAT1),
1426	PINMUX_IPSR_GPSR(IP11_10_9, MMC1_D1),
1427	PINMUX_IPSR_GPSR(IP11_10_9, MDATA),
1428	PINMUX_IPSR_GPSR(IP11_12_11, SD3_DAT2),
1429	PINMUX_IPSR_GPSR(IP11_12_11, MMC1_D2),
1430	PINMUX_IPSR_GPSR(IP11_12_11, SDATA),
1431	PINMUX_IPSR_GPSR(IP11_14_13, SD3_DAT3),
1432	PINMUX_IPSR_GPSR(IP11_14_13, MMC1_D3),
1433	PINMUX_IPSR_GPSR(IP11_14_13, SCKZ),
1434	PINMUX_IPSR_GPSR(IP11_17_15, SD3_CD),
1435	PINMUX_IPSR_GPSR(IP11_17_15, MMC1_D4),
1436	PINMUX_IPSR_MSEL(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
1437	PINMUX_IPSR_GPSR(IP11_17_15, VSP),
1438	PINMUX_IPSR_MSEL(IP11_17_15, GLO_Q0, SEL_GPS_0),
1439	PINMUX_IPSR_MSEL(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
1440	PINMUX_IPSR_GPSR(IP11_21_18, SD3_WP),
1441	PINMUX_IPSR_GPSR(IP11_21_18, MMC1_D5),
1442	PINMUX_IPSR_MSEL(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
1443	PINMUX_IPSR_MSEL(IP11_21_18, GLO_Q1, SEL_GPS_0),
1444	PINMUX_IPSR_MSEL(IP11_21_18, FMIN_C, SEL_FM_2),
1445	PINMUX_IPSR_MSEL(IP11_21_18, FMIN_E, SEL_FM_4),
1446	PINMUX_IPSR_MSEL(IP11_21_18, FMIN_F, SEL_FM_5),
1447	PINMUX_IPSR_GPSR(IP11_23_22, MLB_CLK),
1448	PINMUX_IPSR_MSEL(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1),
1449	PINMUX_IPSR_MSEL(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1),
1450	PINMUX_IPSR_GPSR(IP11_26_24, MLB_SIG),
1451	PINMUX_IPSR_MSEL(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
1452	PINMUX_IPSR_MSEL(IP11_26_24, RX1_C, SEL_SCIF1_2),
1453	PINMUX_IPSR_MSEL(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1),
1454	PINMUX_IPSR_MSEL(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1),
1455	PINMUX_IPSR_GPSR(IP11_29_27, MLB_DAT),
1456	PINMUX_IPSR_MSEL(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
1457	PINMUX_IPSR_MSEL(IP11_29_27, TX1_C, SEL_SCIF1_2),
1458	PINMUX_IPSR_MSEL(IP11_29_27, BPFCLK_C, SEL_FM_2),
1459	PINMUX_IPSR_GPSR(IP11_31_30, SSI_SCK0129),
1460	PINMUX_IPSR_MSEL(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
1461	PINMUX_IPSR_GPSR(IP11_31_30, MOUT0),
1462
1463	PINMUX_IPSR_GPSR(IP12_1_0, SSI_WS0129),
1464	PINMUX_IPSR_MSEL(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
1465	PINMUX_IPSR_GPSR(IP12_1_0, MOUT1),
1466	PINMUX_IPSR_GPSR(IP12_3_2, SSI_SDATA0),
1467	PINMUX_IPSR_MSEL(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
1468	PINMUX_IPSR_GPSR(IP12_3_2, MOUT2),
1469	PINMUX_IPSR_GPSR(IP12_5_4, SSI_SDATA1),
1470	PINMUX_IPSR_MSEL(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
1471	PINMUX_IPSR_GPSR(IP12_5_4, MOUT5),
1472	PINMUX_IPSR_GPSR(IP12_7_6, SSI_SDATA2),
1473	PINMUX_IPSR_MSEL(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
1474	PINMUX_IPSR_GPSR(IP12_7_6, SSI_SCK1),
1475	PINMUX_IPSR_GPSR(IP12_7_6, MOUT6),
1476	PINMUX_IPSR_GPSR(IP12_10_8, SSI_SCK34),
1477	PINMUX_IPSR_GPSR(IP12_10_8, STP_OPWM_0),
1478	PINMUX_IPSR_MSEL(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
1479	PINMUX_IPSR_MSEL(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
1480	PINMUX_IPSR_GPSR(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
1481	PINMUX_IPSR_GPSR(IP12_13_11, SSI_WS34),
1482	PINMUX_IPSR_MSEL(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
1483	PINMUX_IPSR_MSEL(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
1484	PINMUX_IPSR_GPSR(IP12_13_11, MSIOF1_SYNC),
1485	PINMUX_IPSR_GPSR(IP12_13_11, CAN_STEP0),
1486	PINMUX_IPSR_GPSR(IP12_16_14, SSI_SDATA3),
1487	PINMUX_IPSR_MSEL(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
1488	PINMUX_IPSR_MSEL(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
1489	PINMUX_IPSR_MSEL(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
1490	PINMUX_IPSR_GPSR(IP12_16_14, CAN_TXCLK),
1491	PINMUX_IPSR_GPSR(IP12_19_17, SSI_SCK4),
1492	PINMUX_IPSR_MSEL(IP12_19_17, STP_ISD_0, SEL_SSP_0),
1493	PINMUX_IPSR_MSEL(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
1494	PINMUX_IPSR_MSEL(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
1495	PINMUX_IPSR_MSEL(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
1496	PINMUX_IPSR_GPSR(IP12_19_17, CAN_DEBUGOUT0),
1497	PINMUX_IPSR_GPSR(IP12_22_20, SSI_WS4),
1498	PINMUX_IPSR_MSEL(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
1499	PINMUX_IPSR_MSEL(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
1500	PINMUX_IPSR_MSEL(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
1501	PINMUX_IPSR_MSEL(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
1502	PINMUX_IPSR_GPSR(IP12_22_20, CAN_DEBUGOUT1),
1503	PINMUX_IPSR_GPSR(IP12_24_23, SSI_SDATA4),
1504	PINMUX_IPSR_MSEL(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
1505	PINMUX_IPSR_MSEL(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
1506	PINMUX_IPSR_GPSR(IP12_24_23, CAN_DEBUGOUT2),
1507	PINMUX_IPSR_MSEL(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
1508	PINMUX_IPSR_MSEL(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
1509	PINMUX_IPSR_MSEL(IP12_27_25, IERX_B, SEL_IEB_1),
1510	PINMUX_IPSR_GPSR(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
1511	PINMUX_IPSR_GPSR(IP12_27_25, QSTH_QHS),
1512	PINMUX_IPSR_GPSR(IP12_27_25, CAN_DEBUGOUT3),
1513	PINMUX_IPSR_MSEL(IP12_30_28, SSI_WS5, SEL_SSI5_0),
1514	PINMUX_IPSR_MSEL(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
1515	PINMUX_IPSR_MSEL(IP12_30_28, IECLK_B, SEL_IEB_1),
1516	PINMUX_IPSR_GPSR(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
1517	PINMUX_IPSR_GPSR(IP12_30_28, QSTB_QHE),
1518	PINMUX_IPSR_GPSR(IP12_30_28, CAN_DEBUGOUT4),
1519
1520	PINMUX_IPSR_MSEL(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
1521	PINMUX_IPSR_MSEL(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
1522	PINMUX_IPSR_MSEL(IP13_2_0, IETX_B, SEL_IEB_1),
1523	PINMUX_IPSR_GPSR(IP13_2_0, DU2_DR2),
1524	PINMUX_IPSR_GPSR(IP13_2_0, LCDOUT2),
1525	PINMUX_IPSR_GPSR(IP13_2_0, CAN_DEBUGOUT5),
1526	PINMUX_IPSR_MSEL(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
1527	PINMUX_IPSR_MSEL(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
1528	PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_D, SEL_FM_3),
1529	PINMUX_IPSR_GPSR(IP13_6_3, DU2_DR3),
1530	PINMUX_IPSR_GPSR(IP13_6_3, LCDOUT3),
1531	PINMUX_IPSR_GPSR(IP13_6_3, CAN_DEBUGOUT6),
1532	PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_F, SEL_FM_5),
1533	PINMUX_IPSR_MSEL(IP13_9_7, SSI_WS6, SEL_SSI6_0),
1534	PINMUX_IPSR_MSEL(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
1535	PINMUX_IPSR_MSEL(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
1536	PINMUX_IPSR_GPSR(IP13_9_7, DU2_DR4),
1537	PINMUX_IPSR_GPSR(IP13_9_7, LCDOUT4),
1538	PINMUX_IPSR_GPSR(IP13_9_7, CAN_DEBUGOUT7),
1539	PINMUX_IPSR_MSEL(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
1540	PINMUX_IPSR_MSEL(IP13_12_10, FMIN_D, SEL_FM_3),
1541	PINMUX_IPSR_GPSR(IP13_12_10, DU2_DR5),
1542	PINMUX_IPSR_GPSR(IP13_12_10, LCDOUT5),
1543	PINMUX_IPSR_GPSR(IP13_12_10, CAN_DEBUGOUT8),
1544	PINMUX_IPSR_MSEL(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
1545	PINMUX_IPSR_MSEL(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
1546	PINMUX_IPSR_MSEL(IP13_15_13, SCK1, SEL_SCIF1_0),
1547	PINMUX_IPSR_MSEL(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
1548	PINMUX_IPSR_GPSR(IP13_15_13, DU2_DR6),
1549	PINMUX_IPSR_GPSR(IP13_15_13, LCDOUT6),
1550	PINMUX_IPSR_GPSR(IP13_15_13, CAN_DEBUGOUT9),
1551	PINMUX_IPSR_MSEL(IP13_18_16, SSI_WS78, SEL_SSI7_0),
1552	PINMUX_IPSR_MSEL(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
1553	PINMUX_IPSR_MSEL(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
1554	PINMUX_IPSR_GPSR(IP13_18_16, SCIFA2_CTS_N),
1555	PINMUX_IPSR_GPSR(IP13_18_16, DU2_DR7),
1556	PINMUX_IPSR_GPSR(IP13_18_16, LCDOUT7),
1557	PINMUX_IPSR_GPSR(IP13_18_16, CAN_DEBUGOUT10),
1558	PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
1559	PINMUX_IPSR_MSEL(IP13_22_19, STP_ISD_1, SEL_SSP_0),
1560	PINMUX_IPSR_MSEL(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
1561	PINMUX_IPSR_GPSR(IP13_22_19, SCIFA2_RTS_N),
1562	PINMUX_IPSR_GPSR(IP13_22_19, TCLK2),
1563	PINMUX_IPSR_GPSR(IP13_22_19, QSTVA_QVS),
1564	PINMUX_IPSR_GPSR(IP13_22_19, CAN_DEBUGOUT11),
1565	PINMUX_IPSR_MSEL(IP13_22_19, BPFCLK_E, SEL_FM_4),
1566	PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
1567	PINMUX_IPSR_MSEL(IP13_22_19, FMIN_G, SEL_FM_6),
1568	PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
1569	PINMUX_IPSR_MSEL(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
1570	PINMUX_IPSR_MSEL(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
1571	PINMUX_IPSR_MSEL(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
1572	PINMUX_IPSR_GPSR(IP13_25_23, CAN_DEBUGOUT12),
1573	PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
1574	PINMUX_IPSR_GPSR(IP13_28_26, SSI_SDATA9),
1575	PINMUX_IPSR_MSEL(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
1576	PINMUX_IPSR_MSEL(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
1577	PINMUX_IPSR_GPSR(IP13_28_26, SSI_WS1),
1578	PINMUX_IPSR_MSEL(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
1579	PINMUX_IPSR_GPSR(IP13_28_26, CAN_DEBUGOUT13),
1580	PINMUX_IPSR_GPSR(IP13_30_29, AUDIO_CLKA),
1581	PINMUX_IPSR_MSEL(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
1582	PINMUX_IPSR_GPSR(IP13_30_29, CAN_DEBUGOUT14),
1583
1584	PINMUX_IPSR_GPSR(IP14_2_0, AUDIO_CLKB),
1585	PINMUX_IPSR_MSEL(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
1586	PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
1587	PINMUX_IPSR_GPSR(IP14_2_0, DVC_MUTE),
1588	PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
1589	PINMUX_IPSR_GPSR(IP14_2_0, CAN_DEBUGOUT15),
1590	PINMUX_IPSR_GPSR(IP14_2_0, REMOCON),
1591	PINMUX_IPSR_MSEL(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
1592	PINMUX_IPSR_MSEL(IP14_5_3, HSCK1, SEL_HSCIF1_0),
1593	PINMUX_IPSR_GPSR(IP14_5_3, SCK0),
1594	PINMUX_IPSR_GPSR(IP14_5_3, MSIOF3_SS2),
1595	PINMUX_IPSR_GPSR(IP14_5_3, DU2_DG2),
1596	PINMUX_IPSR_GPSR(IP14_5_3, LCDOUT10),
1597	PINMUX_IPSR_MSEL(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2),
1598	PINMUX_IPSR_MSEL(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2),
1599	PINMUX_IPSR_MSEL(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
1600	PINMUX_IPSR_MSEL(IP14_8_6, HRX1, SEL_HSCIF1_0),
1601	PINMUX_IPSR_MSEL(IP14_8_6, RX0, SEL_SCIF0_0),
1602	PINMUX_IPSR_GPSR(IP14_8_6, DU2_DR0),
1603	PINMUX_IPSR_GPSR(IP14_8_6, LCDOUT0),
1604	PINMUX_IPSR_MSEL(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
1605	PINMUX_IPSR_MSEL(IP14_11_9, HTX1, SEL_HSCIF1_0),
1606	PINMUX_IPSR_MSEL(IP14_11_9, TX0, SEL_SCIF0_0),
1607	PINMUX_IPSR_GPSR(IP14_11_9, DU2_DR1),
1608	PINMUX_IPSR_GPSR(IP14_11_9, LCDOUT1),
1609	PINMUX_IPSR_MSEL(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
1610	PINMUX_IPSR_MSEL(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
1611	PINMUX_IPSR_GPSR(IP14_15_12, CTS0_N),
1612	PINMUX_IPSR_MSEL(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
1613	PINMUX_IPSR_GPSR(IP14_15_12, DU2_DG3),
1614	PINMUX_IPSR_GPSR(IP14_15_12, LCDOUT11),
1615	PINMUX_IPSR_GPSR(IP14_15_12, PWM0_B),
1616	PINMUX_IPSR_MSEL(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2),
1617	PINMUX_IPSR_MSEL(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2),
1618	PINMUX_IPSR_MSEL(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
1619	PINMUX_IPSR_MSEL(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
1620	PINMUX_IPSR_GPSR(IP14_18_16, RTS0_N),
1621	PINMUX_IPSR_GPSR(IP14_18_16, MSIOF3_SS1),
1622	PINMUX_IPSR_GPSR(IP14_18_16, DU2_DG0),
1623	PINMUX_IPSR_GPSR(IP14_18_16, LCDOUT8),
1624	PINMUX_IPSR_GPSR(IP14_18_16, PWM1_B),
1625	PINMUX_IPSR_MSEL(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
1626	PINMUX_IPSR_MSEL(IP14_21_19, AD_DI, SEL_ADI_0),
1627	PINMUX_IPSR_MSEL(IP14_21_19, RX1, SEL_SCIF1_0),
1628	PINMUX_IPSR_GPSR(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
1629	PINMUX_IPSR_GPSR(IP14_21_19, QCPV_QDE),
1630	PINMUX_IPSR_MSEL(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
1631	PINMUX_IPSR_MSEL(IP14_24_22, AD_DO, SEL_ADI_0),
1632	PINMUX_IPSR_MSEL(IP14_24_22, TX1, SEL_SCIF1_0),
1633	PINMUX_IPSR_GPSR(IP14_24_22, DU2_DG1),
1634	PINMUX_IPSR_GPSR(IP14_24_22, LCDOUT9),
1635	PINMUX_IPSR_MSEL(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
1636	PINMUX_IPSR_MSEL(IP14_27_25, AD_CLK, SEL_ADI_0),
1637	PINMUX_IPSR_GPSR(IP14_27_25, CTS1_N),
1638	PINMUX_IPSR_MSEL(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
1639	PINMUX_IPSR_GPSR(IP14_27_25, DU0_DOTCLKOUT),
1640	PINMUX_IPSR_GPSR(IP14_27_25, QCLK),
1641	PINMUX_IPSR_MSEL(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
1642	PINMUX_IPSR_MSEL(IP14_30_28, AD_NCS_N, SEL_ADI_0),
1643	PINMUX_IPSR_GPSR(IP14_30_28, RTS1_N),
1644	PINMUX_IPSR_MSEL(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
1645	PINMUX_IPSR_GPSR(IP14_30_28, DU1_DOTCLKOUT),
1646	PINMUX_IPSR_GPSR(IP14_30_28, QSTVB_QVE),
1647	PINMUX_IPSR_MSEL(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
1648
1649	PINMUX_IPSR_MSEL(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
1650	PINMUX_IPSR_MSEL(IP15_2_0, FMCLK, SEL_FM_0),
1651	PINMUX_IPSR_GPSR(IP15_2_0, SCK2),
1652	PINMUX_IPSR_MSEL(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
1653	PINMUX_IPSR_GPSR(IP15_2_0, DU2_DG7),
1654	PINMUX_IPSR_GPSR(IP15_2_0, LCDOUT15),
1655	PINMUX_IPSR_MSEL(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1),
1656	PINMUX_IPSR_MSEL(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1657	PINMUX_IPSR_MSEL(IP15_5_3, FMIN, SEL_FM_0),
1658	PINMUX_IPSR_MSEL(IP15_5_3, TX2, SEL_SCIF2_0),
1659	PINMUX_IPSR_GPSR(IP15_5_3, DU2_DB0),
1660	PINMUX_IPSR_GPSR(IP15_5_3, LCDOUT16),
1661	PINMUX_IPSR_MSEL(IP15_5_3, IIC2_SCL, SEL_IIC2_0),
1662	PINMUX_IPSR_MSEL(IP15_5_3, I2C2_SCL, SEL_I2C2_0),
1663	PINMUX_IPSR_MSEL(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
1664	PINMUX_IPSR_MSEL(IP15_8_6, BPFCLK, SEL_FM_0),
1665	PINMUX_IPSR_MSEL(IP15_8_6, RX2, SEL_SCIF2_0),
1666	PINMUX_IPSR_GPSR(IP15_8_6, DU2_DB1),
1667	PINMUX_IPSR_GPSR(IP15_8_6, LCDOUT17),
1668	PINMUX_IPSR_MSEL(IP15_8_6, IIC2_SDA, SEL_IIC2_0),
1669	PINMUX_IPSR_MSEL(IP15_8_6, I2C2_SDA, SEL_I2C2_0),
1670	PINMUX_IPSR_GPSR(IP15_11_9, HSCK0),
1671	PINMUX_IPSR_MSEL(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
1672	PINMUX_IPSR_GPSR(IP15_11_9, DU2_DG4),
1673	PINMUX_IPSR_GPSR(IP15_11_9, LCDOUT12),
1674	PINMUX_IPSR_MSEL(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2),
1675	PINMUX_IPSR_MSEL(IP15_13_12, HRX0, SEL_HSCIF0_0),
1676	PINMUX_IPSR_GPSR(IP15_13_12, DU2_DB2),
1677	PINMUX_IPSR_GPSR(IP15_13_12, LCDOUT18),
1678	PINMUX_IPSR_MSEL(IP15_15_14, HTX0, SEL_HSCIF0_0),
1679	PINMUX_IPSR_GPSR(IP15_15_14, DU2_DB3),
1680	PINMUX_IPSR_GPSR(IP15_15_14, LCDOUT19),
1681	PINMUX_IPSR_MSEL(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
1682	PINMUX_IPSR_GPSR(IP15_17_16, SSI_SCK9),
1683	PINMUX_IPSR_GPSR(IP15_17_16, DU2_DB4),
1684	PINMUX_IPSR_GPSR(IP15_17_16, LCDOUT20),
1685	PINMUX_IPSR_MSEL(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
1686	PINMUX_IPSR_GPSR(IP15_19_18, SSI_WS9),
1687	PINMUX_IPSR_GPSR(IP15_19_18, DU2_DB5),
1688	PINMUX_IPSR_GPSR(IP15_19_18, LCDOUT21),
1689	PINMUX_IPSR_MSEL(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
1690	PINMUX_IPSR_MSEL(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
1691	PINMUX_IPSR_GPSR(IP15_22_20, ADICLK),
1692	PINMUX_IPSR_GPSR(IP15_22_20, DU2_DB6),
1693	PINMUX_IPSR_GPSR(IP15_22_20, LCDOUT22),
1694	PINMUX_IPSR_GPSR(IP15_25_23, MSIOF0_SYNC),
1695	PINMUX_IPSR_MSEL(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
1696	PINMUX_IPSR_GPSR(IP15_25_23, SSI_SCK2),
1697	PINMUX_IPSR_GPSR(IP15_25_23, ADIDATA),
1698	PINMUX_IPSR_GPSR(IP15_25_23, DU2_DB7),
1699	PINMUX_IPSR_GPSR(IP15_25_23, LCDOUT23),
1700	PINMUX_IPSR_MSEL(IP15_25_23, HRX0_C, SEL_SCIFA2_1),
1701	PINMUX_IPSR_MSEL(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
1702	PINMUX_IPSR_GPSR(IP15_27_26, ADICHS0),
1703	PINMUX_IPSR_GPSR(IP15_27_26, DU2_DG5),
1704	PINMUX_IPSR_GPSR(IP15_27_26, LCDOUT13),
1705	PINMUX_IPSR_MSEL(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
1706	PINMUX_IPSR_GPSR(IP15_29_28, ADICHS1),
1707	PINMUX_IPSR_GPSR(IP15_29_28, DU2_DG6),
1708	PINMUX_IPSR_GPSR(IP15_29_28, LCDOUT14),
1709
1710	PINMUX_IPSR_MSEL(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
1711	PINMUX_IPSR_GPSR(IP16_2_0, AUDIO_CLKOUT),
1712	PINMUX_IPSR_GPSR(IP16_2_0, ADICHS2),
1713	PINMUX_IPSR_GPSR(IP16_2_0, DU2_DISP),
1714	PINMUX_IPSR_GPSR(IP16_2_0, QPOLA),
1715	PINMUX_IPSR_MSEL(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
1716	PINMUX_IPSR_MSEL(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
1717	PINMUX_IPSR_MSEL(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
1718	PINMUX_IPSR_MSEL(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
1719	PINMUX_IPSR_GPSR(IP16_5_3, SSI_WS2),
1720	PINMUX_IPSR_GPSR(IP16_5_3, ADICS_SAMP),
1721	PINMUX_IPSR_GPSR(IP16_5_3, DU2_CDE),
1722	PINMUX_IPSR_GPSR(IP16_5_3, QPOLB),
1723	PINMUX_IPSR_MSEL(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2),
1724	PINMUX_IPSR_GPSR(IP16_6, USB1_PWEN),
1725	PINMUX_IPSR_GPSR(IP16_6, AUDIO_CLKOUT_D),
1726	PINMUX_IPSR_GPSR(IP16_7, USB1_OVC),
1727	PINMUX_IPSR_MSEL(IP16_7, TCLK1_B, SEL_TMU1_1),
1728
1729	PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0),
1730	PINMUX_DATA(IIC0_SDA_MARK, FN_SEL_IIC0_0),
1731	PINMUX_DATA(I2C0_SCL_MARK, FN_SEL_IIC0_1),
1732	PINMUX_DATA(I2C0_SDA_MARK, FN_SEL_IIC0_1),
1733
1734	PINMUX_DATA(IIC3_SCL_MARK, FN_SEL_IICDVFS_0),
1735	PINMUX_DATA(IIC3_SDA_MARK, FN_SEL_IICDVFS_0),
1736	PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1),
1737	PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1),
1738};
1739
1740/* R8A7790 has 6 banks with 32 GPIOs in each = 192 GPIOs */
1741#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1742#define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200)
1743#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1744
1745static const struct sh_pfc_pin pinmux_pins[] = {
1746	PINMUX_GPIO_GP_ALL(),
1747
1748	/* Pins not associated with a GPIO port */
1749	SH_PFC_PIN_NAMED(ROW_GROUP_A('F'), 15, AF15),
1750	SH_PFC_PIN_NAMED(ROW_GROUP_A('G'), 15, AG15),
1751	SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15),
1752	SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15),
1753};
1754
1755/* - AUDIO CLOCK ------------------------------------------------------------ */
1756static const unsigned int audio_clk_a_pins[] = {
1757	/* CLK A */
1758	RCAR_GP_PIN(4, 25),
1759};
1760static const unsigned int audio_clk_a_mux[] = {
1761	AUDIO_CLKA_MARK,
1762};
1763static const unsigned int audio_clk_b_pins[] = {
1764	/* CLK B */
1765	RCAR_GP_PIN(4, 26),
1766};
1767static const unsigned int audio_clk_b_mux[] = {
1768	AUDIO_CLKB_MARK,
1769};
1770static const unsigned int audio_clk_c_pins[] = {
1771	/* CLK C */
1772	RCAR_GP_PIN(5, 27),
1773};
1774static const unsigned int audio_clk_c_mux[] = {
1775	AUDIO_CLKC_MARK,
1776};
1777static const unsigned int audio_clkout_pins[] = {
1778	/* CLK OUT */
1779	RCAR_GP_PIN(5, 16),
1780};
1781static const unsigned int audio_clkout_mux[] = {
1782	AUDIO_CLKOUT_MARK,
1783};
1784static const unsigned int audio_clkout_b_pins[] = {
1785	/* CLK OUT B */
1786	RCAR_GP_PIN(0, 23),
1787};
1788static const unsigned int audio_clkout_b_mux[] = {
1789	AUDIO_CLKOUT_B_MARK,
1790};
1791static const unsigned int audio_clkout_c_pins[] = {
1792	/* CLK OUT C */
1793	RCAR_GP_PIN(5, 27),
1794};
1795static const unsigned int audio_clkout_c_mux[] = {
1796	AUDIO_CLKOUT_C_MARK,
1797};
1798static const unsigned int audio_clkout_d_pins[] = {
1799	/* CLK OUT D */
1800	RCAR_GP_PIN(5, 20),
1801};
1802static const unsigned int audio_clkout_d_mux[] = {
1803	AUDIO_CLKOUT_D_MARK,
1804};
1805/* - AVB -------------------------------------------------------------------- */
1806static const unsigned int avb_link_pins[] = {
1807	RCAR_GP_PIN(3, 11),
1808};
1809static const unsigned int avb_link_mux[] = {
1810	AVB_LINK_MARK,
1811};
1812static const unsigned int avb_magic_pins[] = {
1813	RCAR_GP_PIN(2, 14),
1814};
1815static const unsigned int avb_magic_mux[] = {
1816	AVB_MAGIC_MARK,
1817};
1818static const unsigned int avb_phy_int_pins[] = {
1819	RCAR_GP_PIN(2, 15),
1820};
1821static const unsigned int avb_phy_int_mux[] = {
1822	AVB_PHY_INT_MARK,
1823};
1824static const unsigned int avb_mdio_pins[] = {
1825	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1826};
1827static const unsigned int avb_mdio_mux[] = {
1828	AVB_MDC_MARK, AVB_MDIO_MARK,
1829};
1830static const unsigned int avb_mii_pins[] = {
1831	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1832	RCAR_GP_PIN(0, 11),
1833
1834	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1835	RCAR_GP_PIN(2, 2),
1836
1837	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1838	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 10),
1839	RCAR_GP_PIN(3, 12),
1840};
1841static const unsigned int avb_mii_mux[] = {
1842	AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1843	AVB_TXD3_MARK,
1844
1845	AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1846	AVB_RXD3_MARK,
1847
1848	AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1849	AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_CLK_MARK,
1850	AVB_COL_MARK,
1851};
1852static const unsigned int avb_gmii_pins[] = {
1853	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1854	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1855	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
1856
1857	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1858	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
1859	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
1860
1861	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1862	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 16),
1863	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
1864	RCAR_GP_PIN(3, 12),
1865};
1866static const unsigned int avb_gmii_mux[] = {
1867	AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1868	AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1869	AVB_TXD6_MARK, AVB_TXD7_MARK,
1870
1871	AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1872	AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1873	AVB_RXD6_MARK, AVB_RXD7_MARK,
1874
1875	AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1876	AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1877	AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1878	AVB_COL_MARK,
1879};
1880/* - DU RGB ----------------------------------------------------------------- */
1881static const unsigned int du_rgb666_pins[] = {
1882	/* R[7:2], G[7:2], B[7:2] */
1883	RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1884	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1885	RCAR_GP_PIN(5, 4),  RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
1886	RCAR_GP_PIN(5, 7),  RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
1887	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
1888	RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9),  RCAR_GP_PIN(5, 8),
1889};
1890static const unsigned int du_rgb666_mux[] = {
1891	DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
1892	DU2_DR3_MARK, DU2_DR2_MARK,
1893	DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
1894	DU2_DG3_MARK, DU2_DG2_MARK,
1895	DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
1896	DU2_DB3_MARK, DU2_DB2_MARK,
1897};
1898static const unsigned int du_rgb888_pins[] = {
1899	/* R[7:0], G[7:0], B[7:0] */
1900	RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1901	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1902	RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4),
1903	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7),
1904	RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1),
1905	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12),
1906	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9),
1907	RCAR_GP_PIN(5, 8),  RCAR_GP_PIN(5, 6),  RCAR_GP_PIN(5, 5),
1908};
1909static const unsigned int du_rgb888_mux[] = {
1910	DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
1911	DU2_DR3_MARK, DU2_DR2_MARK, DU2_DR1_MARK, DU2_DR0_MARK,
1912	DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
1913	DU2_DG3_MARK, DU2_DG2_MARK, DU2_DG1_MARK, DU2_DG0_MARK,
1914	DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
1915	DU2_DB3_MARK, DU2_DB2_MARK, DU2_DB1_MARK, DU2_DB0_MARK,
1916};
1917static const unsigned int du_clk_out_0_pins[] = {
1918	/* CLKOUT */
1919	RCAR_GP_PIN(5, 2),
1920};
1921static const unsigned int du_clk_out_0_mux[] = {
1922	DU0_DOTCLKOUT_MARK
1923};
1924static const unsigned int du_clk_out_1_pins[] = {
1925	/* CLKOUT */
1926	RCAR_GP_PIN(5, 3),
1927};
1928static const unsigned int du_clk_out_1_mux[] = {
1929	DU1_DOTCLKOUT_MARK
1930};
1931static const unsigned int du_sync_0_pins[] = {
1932	/* VSYNC, HSYNC, DISP */
1933	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0),
1934};
1935static const unsigned int du_sync_0_mux[] = {
1936	DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
1937	DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK
1938};
1939static const unsigned int du_sync_1_pins[] = {
1940	/* VSYNC, HSYNC, DISP */
1941	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16),
1942};
1943static const unsigned int du_sync_1_mux[] = {
1944	DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
1945	DU2_DISP_MARK
1946};
1947static const unsigned int du_cde_pins[] = {
1948	/* CDE */
1949	RCAR_GP_PIN(5, 17),
1950};
1951static const unsigned int du_cde_mux[] = {
1952	DU2_CDE_MARK,
1953};
1954/* - DU0 -------------------------------------------------------------------- */
1955static const unsigned int du0_clk_in_pins[] = {
1956	/* CLKIN */
1957	RCAR_GP_PIN(5, 26),
1958};
1959static const unsigned int du0_clk_in_mux[] = {
1960	DU_DOTCLKIN0_MARK
1961};
1962/* - DU1 -------------------------------------------------------------------- */
1963static const unsigned int du1_clk_in_pins[] = {
1964	/* CLKIN */
1965	RCAR_GP_PIN(5, 27),
1966};
1967static const unsigned int du1_clk_in_mux[] = {
1968	DU_DOTCLKIN1_MARK,
1969};
1970/* - DU2 -------------------------------------------------------------------- */
1971static const unsigned int du2_clk_in_pins[] = {
1972	/* CLKIN */
1973	RCAR_GP_PIN(5, 28),
1974};
1975static const unsigned int du2_clk_in_mux[] = {
1976	DU_DOTCLKIN2_MARK,
1977};
1978/* - ETH -------------------------------------------------------------------- */
1979static const unsigned int eth_link_pins[] = {
1980	/* LINK */
1981	RCAR_GP_PIN(2, 22),
1982};
1983static const unsigned int eth_link_mux[] = {
1984	ETH_LINK_MARK,
1985};
1986static const unsigned int eth_magic_pins[] = {
1987	/* MAGIC */
1988	RCAR_GP_PIN(2, 27),
1989};
1990static const unsigned int eth_magic_mux[] = {
1991	ETH_MAGIC_MARK,
1992};
1993static const unsigned int eth_mdio_pins[] = {
1994	/* MDC, MDIO */
1995	RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
1996};
1997static const unsigned int eth_mdio_mux[] = {
1998	ETH_MDC_MARK, ETH_MDIO_MARK,
1999};
2000static const unsigned int eth_rmii_pins[] = {
2001	/* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
2002	RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
2003	RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
2004	RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
2005};
2006static const unsigned int eth_rmii_mux[] = {
2007	ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
2008	ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
2009};
2010/* - HSCIF0 ----------------------------------------------------------------- */
2011static const unsigned int hscif0_data_pins[] = {
2012	/* RX, TX */
2013	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
2014};
2015static const unsigned int hscif0_data_mux[] = {
2016	HRX0_MARK, HTX0_MARK,
2017};
2018static const unsigned int hscif0_clk_pins[] = {
2019	/* SCK */
2020	RCAR_GP_PIN(5, 7),
2021};
2022static const unsigned int hscif0_clk_mux[] = {
2023	HSCK0_MARK,
2024};
2025static const unsigned int hscif0_ctrl_pins[] = {
2026	/* RTS, CTS */
2027	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2028};
2029static const unsigned int hscif0_ctrl_mux[] = {
2030	HRTS0_N_MARK, HCTS0_N_MARK,
2031};
2032static const unsigned int hscif0_data_b_pins[] = {
2033	/* RX, TX */
2034	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12),
2035};
2036static const unsigned int hscif0_data_b_mux[] = {
2037	HRX0_B_MARK, HTX0_B_MARK,
2038};
2039static const unsigned int hscif0_ctrl_b_pins[] = {
2040	/* RTS, CTS */
2041	RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28),
2042};
2043static const unsigned int hscif0_ctrl_b_mux[] = {
2044	HRTS0_N_B_MARK, HCTS0_N_B_MARK,
2045};
2046static const unsigned int hscif0_data_c_pins[] = {
2047	/* RX, TX */
2048	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
2049};
2050static const unsigned int hscif0_data_c_mux[] = {
2051	HRX0_C_MARK, HTX0_C_MARK,
2052};
2053static const unsigned int hscif0_ctrl_c_pins[] = {
2054	/* RTS, CTS */
2055	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7),
2056};
2057static const unsigned int hscif0_ctrl_c_mux[] = {
2058	HRTS0_N_C_MARK, HCTS0_N_C_MARK,
2059};
2060static const unsigned int hscif0_data_d_pins[] = {
2061	/* RX, TX */
2062	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2063};
2064static const unsigned int hscif0_data_d_mux[] = {
2065	HRX0_D_MARK, HTX0_D_MARK,
2066};
2067static const unsigned int hscif0_ctrl_d_pins[] = {
2068	/* RTS, CTS */
2069	RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22),
2070};
2071static const unsigned int hscif0_ctrl_d_mux[] = {
2072	HRTS0_N_D_MARK, HCTS0_N_D_MARK,
2073};
2074static const unsigned int hscif0_data_e_pins[] = {
2075	/* RX, TX */
2076	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2077};
2078static const unsigned int hscif0_data_e_mux[] = {
2079	HRX0_E_MARK, HTX0_E_MARK,
2080};
2081static const unsigned int hscif0_ctrl_e_pins[] = {
2082	/* RTS, CTS */
2083	RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
2084};
2085static const unsigned int hscif0_ctrl_e_mux[] = {
2086	HRTS0_N_E_MARK, HCTS0_N_E_MARK,
2087};
2088static const unsigned int hscif0_data_f_pins[] = {
2089	/* RX, TX */
2090	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25),
2091};
2092static const unsigned int hscif0_data_f_mux[] = {
2093	HRX0_F_MARK, HTX0_F_MARK,
2094};
2095static const unsigned int hscif0_ctrl_f_pins[] = {
2096	/* RTS, CTS */
2097	RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24),
2098};
2099static const unsigned int hscif0_ctrl_f_mux[] = {
2100	HRTS0_N_F_MARK, HCTS0_N_F_MARK,
2101};
2102/* - HSCIF1 ----------------------------------------------------------------- */
2103static const unsigned int hscif1_data_pins[] = {
2104	/* RX, TX */
2105	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2106};
2107static const unsigned int hscif1_data_mux[] = {
2108	HRX1_MARK, HTX1_MARK,
2109};
2110static const unsigned int hscif1_clk_pins[] = {
2111	/* SCK */
2112	RCAR_GP_PIN(4, 27),
2113};
2114static const unsigned int hscif1_clk_mux[] = {
2115	HSCK1_MARK,
2116};
2117static const unsigned int hscif1_ctrl_pins[] = {
2118	/* RTS, CTS */
2119	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2120};
2121static const unsigned int hscif1_ctrl_mux[] = {
2122	HRTS1_N_MARK, HCTS1_N_MARK,
2123};
2124static const unsigned int hscif1_data_b_pins[] = {
2125	/* RX, TX */
2126	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18),
2127};
2128static const unsigned int hscif1_data_b_mux[] = {
2129	HRX1_B_MARK, HTX1_B_MARK,
2130};
2131static const unsigned int hscif1_clk_b_pins[] = {
2132	/* SCK */
2133	RCAR_GP_PIN(1, 28),
2134};
2135static const unsigned int hscif1_clk_b_mux[] = {
2136	HSCK1_B_MARK,
2137};
2138static const unsigned int hscif1_ctrl_b_pins[] = {
2139	/* RTS, CTS */
2140	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2141};
2142static const unsigned int hscif1_ctrl_b_mux[] = {
2143	HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2144};
2145/* - I2C0 ------------------------------------------------------------------- */
2146static const unsigned int i2c0_pins[] = {
2147	/* SCL, SDA */
2148	PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
2149};
2150static const unsigned int i2c0_mux[] = {
2151	I2C0_SCL_MARK, I2C0_SDA_MARK,
2152};
2153/* - I2C1 ------------------------------------------------------------------- */
2154static const unsigned int i2c1_pins[] = {
2155	/* SCL, SDA */
2156	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2157};
2158static const unsigned int i2c1_mux[] = {
2159	I2C1_SCL_MARK, I2C1_SDA_MARK,
2160};
2161static const unsigned int i2c1_b_pins[] = {
2162	/* SCL, SDA */
2163	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2164};
2165static const unsigned int i2c1_b_mux[] = {
2166	I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2167};
2168static const unsigned int i2c1_c_pins[] = {
2169	/* SCL, SDA */
2170	RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2171};
2172static const unsigned int i2c1_c_mux[] = {
2173	I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2174};
2175/* - I2C2 ------------------------------------------------------------------- */
2176static const unsigned int i2c2_pins[] = {
2177	/* SCL, SDA */
2178	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2179};
2180static const unsigned int i2c2_mux[] = {
2181	I2C2_SCL_MARK, I2C2_SDA_MARK,
2182};
2183static const unsigned int i2c2_b_pins[] = {
2184	/* SCL, SDA */
2185	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2186};
2187static const unsigned int i2c2_b_mux[] = {
2188	I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2189};
2190static const unsigned int i2c2_c_pins[] = {
2191	/* SCL, SDA */
2192	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2193};
2194static const unsigned int i2c2_c_mux[] = {
2195	I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2196};
2197static const unsigned int i2c2_d_pins[] = {
2198	/* SCL, SDA */
2199	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2200};
2201static const unsigned int i2c2_d_mux[] = {
2202	I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2203};
2204static const unsigned int i2c2_e_pins[] = {
2205	/* SCL, SDA */
2206	RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2207};
2208static const unsigned int i2c2_e_mux[] = {
2209	I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
2210};
2211/* - I2C3 ------------------------------------------------------------------- */
2212static const unsigned int i2c3_pins[] = {
2213	/* SCL, SDA */
2214	PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
2215};
2216static const unsigned int i2c3_mux[] = {
2217	I2C3_SCL_MARK, I2C3_SDA_MARK,
2218};
2219/* - IIC0 (I2C4) ------------------------------------------------------------ */
2220static const unsigned int iic0_pins[] = {
2221	/* SCL, SDA */
2222	PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
2223};
2224static const unsigned int iic0_mux[] = {
2225	IIC0_SCL_MARK, IIC0_SDA_MARK,
2226};
2227/* - IIC1 (I2C5) ------------------------------------------------------------ */
2228static const unsigned int iic1_pins[] = {
2229	/* SCL, SDA */
2230	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2231};
2232static const unsigned int iic1_mux[] = {
2233	IIC1_SCL_MARK, IIC1_SDA_MARK,
2234};
2235static const unsigned int iic1_b_pins[] = {
2236	/* SCL, SDA */
2237	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2238};
2239static const unsigned int iic1_b_mux[] = {
2240	IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
2241};
2242static const unsigned int iic1_c_pins[] = {
2243	/* SCL, SDA */
2244	RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2245};
2246static const unsigned int iic1_c_mux[] = {
2247	IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
2248};
2249/* - IIC2 (I2C6) ------------------------------------------------------------ */
2250static const unsigned int iic2_pins[] = {
2251	/* SCL, SDA */
2252	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2253};
2254static const unsigned int iic2_mux[] = {
2255	IIC2_SCL_MARK, IIC2_SDA_MARK,
2256};
2257static const unsigned int iic2_b_pins[] = {
2258	/* SCL, SDA */
2259	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2260};
2261static const unsigned int iic2_b_mux[] = {
2262	IIC2_SCL_B_MARK, IIC2_SDA_B_MARK,
2263};
2264static const unsigned int iic2_c_pins[] = {
2265	/* SCL, SDA */
2266	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2267};
2268static const unsigned int iic2_c_mux[] = {
2269	IIC2_SCL_C_MARK, IIC2_SDA_C_MARK,
2270};
2271static const unsigned int iic2_d_pins[] = {
2272	/* SCL, SDA */
2273	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2274};
2275static const unsigned int iic2_d_mux[] = {
2276	IIC2_SCL_D_MARK, IIC2_SDA_D_MARK,
2277};
2278static const unsigned int iic2_e_pins[] = {
2279	/* SCL, SDA */
2280	RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2281};
2282static const unsigned int iic2_e_mux[] = {
2283	IIC2_SCL_E_MARK, IIC2_SDA_E_MARK,
2284};
2285/* - IIC3 (I2C7) ------------------------------------------------------------ */
2286static const unsigned int iic3_pins[] = {
2287/* SCL, SDA */
2288	PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
2289};
2290static const unsigned int iic3_mux[] = {
2291	IIC3_SCL_MARK, IIC3_SDA_MARK,
2292};
2293/* - INTC ------------------------------------------------------------------- */
2294static const unsigned int intc_irq0_pins[] = {
2295	/* IRQ */
2296	RCAR_GP_PIN(1, 25),
2297};
2298static const unsigned int intc_irq0_mux[] = {
2299	IRQ0_MARK,
2300};
2301static const unsigned int intc_irq1_pins[] = {
2302	/* IRQ */
2303	RCAR_GP_PIN(1, 27),
2304};
2305static const unsigned int intc_irq1_mux[] = {
2306	IRQ1_MARK,
2307};
2308static const unsigned int intc_irq2_pins[] = {
2309	/* IRQ */
2310	RCAR_GP_PIN(1, 29),
2311};
2312static const unsigned int intc_irq2_mux[] = {
2313	IRQ2_MARK,
2314};
2315static const unsigned int intc_irq3_pins[] = {
2316	/* IRQ */
2317	RCAR_GP_PIN(1, 23),
2318};
2319static const unsigned int intc_irq3_mux[] = {
2320	IRQ3_MARK,
2321};
2322/* - MLB+ ------------------------------------------------------------------- */
2323static const unsigned int mlb_3pin_pins[] = {
2324	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2325};
2326static const unsigned int mlb_3pin_mux[] = {
2327	MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2328};
2329/* - MMCIF0 ----------------------------------------------------------------- */
2330static const unsigned int mmc0_data1_pins[] = {
2331	/* D[0] */
2332	RCAR_GP_PIN(3, 18),
2333};
2334static const unsigned int mmc0_data1_mux[] = {
2335	MMC0_D0_MARK,
2336};
2337static const unsigned int mmc0_data4_pins[] = {
2338	/* D[0:3] */
2339	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2340	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2341};
2342static const unsigned int mmc0_data4_mux[] = {
2343	MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2344};
2345static const unsigned int mmc0_data8_pins[] = {
2346	/* D[0:7] */
2347	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2348	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2349	RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2350	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2351};
2352static const unsigned int mmc0_data8_mux[] = {
2353	MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2354	MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
2355};
2356static const unsigned int mmc0_ctrl_pins[] = {
2357	/* CLK, CMD */
2358	RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
2359};
2360static const unsigned int mmc0_ctrl_mux[] = {
2361	MMC0_CLK_MARK, MMC0_CMD_MARK,
2362};
2363/* - MMCIF1 ----------------------------------------------------------------- */
2364static const unsigned int mmc1_data1_pins[] = {
2365	/* D[0] */
2366	RCAR_GP_PIN(3, 26),
2367};
2368static const unsigned int mmc1_data1_mux[] = {
2369	MMC1_D0_MARK,
2370};
2371static const unsigned int mmc1_data4_pins[] = {
2372	/* D[0:3] */
2373	RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2374	RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2375};
2376static const unsigned int mmc1_data4_mux[] = {
2377	MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2378};
2379static const unsigned int mmc1_data8_pins[] = {
2380	/* D[0:7] */
2381	RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2382	RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2383	RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2384	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2385};
2386static const unsigned int mmc1_data8_mux[] = {
2387	MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2388	MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
2389};
2390static const unsigned int mmc1_ctrl_pins[] = {
2391	/* CLK, CMD */
2392	RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
2393};
2394static const unsigned int mmc1_ctrl_mux[] = {
2395	MMC1_CLK_MARK, MMC1_CMD_MARK,
2396};
2397/* - MSIOF0 ----------------------------------------------------------------- */
2398static const unsigned int msiof0_clk_pins[] = {
2399	/* SCK */
2400	RCAR_GP_PIN(5, 12),
2401};
2402static const unsigned int msiof0_clk_mux[] = {
2403	MSIOF0_SCK_MARK,
2404};
2405static const unsigned int msiof0_sync_pins[] = {
2406	/* SYNC */
2407	RCAR_GP_PIN(5, 13),
2408};
2409static const unsigned int msiof0_sync_mux[] = {
2410	MSIOF0_SYNC_MARK,
2411};
2412static const unsigned int msiof0_ss1_pins[] = {
2413	/* SS1 */
2414	RCAR_GP_PIN(5, 14),
2415};
2416static const unsigned int msiof0_ss1_mux[] = {
2417	MSIOF0_SS1_MARK,
2418};
2419static const unsigned int msiof0_ss2_pins[] = {
2420	/* SS2 */
2421	RCAR_GP_PIN(5, 16),
2422};
2423static const unsigned int msiof0_ss2_mux[] = {
2424	MSIOF0_SS2_MARK,
2425};
2426static const unsigned int msiof0_rx_pins[] = {
2427	/* RXD */
2428	RCAR_GP_PIN(5, 17),
2429};
2430static const unsigned int msiof0_rx_mux[] = {
2431	MSIOF0_RXD_MARK,
2432};
2433static const unsigned int msiof0_tx_pins[] = {
2434	/* TXD */
2435	RCAR_GP_PIN(5, 15),
2436};
2437static const unsigned int msiof0_tx_mux[] = {
2438	MSIOF0_TXD_MARK,
2439};
2440
2441static const unsigned int msiof0_clk_b_pins[] = {
2442	/* SCK */
2443	RCAR_GP_PIN(1, 23),
2444};
2445static const unsigned int msiof0_clk_b_mux[] = {
2446	MSIOF0_SCK_B_MARK,
2447};
2448static const unsigned int msiof0_ss1_b_pins[] = {
2449	/* SS1 */
2450	RCAR_GP_PIN(1, 12),
2451};
2452static const unsigned int msiof0_ss1_b_mux[] = {
2453	MSIOF0_SS1_B_MARK,
2454};
2455static const unsigned int msiof0_ss2_b_pins[] = {
2456	/* SS2 */
2457	RCAR_GP_PIN(1, 10),
2458};
2459static const unsigned int msiof0_ss2_b_mux[] = {
2460	MSIOF0_SS2_B_MARK,
2461};
2462static const unsigned int msiof0_rx_b_pins[] = {
2463	/* RXD */
2464	RCAR_GP_PIN(1, 29),
2465};
2466static const unsigned int msiof0_rx_b_mux[] = {
2467	MSIOF0_RXD_B_MARK,
2468};
2469static const unsigned int msiof0_tx_b_pins[] = {
2470	/* TXD */
2471	RCAR_GP_PIN(1, 28),
2472};
2473static const unsigned int msiof0_tx_b_mux[] = {
2474	MSIOF0_TXD_B_MARK,
2475};
2476/* - MSIOF1 ----------------------------------------------------------------- */
2477static const unsigned int msiof1_clk_pins[] = {
2478	/* SCK */
2479	RCAR_GP_PIN(4, 8),
2480};
2481static const unsigned int msiof1_clk_mux[] = {
2482	MSIOF1_SCK_MARK,
2483};
2484static const unsigned int msiof1_sync_pins[] = {
2485	/* SYNC */
2486	RCAR_GP_PIN(4, 9),
2487};
2488static const unsigned int msiof1_sync_mux[] = {
2489	MSIOF1_SYNC_MARK,
2490};
2491static const unsigned int msiof1_ss1_pins[] = {
2492	/* SS1 */
2493	RCAR_GP_PIN(4, 10),
2494};
2495static const unsigned int msiof1_ss1_mux[] = {
2496	MSIOF1_SS1_MARK,
2497};
2498static const unsigned int msiof1_ss2_pins[] = {
2499	/* SS2 */
2500	RCAR_GP_PIN(4, 11),
2501};
2502static const unsigned int msiof1_ss2_mux[] = {
2503	MSIOF1_SS2_MARK,
2504};
2505static const unsigned int msiof1_rx_pins[] = {
2506	/* RXD */
2507	RCAR_GP_PIN(4, 13),
2508};
2509static const unsigned int msiof1_rx_mux[] = {
2510	MSIOF1_RXD_MARK,
2511};
2512static const unsigned int msiof1_tx_pins[] = {
2513	/* TXD */
2514	RCAR_GP_PIN(4, 12),
2515};
2516static const unsigned int msiof1_tx_mux[] = {
2517	MSIOF1_TXD_MARK,
2518};
2519
2520static const unsigned int msiof1_clk_b_pins[] = {
2521	/* SCK */
2522	RCAR_GP_PIN(1, 16),
2523};
2524static const unsigned int msiof1_clk_b_mux[] = {
2525	MSIOF1_SCK_B_MARK,
2526};
2527static const unsigned int msiof1_ss1_b_pins[] = {
2528	/* SS1 */
2529	RCAR_GP_PIN(0, 18),
2530};
2531static const unsigned int msiof1_ss1_b_mux[] = {
2532	MSIOF1_SS1_B_MARK,
2533};
2534static const unsigned int msiof1_ss2_b_pins[] = {
2535	/* SS2 */
2536	RCAR_GP_PIN(0, 19),
2537};
2538static const unsigned int msiof1_ss2_b_mux[] = {
2539	MSIOF1_SS2_B_MARK,
2540};
2541static const unsigned int msiof1_rx_b_pins[] = {
2542	/* RXD */
2543	RCAR_GP_PIN(1, 17),
2544};
2545static const unsigned int msiof1_rx_b_mux[] = {
2546	MSIOF1_RXD_B_MARK,
2547};
2548static const unsigned int msiof1_tx_b_pins[] = {
2549	/* TXD */
2550	RCAR_GP_PIN(0, 20),
2551};
2552static const unsigned int msiof1_tx_b_mux[] = {
2553	MSIOF1_TXD_B_MARK,
2554};
2555/* - MSIOF2 ----------------------------------------------------------------- */
2556static const unsigned int msiof2_clk_pins[] = {
2557	/* SCK */
2558	RCAR_GP_PIN(0, 27),
2559};
2560static const unsigned int msiof2_clk_mux[] = {
2561	MSIOF2_SCK_MARK,
2562};
2563static const unsigned int msiof2_sync_pins[] = {
2564	/* SYNC */
2565	RCAR_GP_PIN(0, 26),
2566};
2567static const unsigned int msiof2_sync_mux[] = {
2568	MSIOF2_SYNC_MARK,
2569};
2570static const unsigned int msiof2_ss1_pins[] = {
2571	/* SS1 */
2572	RCAR_GP_PIN(0, 30),
2573};
2574static const unsigned int msiof2_ss1_mux[] = {
2575	MSIOF2_SS1_MARK,
2576};
2577static const unsigned int msiof2_ss2_pins[] = {
2578	/* SS2 */
2579	RCAR_GP_PIN(0, 31),
2580};
2581static const unsigned int msiof2_ss2_mux[] = {
2582	MSIOF2_SS2_MARK,
2583};
2584static const unsigned int msiof2_rx_pins[] = {
2585	/* RXD */
2586	RCAR_GP_PIN(0, 29),
2587};
2588static const unsigned int msiof2_rx_mux[] = {
2589	MSIOF2_RXD_MARK,
2590};
2591static const unsigned int msiof2_tx_pins[] = {
2592	/* TXD */
2593	RCAR_GP_PIN(0, 28),
2594};
2595static const unsigned int msiof2_tx_mux[] = {
2596	MSIOF2_TXD_MARK,
2597};
2598/* - MSIOF3 ----------------------------------------------------------------- */
2599static const unsigned int msiof3_clk_pins[] = {
2600	/* SCK */
2601	RCAR_GP_PIN(5, 4),
2602};
2603static const unsigned int msiof3_clk_mux[] = {
2604	MSIOF3_SCK_MARK,
2605};
2606static const unsigned int msiof3_sync_pins[] = {
2607	/* SYNC */
2608	RCAR_GP_PIN(4, 30),
2609};
2610static const unsigned int msiof3_sync_mux[] = {
2611	MSIOF3_SYNC_MARK,
2612};
2613static const unsigned int msiof3_ss1_pins[] = {
2614	/* SS1 */
2615	RCAR_GP_PIN(4, 31),
2616};
2617static const unsigned int msiof3_ss1_mux[] = {
2618	MSIOF3_SS1_MARK,
2619};
2620static const unsigned int msiof3_ss2_pins[] = {
2621	/* SS2 */
2622	RCAR_GP_PIN(4, 27),
2623};
2624static const unsigned int msiof3_ss2_mux[] = {
2625	MSIOF3_SS2_MARK,
2626};
2627static const unsigned int msiof3_rx_pins[] = {
2628	/* RXD */
2629	RCAR_GP_PIN(5, 2),
2630};
2631static const unsigned int msiof3_rx_mux[] = {
2632	MSIOF3_RXD_MARK,
2633};
2634static const unsigned int msiof3_tx_pins[] = {
2635	/* TXD */
2636	RCAR_GP_PIN(5, 3),
2637};
2638static const unsigned int msiof3_tx_mux[] = {
2639	MSIOF3_TXD_MARK,
2640};
2641
2642static const unsigned int msiof3_clk_b_pins[] = {
2643	/* SCK */
2644	RCAR_GP_PIN(0, 0),
2645};
2646static const unsigned int msiof3_clk_b_mux[] = {
2647	MSIOF3_SCK_B_MARK,
2648};
2649static const unsigned int msiof3_sync_b_pins[] = {
2650	/* SYNC */
2651	RCAR_GP_PIN(0, 1),
2652};
2653static const unsigned int msiof3_sync_b_mux[] = {
2654	MSIOF3_SYNC_B_MARK,
2655};
2656static const unsigned int msiof3_rx_b_pins[] = {
2657	/* RXD */
2658	RCAR_GP_PIN(0, 2),
2659};
2660static const unsigned int msiof3_rx_b_mux[] = {
2661	MSIOF3_RXD_B_MARK,
2662};
2663static const unsigned int msiof3_tx_b_pins[] = {
2664	/* TXD */
2665	RCAR_GP_PIN(0, 3),
2666};
2667static const unsigned int msiof3_tx_b_mux[] = {
2668	MSIOF3_TXD_B_MARK,
2669};
2670/* - PWM -------------------------------------------------------------------- */
2671static const unsigned int pwm0_pins[] = {
2672	RCAR_GP_PIN(5, 29),
2673};
2674static const unsigned int pwm0_mux[] = {
2675	PWM0_MARK,
2676};
2677static const unsigned int pwm0_b_pins[] = {
2678	RCAR_GP_PIN(4, 30),
2679};
2680static const unsigned int pwm0_b_mux[] = {
2681	PWM0_B_MARK,
2682};
2683static const unsigned int pwm1_pins[] = {
2684	RCAR_GP_PIN(5, 30),
2685};
2686static const unsigned int pwm1_mux[] = {
2687	PWM1_MARK,
2688};
2689static const unsigned int pwm1_b_pins[] = {
2690	RCAR_GP_PIN(4, 31),
2691};
2692static const unsigned int pwm1_b_mux[] = {
2693	PWM1_B_MARK,
2694};
2695static const unsigned int pwm2_pins[] = {
2696	RCAR_GP_PIN(5, 31),
2697};
2698static const unsigned int pwm2_mux[] = {
2699	PWM2_MARK,
2700};
2701static const unsigned int pwm3_pins[] = {
2702	RCAR_GP_PIN(0, 16),
2703};
2704static const unsigned int pwm3_mux[] = {
2705	PWM3_MARK,
2706};
2707static const unsigned int pwm4_pins[] = {
2708	RCAR_GP_PIN(0, 17),
2709};
2710static const unsigned int pwm4_mux[] = {
2711	PWM4_MARK,
2712};
2713static const unsigned int pwm5_pins[] = {
2714	RCAR_GP_PIN(0, 18),
2715};
2716static const unsigned int pwm5_mux[] = {
2717	PWM5_MARK,
2718};
2719static const unsigned int pwm6_pins[] = {
2720	RCAR_GP_PIN(0, 19),
2721};
2722static const unsigned int pwm6_mux[] = {
2723	PWM6_MARK,
2724};
2725/* - QSPI ------------------------------------------------------------------- */
2726static const unsigned int qspi_ctrl_pins[] = {
2727	/* SPCLK, SSL */
2728	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2729};
2730static const unsigned int qspi_ctrl_mux[] = {
2731	SPCLK_MARK, SSL_MARK,
2732};
2733static const unsigned int qspi_data2_pins[] = {
2734	/* MOSI_IO0, MISO_IO1 */
2735	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2736};
2737static const unsigned int qspi_data2_mux[] = {
2738	MOSI_IO0_MARK, MISO_IO1_MARK,
2739};
2740static const unsigned int qspi_data4_pins[] = {
2741	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
2742	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2743	RCAR_GP_PIN(1, 8),
2744};
2745static const unsigned int qspi_data4_mux[] = {
2746	MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2747};
2748/* - SCIF0 ------------------------------------------------------------------ */
2749static const unsigned int scif0_data_pins[] = {
2750	/* RX, TX */
2751	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2752};
2753static const unsigned int scif0_data_mux[] = {
2754	RX0_MARK, TX0_MARK,
2755};
2756static const unsigned int scif0_clk_pins[] = {
2757	/* SCK */
2758	RCAR_GP_PIN(4, 27),
2759};
2760static const unsigned int scif0_clk_mux[] = {
2761	SCK0_MARK,
2762};
2763static const unsigned int scif0_ctrl_pins[] = {
2764	/* RTS, CTS */
2765	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2766};
2767static const unsigned int scif0_ctrl_mux[] = {
2768	RTS0_N_MARK, CTS0_N_MARK,
2769};
2770static const unsigned int scif0_data_b_pins[] = {
2771	/* RX, TX */
2772	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2773};
2774static const unsigned int scif0_data_b_mux[] = {
2775	RX0_B_MARK, TX0_B_MARK,
2776};
2777/* - SCIF1 ------------------------------------------------------------------ */
2778static const unsigned int scif1_data_pins[] = {
2779	/* RX, TX */
2780	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2781};
2782static const unsigned int scif1_data_mux[] = {
2783	RX1_MARK, TX1_MARK,
2784};
2785static const unsigned int scif1_clk_pins[] = {
2786	/* SCK */
2787	RCAR_GP_PIN(4, 20),
2788};
2789static const unsigned int scif1_clk_mux[] = {
2790	SCK1_MARK,
2791};
2792static const unsigned int scif1_ctrl_pins[] = {
2793	/* RTS, CTS */
2794	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2795};
2796static const unsigned int scif1_ctrl_mux[] = {
2797	RTS1_N_MARK, CTS1_N_MARK,
2798};
2799static const unsigned int scif1_data_b_pins[] = {
2800	/* RX, TX */
2801	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2802};
2803static const unsigned int scif1_data_b_mux[] = {
2804	RX1_B_MARK, TX1_B_MARK,
2805};
2806static const unsigned int scif1_data_c_pins[] = {
2807	/* RX, TX */
2808	RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2809};
2810static const unsigned int scif1_data_c_mux[] = {
2811	RX1_C_MARK, TX1_C_MARK,
2812};
2813static const unsigned int scif1_data_d_pins[] = {
2814	/* RX, TX */
2815	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2816};
2817static const unsigned int scif1_data_d_mux[] = {
2818	RX1_D_MARK, TX1_D_MARK,
2819};
2820static const unsigned int scif1_clk_d_pins[] = {
2821	/* SCK */
2822	RCAR_GP_PIN(3, 17),
2823};
2824static const unsigned int scif1_clk_d_mux[] = {
2825	SCK1_D_MARK,
2826};
2827static const unsigned int scif1_data_e_pins[] = {
2828	/* RX, TX */
2829	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2830};
2831static const unsigned int scif1_data_e_mux[] = {
2832	RX1_E_MARK, TX1_E_MARK,
2833};
2834static const unsigned int scif1_clk_e_pins[] = {
2835	/* SCK */
2836	RCAR_GP_PIN(2, 20),
2837};
2838static const unsigned int scif1_clk_e_mux[] = {
2839	SCK1_E_MARK,
2840};
2841/* - SCIF2 ------------------------------------------------------------------ */
2842static const unsigned int scif2_data_pins[] = {
2843	/* RX, TX */
2844	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
2845};
2846static const unsigned int scif2_data_mux[] = {
2847	RX2_MARK, TX2_MARK,
2848};
2849static const unsigned int scif2_clk_pins[] = {
2850	/* SCK */
2851	RCAR_GP_PIN(5, 4),
2852};
2853static const unsigned int scif2_clk_mux[] = {
2854	SCK2_MARK,
2855};
2856static const unsigned int scif2_data_b_pins[] = {
2857	/* RX, TX */
2858	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2859};
2860static const unsigned int scif2_data_b_mux[] = {
2861	RX2_B_MARK, TX2_B_MARK,
2862};
2863/* - SCIFA0 ----------------------------------------------------------------- */
2864static const unsigned int scifa0_data_pins[] = {
2865	/* RXD, TXD */
2866	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2867};
2868static const unsigned int scifa0_data_mux[] = {
2869	SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2870};
2871static const unsigned int scifa0_clk_pins[] = {
2872	/* SCK */
2873	RCAR_GP_PIN(4, 27),
2874};
2875static const unsigned int scifa0_clk_mux[] = {
2876	SCIFA0_SCK_MARK,
2877};
2878static const unsigned int scifa0_ctrl_pins[] = {
2879	/* RTS, CTS */
2880	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2881};
2882static const unsigned int scifa0_ctrl_mux[] = {
2883	SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK,
2884};
2885static const unsigned int scifa0_data_b_pins[] = {
2886	/* RXD, TXD */
2887	RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
2888};
2889static const unsigned int scifa0_data_b_mux[] = {
2890	SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2891};
2892static const unsigned int scifa0_clk_b_pins[] = {
2893	/* SCK */
2894	RCAR_GP_PIN(1, 19),
2895};
2896static const unsigned int scifa0_clk_b_mux[] = {
2897	SCIFA0_SCK_B_MARK,
2898};
2899static const unsigned int scifa0_ctrl_b_pins[] = {
2900	/* RTS, CTS */
2901	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
2902};
2903static const unsigned int scifa0_ctrl_b_mux[] = {
2904	SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK,
2905};
2906/* - SCIFA1 ----------------------------------------------------------------- */
2907static const unsigned int scifa1_data_pins[] = {
2908	/* RXD, TXD */
2909	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2910};
2911static const unsigned int scifa1_data_mux[] = {
2912	SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2913};
2914static const unsigned int scifa1_clk_pins[] = {
2915	/* SCK */
2916	RCAR_GP_PIN(4, 20),
2917};
2918static const unsigned int scifa1_clk_mux[] = {
2919	SCIFA1_SCK_MARK,
2920};
2921static const unsigned int scifa1_ctrl_pins[] = {
2922	/* RTS, CTS */
2923	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2924};
2925static const unsigned int scifa1_ctrl_mux[] = {
2926	SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK,
2927};
2928static const unsigned int scifa1_data_b_pins[] = {
2929	/* RXD, TXD */
2930	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
2931};
2932static const unsigned int scifa1_data_b_mux[] = {
2933	SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2934};
2935static const unsigned int scifa1_clk_b_pins[] = {
2936	/* SCK */
2937	RCAR_GP_PIN(0, 23),
2938};
2939static const unsigned int scifa1_clk_b_mux[] = {
2940	SCIFA1_SCK_B_MARK,
2941};
2942static const unsigned int scifa1_ctrl_b_pins[] = {
2943	/* RTS, CTS */
2944	RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
2945};
2946static const unsigned int scifa1_ctrl_b_mux[] = {
2947	SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK,
2948};
2949static const unsigned int scifa1_data_c_pins[] = {
2950	/* RXD, TXD */
2951	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2952};
2953static const unsigned int scifa1_data_c_mux[] = {
2954	SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2955};
2956static const unsigned int scifa1_clk_c_pins[] = {
2957	/* SCK */
2958	RCAR_GP_PIN(0, 8),
2959};
2960static const unsigned int scifa1_clk_c_mux[] = {
2961	SCIFA1_SCK_C_MARK,
2962};
2963static const unsigned int scifa1_ctrl_c_pins[] = {
2964	/* RTS, CTS */
2965	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
2966};
2967static const unsigned int scifa1_ctrl_c_mux[] = {
2968	SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK,
2969};
2970static const unsigned int scifa1_data_d_pins[] = {
2971	/* RXD, TXD */
2972	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2973};
2974static const unsigned int scifa1_data_d_mux[] = {
2975	SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK,
2976};
2977static const unsigned int scifa1_clk_d_pins[] = {
2978	/* SCK */
2979	RCAR_GP_PIN(2, 10),
2980};
2981static const unsigned int scifa1_clk_d_mux[] = {
2982	SCIFA1_SCK_D_MARK,
2983};
2984static const unsigned int scifa1_ctrl_d_pins[] = {
2985	/* RTS, CTS */
2986	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
2987};
2988static const unsigned int scifa1_ctrl_d_mux[] = {
2989	SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK,
2990};
2991/* - SCIFA2 ----------------------------------------------------------------- */
2992static const unsigned int scifa2_data_pins[] = {
2993	/* RXD, TXD */
2994	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2995};
2996static const unsigned int scifa2_data_mux[] = {
2997	SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2998};
2999static const unsigned int scifa2_clk_pins[] = {
3000	/* SCK */
3001	RCAR_GP_PIN(5, 4),
3002};
3003static const unsigned int scifa2_clk_mux[] = {
3004	SCIFA2_SCK_MARK,
3005};
3006static const unsigned int scifa2_ctrl_pins[] = {
3007	/* RTS, CTS */
3008	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
3009};
3010static const unsigned int scifa2_ctrl_mux[] = {
3011	SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK,
3012};
3013static const unsigned int scifa2_data_b_pins[] = {
3014	/* RXD, TXD */
3015	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
3016};
3017static const unsigned int scifa2_data_b_mux[] = {
3018	SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
3019};
3020static const unsigned int scifa2_data_c_pins[] = {
3021	/* RXD, TXD */
3022	RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
3023};
3024static const unsigned int scifa2_data_c_mux[] = {
3025	SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK,
3026};
3027static const unsigned int scifa2_clk_c_pins[] = {
3028	/* SCK */
3029	RCAR_GP_PIN(5, 29),
3030};
3031static const unsigned int scifa2_clk_c_mux[] = {
3032	SCIFA2_SCK_C_MARK,
3033};
3034/* - SCIFB0 ----------------------------------------------------------------- */
3035static const unsigned int scifb0_data_pins[] = {
3036	/* RXD, TXD */
3037	RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3038};
3039static const unsigned int scifb0_data_mux[] = {
3040	SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
3041};
3042static const unsigned int scifb0_clk_pins[] = {
3043	/* SCK */
3044	RCAR_GP_PIN(4, 8),
3045};
3046static const unsigned int scifb0_clk_mux[] = {
3047	SCIFB0_SCK_MARK,
3048};
3049static const unsigned int scifb0_ctrl_pins[] = {
3050	/* RTS, CTS */
3051	RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
3052};
3053static const unsigned int scifb0_ctrl_mux[] = {
3054	SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
3055};
3056static const unsigned int scifb0_data_b_pins[] = {
3057	/* RXD, TXD */
3058	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3059};
3060static const unsigned int scifb0_data_b_mux[] = {
3061	SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
3062};
3063static const unsigned int scifb0_clk_b_pins[] = {
3064	/* SCK */
3065	RCAR_GP_PIN(3, 9),
3066};
3067static const unsigned int scifb0_clk_b_mux[] = {
3068	SCIFB0_SCK_B_MARK,
3069};
3070static const unsigned int scifb0_ctrl_b_pins[] = {
3071	/* RTS, CTS */
3072	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
3073};
3074static const unsigned int scifb0_ctrl_b_mux[] = {
3075	SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
3076};
3077static const unsigned int scifb0_data_c_pins[] = {
3078	/* RXD, TXD */
3079	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3080};
3081static const unsigned int scifb0_data_c_mux[] = {
3082	SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
3083};
3084/* - SCIFB1 ----------------------------------------------------------------- */
3085static const unsigned int scifb1_data_pins[] = {
3086	/* RXD, TXD */
3087	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3088};
3089static const unsigned int scifb1_data_mux[] = {
3090	SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3091};
3092static const unsigned int scifb1_clk_pins[] = {
3093	/* SCK */
3094	RCAR_GP_PIN(4, 14),
3095};
3096static const unsigned int scifb1_clk_mux[] = {
3097	SCIFB1_SCK_MARK,
3098};
3099static const unsigned int scifb1_ctrl_pins[] = {
3100	/* RTS, CTS */
3101	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
3102};
3103static const unsigned int scifb1_ctrl_mux[] = {
3104	SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
3105};
3106static const unsigned int scifb1_data_b_pins[] = {
3107	/* RXD, TXD */
3108	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3109};
3110static const unsigned int scifb1_data_b_mux[] = {
3111	SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
3112};
3113static const unsigned int scifb1_clk_b_pins[] = {
3114	/* SCK */
3115	RCAR_GP_PIN(3, 1),
3116};
3117static const unsigned int scifb1_clk_b_mux[] = {
3118	SCIFB1_SCK_B_MARK,
3119};
3120static const unsigned int scifb1_ctrl_b_pins[] = {
3121	/* RTS, CTS */
3122	RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
3123};
3124static const unsigned int scifb1_ctrl_b_mux[] = {
3125	SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK,
3126};
3127static const unsigned int scifb1_data_c_pins[] = {
3128	/* RXD, TXD */
3129	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3130};
3131static const unsigned int scifb1_data_c_mux[] = {
3132	SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
3133};
3134static const unsigned int scifb1_data_d_pins[] = {
3135	/* RXD, TXD */
3136	RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
3137};
3138static const unsigned int scifb1_data_d_mux[] = {
3139	SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
3140};
3141static const unsigned int scifb1_data_e_pins[] = {
3142	/* RXD, TXD */
3143	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
3144};
3145static const unsigned int scifb1_data_e_mux[] = {
3146	SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK,
3147};
3148static const unsigned int scifb1_clk_e_pins[] = {
3149	/* SCK */
3150	RCAR_GP_PIN(3, 17),
3151};
3152static const unsigned int scifb1_clk_e_mux[] = {
3153	SCIFB1_SCK_E_MARK,
3154};
3155static const unsigned int scifb1_data_f_pins[] = {
3156	/* RXD, TXD */
3157	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3158};
3159static const unsigned int scifb1_data_f_mux[] = {
3160	SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK,
3161};
3162static const unsigned int scifb1_data_g_pins[] = {
3163	/* RXD, TXD */
3164	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
3165};
3166static const unsigned int scifb1_data_g_mux[] = {
3167	SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK,
3168};
3169static const unsigned int scifb1_clk_g_pins[] = {
3170	/* SCK */
3171	RCAR_GP_PIN(2, 20),
3172};
3173static const unsigned int scifb1_clk_g_mux[] = {
3174	SCIFB1_SCK_G_MARK,
3175};
3176/* - SCIFB2 ----------------------------------------------------------------- */
3177static const unsigned int scifb2_data_pins[] = {
3178	/* RXD, TXD */
3179	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
3180};
3181static const unsigned int scifb2_data_mux[] = {
3182	SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3183};
3184static const unsigned int scifb2_clk_pins[] = {
3185	/* SCK */
3186	RCAR_GP_PIN(4, 21),
3187};
3188static const unsigned int scifb2_clk_mux[] = {
3189	SCIFB2_SCK_MARK,
3190};
3191static const unsigned int scifb2_ctrl_pins[] = {
3192	/* RTS, CTS */
3193	RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
3194};
3195static const unsigned int scifb2_ctrl_mux[] = {
3196	SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3197};
3198static const unsigned int scifb2_data_b_pins[] = {
3199	/* RXD, TXD */
3200	RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
3201};
3202static const unsigned int scifb2_data_b_mux[] = {
3203	SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
3204};
3205static const unsigned int scifb2_clk_b_pins[] = {
3206	/* SCK */
3207	RCAR_GP_PIN(0, 31),
3208};
3209static const unsigned int scifb2_clk_b_mux[] = {
3210	SCIFB2_SCK_B_MARK,
3211};
3212static const unsigned int scifb2_ctrl_b_pins[] = {
3213	/* RTS, CTS */
3214	RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
3215};
3216static const unsigned int scifb2_ctrl_b_mux[] = {
3217	SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
3218};
3219static const unsigned int scifb2_data_c_pins[] = {
3220	/* RXD, TXD */
3221	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3222};
3223static const unsigned int scifb2_data_c_mux[] = {
3224	SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
3225};
3226/* - SCIF Clock ------------------------------------------------------------- */
3227static const unsigned int scif_clk_pins[] = {
3228	/* SCIF_CLK */
3229	RCAR_GP_PIN(4, 26),
3230};
3231static const unsigned int scif_clk_mux[] = {
3232	SCIF_CLK_MARK,
3233};
3234static const unsigned int scif_clk_b_pins[] = {
3235	/* SCIF_CLK */
3236	RCAR_GP_PIN(5, 4),
3237};
3238static const unsigned int scif_clk_b_mux[] = {
3239	SCIF_CLK_B_MARK,
3240};
3241/* - SDHI0 ------------------------------------------------------------------ */
3242static const unsigned int sdhi0_data1_pins[] = {
3243	/* D0 */
3244	RCAR_GP_PIN(3, 2),
3245};
3246static const unsigned int sdhi0_data1_mux[] = {
3247	SD0_DAT0_MARK,
3248};
3249static const unsigned int sdhi0_data4_pins[] = {
3250	/* D[0:3] */
3251	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3252};
3253static const unsigned int sdhi0_data4_mux[] = {
3254	SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
3255};
3256static const unsigned int sdhi0_ctrl_pins[] = {
3257	/* CLK, CMD */
3258	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3259};
3260static const unsigned int sdhi0_ctrl_mux[] = {
3261	SD0_CLK_MARK, SD0_CMD_MARK,
3262};
3263static const unsigned int sdhi0_cd_pins[] = {
3264	/* CD */
3265	RCAR_GP_PIN(3, 6),
3266};
3267static const unsigned int sdhi0_cd_mux[] = {
3268	SD0_CD_MARK,
3269};
3270static const unsigned int sdhi0_wp_pins[] = {
3271	/* WP */
3272	RCAR_GP_PIN(3, 7),
3273};
3274static const unsigned int sdhi0_wp_mux[] = {
3275	SD0_WP_MARK,
3276};
3277/* - SDHI1 ------------------------------------------------------------------ */
3278static const unsigned int sdhi1_data1_pins[] = {
3279	/* D0 */
3280	RCAR_GP_PIN(3, 10),
3281};
3282static const unsigned int sdhi1_data1_mux[] = {
3283	SD1_DAT0_MARK,
3284};
3285static const unsigned int sdhi1_data4_pins[] = {
3286	/* D[0:3] */
3287	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3288};
3289static const unsigned int sdhi1_data4_mux[] = {
3290	SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
3291};
3292static const unsigned int sdhi1_ctrl_pins[] = {
3293	/* CLK, CMD */
3294	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3295};
3296static const unsigned int sdhi1_ctrl_mux[] = {
3297	SD1_CLK_MARK, SD1_CMD_MARK,
3298};
3299static const unsigned int sdhi1_cd_pins[] = {
3300	/* CD */
3301	RCAR_GP_PIN(3, 14),
3302};
3303static const unsigned int sdhi1_cd_mux[] = {
3304	SD1_CD_MARK,
3305};
3306static const unsigned int sdhi1_wp_pins[] = {
3307	/* WP */
3308	RCAR_GP_PIN(3, 15),
3309};
3310static const unsigned int sdhi1_wp_mux[] = {
3311	SD1_WP_MARK,
3312};
3313/* - SDHI2 ------------------------------------------------------------------ */
3314static const unsigned int sdhi2_data1_pins[] = {
3315	/* D0 */
3316	RCAR_GP_PIN(3, 18),
3317};
3318static const unsigned int sdhi2_data1_mux[] = {
3319	SD2_DAT0_MARK,
3320};
3321static const unsigned int sdhi2_data4_pins[] = {
3322	/* D[0:3] */
3323	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
3324};
3325static const unsigned int sdhi2_data4_mux[] = {
3326	SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
3327};
3328static const unsigned int sdhi2_ctrl_pins[] = {
3329	/* CLK, CMD */
3330	RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
3331};
3332static const unsigned int sdhi2_ctrl_mux[] = {
3333	SD2_CLK_MARK, SD2_CMD_MARK,
3334};
3335static const unsigned int sdhi2_cd_pins[] = {
3336	/* CD */
3337	RCAR_GP_PIN(3, 22),
3338};
3339static const unsigned int sdhi2_cd_mux[] = {
3340	SD2_CD_MARK,
3341};
3342static const unsigned int sdhi2_wp_pins[] = {
3343	/* WP */
3344	RCAR_GP_PIN(3, 23),
3345};
3346static const unsigned int sdhi2_wp_mux[] = {
3347	SD2_WP_MARK,
3348};
3349/* - SDHI3 ------------------------------------------------------------------ */
3350static const unsigned int sdhi3_data1_pins[] = {
3351	/* D0 */
3352	RCAR_GP_PIN(3, 26),
3353};
3354static const unsigned int sdhi3_data1_mux[] = {
3355	SD3_DAT0_MARK,
3356};
3357static const unsigned int sdhi3_data4_pins[] = {
3358	/* D[0:3] */
3359	RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
3360};
3361static const unsigned int sdhi3_data4_mux[] = {
3362	SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
3363};
3364static const unsigned int sdhi3_ctrl_pins[] = {
3365	/* CLK, CMD */
3366	RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
3367};
3368static const unsigned int sdhi3_ctrl_mux[] = {
3369	SD3_CLK_MARK, SD3_CMD_MARK,
3370};
3371static const unsigned int sdhi3_cd_pins[] = {
3372	/* CD */
3373	RCAR_GP_PIN(3, 30),
3374};
3375static const unsigned int sdhi3_cd_mux[] = {
3376	SD3_CD_MARK,
3377};
3378static const unsigned int sdhi3_wp_pins[] = {
3379	/* WP */
3380	RCAR_GP_PIN(3, 31),
3381};
3382static const unsigned int sdhi3_wp_mux[] = {
3383	SD3_WP_MARK,
3384};
3385/* - SSI -------------------------------------------------------------------- */
3386static const unsigned int ssi0_data_pins[] = {
3387	/* SDATA0 */
3388	RCAR_GP_PIN(4, 5),
3389};
3390static const unsigned int ssi0_data_mux[] = {
3391	SSI_SDATA0_MARK,
3392};
3393static const unsigned int ssi0129_ctrl_pins[] = {
3394	/* SCK, WS */
3395	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4),
3396};
3397static const unsigned int ssi0129_ctrl_mux[] = {
3398	SSI_SCK0129_MARK, SSI_WS0129_MARK,
3399};
3400static const unsigned int ssi1_data_pins[] = {
3401	/* SDATA1 */
3402	RCAR_GP_PIN(4, 6),
3403};
3404static const unsigned int ssi1_data_mux[] = {
3405	SSI_SDATA1_MARK,
3406};
3407static const unsigned int ssi1_ctrl_pins[] = {
3408	/* SCK, WS */
3409	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24),
3410};
3411static const unsigned int ssi1_ctrl_mux[] = {
3412	SSI_SCK1_MARK, SSI_WS1_MARK,
3413};
3414static const unsigned int ssi2_data_pins[] = {
3415	/* SDATA2 */
3416	RCAR_GP_PIN(4, 7),
3417};
3418static const unsigned int ssi2_data_mux[] = {
3419	SSI_SDATA2_MARK,
3420};
3421static const unsigned int ssi2_ctrl_pins[] = {
3422	/* SCK, WS */
3423	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17),
3424};
3425static const unsigned int ssi2_ctrl_mux[] = {
3426	SSI_SCK2_MARK, SSI_WS2_MARK,
3427};
3428static const unsigned int ssi3_data_pins[] = {
3429	/* SDATA3 */
3430	RCAR_GP_PIN(4, 10),
3431};
3432static const unsigned int ssi3_data_mux[] = {
3433	SSI_SDATA3_MARK
3434};
3435static const unsigned int ssi34_ctrl_pins[] = {
3436	/* SCK, WS */
3437	RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
3438};
3439static const unsigned int ssi34_ctrl_mux[] = {
3440	SSI_SCK34_MARK, SSI_WS34_MARK,
3441};
3442static const unsigned int ssi4_data_pins[] = {
3443	/* SDATA4 */
3444	RCAR_GP_PIN(4, 13),
3445};
3446static const unsigned int ssi4_data_mux[] = {
3447	SSI_SDATA4_MARK,
3448};
3449static const unsigned int ssi4_ctrl_pins[] = {
3450	/* SCK, WS */
3451	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3452};
3453static const unsigned int ssi4_ctrl_mux[] = {
3454	SSI_SCK4_MARK, SSI_WS4_MARK,
3455};
3456static const unsigned int ssi5_pins[] = {
3457	/* SDATA5, SCK, WS */
3458	RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
3459};
3460static const unsigned int ssi5_mux[] = {
3461	SSI_SDATA5_MARK, SSI_SCK5_MARK, SSI_WS5_MARK,
3462};
3463static const unsigned int ssi5_b_pins[] = {
3464	/* SDATA5, SCK, WS */
3465	RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3466};
3467static const unsigned int ssi5_b_mux[] = {
3468	SSI_SDATA5_B_MARK, SSI_SCK5_B_MARK, SSI_WS5_B_MARK
3469};
3470static const unsigned int ssi5_c_pins[] = {
3471	/* SDATA5, SCK, WS */
3472	RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3473};
3474static const unsigned int ssi5_c_mux[] = {
3475	SSI_SDATA5_C_MARK, SSI_SCK5_C_MARK, SSI_WS5_C_MARK,
3476};
3477static const unsigned int ssi6_pins[] = {
3478	/* SDATA6, SCK, WS */
3479	RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3480};
3481static const unsigned int ssi6_mux[] = {
3482	SSI_SDATA6_MARK, SSI_SCK6_MARK, SSI_WS6_MARK,
3483};
3484static const unsigned int ssi6_b_pins[] = {
3485	/* SDATA6, SCK, WS */
3486	RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27),
3487};
3488static const unsigned int ssi6_b_mux[] = {
3489	SSI_SDATA6_B_MARK, SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
3490};
3491static const unsigned int ssi7_data_pins[] = {
3492	/* SDATA7 */
3493	RCAR_GP_PIN(4, 22),
3494};
3495static const unsigned int ssi7_data_mux[] = {
3496	SSI_SDATA7_MARK,
3497};
3498static const unsigned int ssi7_b_data_pins[] = {
3499	/* SDATA7 */
3500	RCAR_GP_PIN(4, 22),
3501};
3502static const unsigned int ssi7_b_data_mux[] = {
3503	SSI_SDATA7_B_MARK,
3504};
3505static const unsigned int ssi7_c_data_pins[] = {
3506	/* SDATA7 */
3507	RCAR_GP_PIN(1, 26),
3508};
3509static const unsigned int ssi7_c_data_mux[] = {
3510	SSI_SDATA7_C_MARK,
3511};
3512static const unsigned int ssi78_ctrl_pins[] = {
3513	/* SCK, WS */
3514	RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3515};
3516static const unsigned int ssi78_ctrl_mux[] = {
3517	SSI_SCK78_MARK, SSI_WS78_MARK,
3518};
3519static const unsigned int ssi78_b_ctrl_pins[] = {
3520	/* SCK, WS */
3521	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24),
3522};
3523static const unsigned int ssi78_b_ctrl_mux[] = {
3524	SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
3525};
3526static const unsigned int ssi78_c_ctrl_pins[] = {
3527	/* SCK, WS */
3528	RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
3529};
3530static const unsigned int ssi78_c_ctrl_mux[] = {
3531	SSI_SCK78_C_MARK, SSI_WS78_C_MARK,
3532};
3533static const unsigned int ssi8_data_pins[] = {
3534	/* SDATA8 */
3535	RCAR_GP_PIN(4, 23),
3536};
3537static const unsigned int ssi8_data_mux[] = {
3538	SSI_SDATA8_MARK,
3539};
3540static const unsigned int ssi8_b_data_pins[] = {
3541	/* SDATA8 */
3542	RCAR_GP_PIN(4, 23),
3543};
3544static const unsigned int ssi8_b_data_mux[] = {
3545	SSI_SDATA8_B_MARK,
3546};
3547static const unsigned int ssi8_c_data_pins[] = {
3548	/* SDATA8 */
3549	RCAR_GP_PIN(1, 27),
3550};
3551static const unsigned int ssi8_c_data_mux[] = {
3552	SSI_SDATA8_C_MARK,
3553};
3554static const unsigned int ssi9_data_pins[] = {
3555	/* SDATA9 */
3556	RCAR_GP_PIN(4, 24),
3557};
3558static const unsigned int ssi9_data_mux[] = {
3559	SSI_SDATA9_MARK,
3560};
3561static const unsigned int ssi9_ctrl_pins[] = {
3562	/* SCK, WS */
3563	RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
3564};
3565static const unsigned int ssi9_ctrl_mux[] = {
3566	SSI_SCK9_MARK, SSI_WS9_MARK,
3567};
3568/* - TPU0 ------------------------------------------------------------------- */
3569static const unsigned int tpu0_to0_pins[] = {
3570	/* TO */
3571	RCAR_GP_PIN(0, 20),
3572};
3573static const unsigned int tpu0_to0_mux[] = {
3574	TPU0TO0_MARK,
3575};
3576static const unsigned int tpu0_to1_pins[] = {
3577	/* TO */
3578	RCAR_GP_PIN(0, 21),
3579};
3580static const unsigned int tpu0_to1_mux[] = {
3581	TPU0TO1_MARK,
3582};
3583static const unsigned int tpu0_to2_pins[] = {
3584	/* TO */
3585	RCAR_GP_PIN(0, 22),
3586};
3587static const unsigned int tpu0_to2_mux[] = {
3588	TPU0TO2_MARK,
3589};
3590static const unsigned int tpu0_to3_pins[] = {
3591	/* TO */
3592	RCAR_GP_PIN(0, 23),
3593};
3594static const unsigned int tpu0_to3_mux[] = {
3595	TPU0TO3_MARK,
3596};
3597/* - USB0 ------------------------------------------------------------------- */
3598static const unsigned int usb0_pins[] = {
3599	/* PWEN, OVC/VBUS */
3600	RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
3601};
3602static const unsigned int usb0_mux[] = {
3603	USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
3604};
3605static const unsigned int usb0_ovc_vbus_pins[] = {
3606	/* OVC/VBUS */
3607	RCAR_GP_PIN(5, 19),
3608};
3609static const unsigned int usb0_ovc_vbus_mux[] = {
3610	USB0_OVC_VBUS_MARK,
3611};
3612/* - USB1 ------------------------------------------------------------------- */
3613static const unsigned int usb1_pins[] = {
3614	/* PWEN, OVC */
3615	RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
3616};
3617static const unsigned int usb1_mux[] = {
3618	USB1_PWEN_MARK, USB1_OVC_MARK,
3619};
3620/* - USB2 ------------------------------------------------------------------- */
3621static const unsigned int usb2_pins[] = {
3622	/* PWEN, OVC */
3623	RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
3624};
3625static const unsigned int usb2_mux[] = {
3626	USB2_PWEN_MARK, USB2_OVC_MARK,
3627};
3628/* - VIN0 ------------------------------------------------------------------- */
3629static const union vin_data vin0_data_pins = {
3630	.data24 = {
3631		/* B */
3632		RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
3633		RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3634		RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3635		RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3636		/* G */
3637		RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3638		RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3639		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3640		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3641		/* R */
3642		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3643		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3644		RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3645		RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3646	},
3647};
3648static const union vin_data vin0_data_mux = {
3649	.data24 = {
3650		/* B */
3651		VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3652		VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3653		VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3654		VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3655		/* G */
3656		VI0_G0_MARK, VI0_G1_MARK,
3657		VI0_G2_MARK, VI0_G3_MARK,
3658		VI0_G4_MARK, VI0_G5_MARK,
3659		VI0_G6_MARK, VI0_G7_MARK,
3660		/* R */
3661		VI0_R0_MARK, VI0_R1_MARK,
3662		VI0_R2_MARK, VI0_R3_MARK,
3663		VI0_R4_MARK, VI0_R5_MARK,
3664		VI0_R6_MARK, VI0_R7_MARK,
3665	},
3666};
3667static const unsigned int vin0_data18_pins[] = {
3668	/* B */
3669	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3670	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3671	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3672	/* G */
3673	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3674	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3675	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3676	/* R */
3677	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3678	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3679	RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3680};
3681static const unsigned int vin0_data18_mux[] = {
3682	/* B */
3683	VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3684	VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3685	VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3686	/* G */
3687	VI0_G2_MARK, VI0_G3_MARK,
3688	VI0_G4_MARK, VI0_G5_MARK,
3689	VI0_G6_MARK, VI0_G7_MARK,
3690	/* R */
3691	VI0_R2_MARK, VI0_R3_MARK,
3692	VI0_R4_MARK, VI0_R5_MARK,
3693	VI0_R6_MARK, VI0_R7_MARK,
3694};
3695static const unsigned int vin0_sync_pins[] = {
3696	RCAR_GP_PIN(0, 12), /* HSYNC */
3697	RCAR_GP_PIN(0, 13), /* VSYNC */
3698};
3699static const unsigned int vin0_sync_mux[] = {
3700	VI0_HSYNC_N_MARK,
3701	VI0_VSYNC_N_MARK,
3702};
3703static const unsigned int vin0_field_pins[] = {
3704	RCAR_GP_PIN(0, 15),
3705};
3706static const unsigned int vin0_field_mux[] = {
3707	VI0_FIELD_MARK,
3708};
3709static const unsigned int vin0_clkenb_pins[] = {
3710	RCAR_GP_PIN(0, 14),
3711};
3712static const unsigned int vin0_clkenb_mux[] = {
3713	VI0_CLKENB_MARK,
3714};
3715static const unsigned int vin0_clk_pins[] = {
3716	RCAR_GP_PIN(2, 0),
3717};
3718static const unsigned int vin0_clk_mux[] = {
3719	VI0_CLK_MARK,
3720};
3721/* - VIN1 ------------------------------------------------------------------- */
3722static const union vin_data vin1_data_pins = {
3723	.data24 = {
3724		/* B */
3725		RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3726		RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3727		RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3728		RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3729		/* G */
3730		RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3731		RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3732		RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3733		RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3734		/* R */
3735		RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3736		RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3737		RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3738		RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3739	},
3740};
3741static const union vin_data vin1_data_mux = {
3742	.data24 = {
3743		/* B */
3744		VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
3745		VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3746		VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3747		VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3748		/* G */
3749		VI1_G0_MARK, VI1_G1_MARK,
3750		VI1_G2_MARK, VI1_G3_MARK,
3751		VI1_G4_MARK, VI1_G5_MARK,
3752		VI1_G6_MARK, VI1_G7_MARK,
3753		/* R */
3754		VI1_R0_MARK, VI1_R1_MARK,
3755		VI1_R2_MARK, VI1_R3_MARK,
3756		VI1_R4_MARK, VI1_R5_MARK,
3757		VI1_R6_MARK, VI1_R7_MARK,
3758	},
3759};
3760static const unsigned int vin1_data18_pins[] = {
3761	/* B */
3762	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3763	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3764	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3765	/* G */
3766	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3767	RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3768	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3769	/* R */
3770	RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3771	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3772	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3773};
3774static const unsigned int vin1_data18_mux[] = {
3775	/* B */
3776	VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3777	VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3778	VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3779	/* G */
3780	VI1_G2_MARK, VI1_G3_MARK,
3781	VI1_G4_MARK, VI1_G5_MARK,
3782	VI1_G6_MARK, VI1_G7_MARK,
3783	/* R */
3784	VI1_R2_MARK, VI1_R3_MARK,
3785	VI1_R4_MARK, VI1_R5_MARK,
3786	VI1_R6_MARK, VI1_R7_MARK,
3787};
3788static const unsigned int vin1_sync_pins[] = {
3789	RCAR_GP_PIN(1, 24), /* HSYNC */
3790	RCAR_GP_PIN(1, 25), /* VSYNC */
3791};
3792static const unsigned int vin1_sync_mux[] = {
3793	VI1_HSYNC_N_MARK,
3794	VI1_VSYNC_N_MARK,
3795};
3796static const unsigned int vin1_field_pins[] = {
3797	RCAR_GP_PIN(1, 13),
3798};
3799static const unsigned int vin1_field_mux[] = {
3800	VI1_FIELD_MARK,
3801};
3802static const unsigned int vin1_clkenb_pins[] = {
3803	RCAR_GP_PIN(1, 26),
3804};
3805static const unsigned int vin1_clkenb_mux[] = {
3806	VI1_CLKENB_MARK,
3807};
3808static const unsigned int vin1_clk_pins[] = {
3809	RCAR_GP_PIN(2, 9),
3810};
3811static const unsigned int vin1_clk_mux[] = {
3812	VI1_CLK_MARK,
3813};
3814/* - VIN2 ----------------------------------------------------------------- */
3815static const union vin_data vin2_data_pins = {
3816	.data24 = {
3817		/* B */
3818		RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3819		RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3820		RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3821		RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3822		/* G */
3823		RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3824		RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3825		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3826		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3827		/* R */
3828		RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3829		RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3830		RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3831		RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3832	},
3833};
3834static const union vin_data vin2_data_mux = {
3835	.data24 = {
3836		/* B */
3837		VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
3838		VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
3839		VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
3840		VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
3841		/* G */
3842		VI2_G0_MARK, VI2_G1_MARK,
3843		VI2_G2_MARK, VI2_G3_MARK,
3844		VI2_G4_MARK, VI2_G5_MARK,
3845		VI2_G6_MARK, VI2_G7_MARK,
3846		/* R */
3847		VI2_R0_MARK, VI2_R1_MARK,
3848		VI2_R2_MARK, VI2_R3_MARK,
3849		VI2_R4_MARK, VI2_R5_MARK,
3850		VI2_R6_MARK, VI2_R7_MARK,
3851	},
3852};
3853static const unsigned int vin2_data18_pins[] = {
3854	/* B */
3855	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3856	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3857	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3858	/* G */
3859	RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3860	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3861	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3862	/* R */
3863	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3864	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3865	RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3866};
3867static const unsigned int vin2_data18_mux[] = {
3868	/* B */
3869	VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
3870	VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
3871	VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
3872	/* G */
3873	VI2_G2_MARK, VI2_G3_MARK,
3874	VI2_G4_MARK, VI2_G5_MARK,
3875	VI2_G6_MARK, VI2_G7_MARK,
3876	/* R */
3877	VI2_R2_MARK, VI2_R3_MARK,
3878	VI2_R4_MARK, VI2_R5_MARK,
3879	VI2_R6_MARK, VI2_R7_MARK,
3880};
3881static const unsigned int vin2_sync_pins[] = {
3882	RCAR_GP_PIN(1, 16), /* HSYNC */
3883	RCAR_GP_PIN(1, 21), /* VSYNC */
3884};
3885static const unsigned int vin2_sync_mux[] = {
3886	VI2_HSYNC_N_MARK,
3887	VI2_VSYNC_N_MARK,
3888};
3889static const unsigned int vin2_field_pins[] = {
3890	RCAR_GP_PIN(1, 9),
3891};
3892static const unsigned int vin2_field_mux[] = {
3893	VI2_FIELD_MARK,
3894};
3895static const unsigned int vin2_clkenb_pins[] = {
3896	RCAR_GP_PIN(1, 8),
3897};
3898static const unsigned int vin2_clkenb_mux[] = {
3899	VI2_CLKENB_MARK,
3900};
3901static const unsigned int vin2_clk_pins[] = {
3902	RCAR_GP_PIN(1, 11),
3903};
3904static const unsigned int vin2_clk_mux[] = {
3905	VI2_CLK_MARK,
3906};
3907/* - VIN3 ----------------------------------------------------------------- */
3908static const unsigned int vin3_data8_pins[] = {
3909	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3910	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3911	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3912	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3913};
3914static const unsigned int vin3_data8_mux[] = {
3915	VI3_DATA0_MARK, VI3_DATA1_MARK,
3916	VI3_DATA2_MARK, VI3_DATA3_MARK,
3917	VI3_DATA4_MARK, VI3_DATA5_MARK,
3918	VI3_DATA6_MARK, VI3_DATA7_MARK,
3919};
3920static const unsigned int vin3_sync_pins[] = {
3921	RCAR_GP_PIN(1, 16), /* HSYNC */
3922	RCAR_GP_PIN(1, 17), /* VSYNC */
3923};
3924static const unsigned int vin3_sync_mux[] = {
3925	VI3_HSYNC_N_MARK,
3926	VI3_VSYNC_N_MARK,
3927};
3928static const unsigned int vin3_field_pins[] = {
3929	RCAR_GP_PIN(1, 15),
3930};
3931static const unsigned int vin3_field_mux[] = {
3932	VI3_FIELD_MARK,
3933};
3934static const unsigned int vin3_clkenb_pins[] = {
3935	RCAR_GP_PIN(1, 14),
3936};
3937static const unsigned int vin3_clkenb_mux[] = {
3938	VI3_CLKENB_MARK,
3939};
3940static const unsigned int vin3_clk_pins[] = {
3941	RCAR_GP_PIN(1, 23),
3942};
3943static const unsigned int vin3_clk_mux[] = {
3944	VI3_CLK_MARK,
3945};
3946
3947static const struct sh_pfc_pin_group pinmux_groups[] = {
3948	SH_PFC_PIN_GROUP(audio_clk_a),
3949	SH_PFC_PIN_GROUP(audio_clk_b),
3950	SH_PFC_PIN_GROUP(audio_clk_c),
3951	SH_PFC_PIN_GROUP(audio_clkout),
3952	SH_PFC_PIN_GROUP(audio_clkout_b),
3953	SH_PFC_PIN_GROUP(audio_clkout_c),
3954	SH_PFC_PIN_GROUP(audio_clkout_d),
3955	SH_PFC_PIN_GROUP(avb_link),
3956	SH_PFC_PIN_GROUP(avb_magic),
3957	SH_PFC_PIN_GROUP(avb_phy_int),
3958	SH_PFC_PIN_GROUP(avb_mdio),
3959	SH_PFC_PIN_GROUP(avb_mii),
3960	SH_PFC_PIN_GROUP(avb_gmii),
3961	SH_PFC_PIN_GROUP(du_rgb666),
3962	SH_PFC_PIN_GROUP(du_rgb888),
3963	SH_PFC_PIN_GROUP(du_clk_out_0),
3964	SH_PFC_PIN_GROUP(du_clk_out_1),
3965	SH_PFC_PIN_GROUP(du_sync_0),
3966	SH_PFC_PIN_GROUP(du_sync_1),
3967	SH_PFC_PIN_GROUP(du_cde),
3968	SH_PFC_PIN_GROUP(du0_clk_in),
3969	SH_PFC_PIN_GROUP(du1_clk_in),
3970	SH_PFC_PIN_GROUP(du2_clk_in),
3971	SH_PFC_PIN_GROUP(eth_link),
3972	SH_PFC_PIN_GROUP(eth_magic),
3973	SH_PFC_PIN_GROUP(eth_mdio),
3974	SH_PFC_PIN_GROUP(eth_rmii),
3975	SH_PFC_PIN_GROUP(hscif0_data),
3976	SH_PFC_PIN_GROUP(hscif0_clk),
3977	SH_PFC_PIN_GROUP(hscif0_ctrl),
3978	SH_PFC_PIN_GROUP(hscif0_data_b),
3979	SH_PFC_PIN_GROUP(hscif0_ctrl_b),
3980	SH_PFC_PIN_GROUP(hscif0_data_c),
3981	SH_PFC_PIN_GROUP(hscif0_ctrl_c),
3982	SH_PFC_PIN_GROUP(hscif0_data_d),
3983	SH_PFC_PIN_GROUP(hscif0_ctrl_d),
3984	SH_PFC_PIN_GROUP(hscif0_data_e),
3985	SH_PFC_PIN_GROUP(hscif0_ctrl_e),
3986	SH_PFC_PIN_GROUP(hscif0_data_f),
3987	SH_PFC_PIN_GROUP(hscif0_ctrl_f),
3988	SH_PFC_PIN_GROUP(hscif1_data),
3989	SH_PFC_PIN_GROUP(hscif1_clk),
3990	SH_PFC_PIN_GROUP(hscif1_ctrl),
3991	SH_PFC_PIN_GROUP(hscif1_data_b),
3992	SH_PFC_PIN_GROUP(hscif1_clk_b),
3993	SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3994	SH_PFC_PIN_GROUP(i2c0),
3995	SH_PFC_PIN_GROUP(i2c1),
3996	SH_PFC_PIN_GROUP(i2c1_b),
3997	SH_PFC_PIN_GROUP(i2c1_c),
3998	SH_PFC_PIN_GROUP(i2c2),
3999	SH_PFC_PIN_GROUP(i2c2_b),
4000	SH_PFC_PIN_GROUP(i2c2_c),
4001	SH_PFC_PIN_GROUP(i2c2_d),
4002	SH_PFC_PIN_GROUP(i2c2_e),
4003	SH_PFC_PIN_GROUP(i2c3),
4004	SH_PFC_PIN_GROUP(iic0),
4005	SH_PFC_PIN_GROUP(iic1),
4006	SH_PFC_PIN_GROUP(iic1_b),
4007	SH_PFC_PIN_GROUP(iic1_c),
4008	SH_PFC_PIN_GROUP(iic2),
4009	SH_PFC_PIN_GROUP(iic2_b),
4010	SH_PFC_PIN_GROUP(iic2_c),
4011	SH_PFC_PIN_GROUP(iic2_d),
4012	SH_PFC_PIN_GROUP(iic2_e),
4013	SH_PFC_PIN_GROUP(iic3),
4014	SH_PFC_PIN_GROUP(intc_irq0),
4015	SH_PFC_PIN_GROUP(intc_irq1),
4016	SH_PFC_PIN_GROUP(intc_irq2),
4017	SH_PFC_PIN_GROUP(intc_irq3),
4018	SH_PFC_PIN_GROUP(mlb_3pin),
4019	SH_PFC_PIN_GROUP(mmc0_data1),
4020	SH_PFC_PIN_GROUP(mmc0_data4),
4021	SH_PFC_PIN_GROUP(mmc0_data8),
4022	SH_PFC_PIN_GROUP(mmc0_ctrl),
4023	SH_PFC_PIN_GROUP(mmc1_data1),
4024	SH_PFC_PIN_GROUP(mmc1_data4),
4025	SH_PFC_PIN_GROUP(mmc1_data8),
4026	SH_PFC_PIN_GROUP(mmc1_ctrl),
4027	SH_PFC_PIN_GROUP(msiof0_clk),
4028	SH_PFC_PIN_GROUP(msiof0_sync),
4029	SH_PFC_PIN_GROUP(msiof0_ss1),
4030	SH_PFC_PIN_GROUP(msiof0_ss2),
4031	SH_PFC_PIN_GROUP(msiof0_rx),
4032	SH_PFC_PIN_GROUP(msiof0_tx),
4033	SH_PFC_PIN_GROUP(msiof0_clk_b),
4034	SH_PFC_PIN_GROUP(msiof0_ss1_b),
4035	SH_PFC_PIN_GROUP(msiof0_ss2_b),
4036	SH_PFC_PIN_GROUP(msiof0_rx_b),
4037	SH_PFC_PIN_GROUP(msiof0_tx_b),
4038	SH_PFC_PIN_GROUP(msiof1_clk),
4039	SH_PFC_PIN_GROUP(msiof1_sync),
4040	SH_PFC_PIN_GROUP(msiof1_ss1),
4041	SH_PFC_PIN_GROUP(msiof1_ss2),
4042	SH_PFC_PIN_GROUP(msiof1_rx),
4043	SH_PFC_PIN_GROUP(msiof1_tx),
4044	SH_PFC_PIN_GROUP(msiof1_clk_b),
4045	SH_PFC_PIN_GROUP(msiof1_ss1_b),
4046	SH_PFC_PIN_GROUP(msiof1_ss2_b),
4047	SH_PFC_PIN_GROUP(msiof1_rx_b),
4048	SH_PFC_PIN_GROUP(msiof1_tx_b),
4049	SH_PFC_PIN_GROUP(msiof2_clk),
4050	SH_PFC_PIN_GROUP(msiof2_sync),
4051	SH_PFC_PIN_GROUP(msiof2_ss1),
4052	SH_PFC_PIN_GROUP(msiof2_ss2),
4053	SH_PFC_PIN_GROUP(msiof2_rx),
4054	SH_PFC_PIN_GROUP(msiof2_tx),
4055	SH_PFC_PIN_GROUP(msiof3_clk),
4056	SH_PFC_PIN_GROUP(msiof3_sync),
4057	SH_PFC_PIN_GROUP(msiof3_ss1),
4058	SH_PFC_PIN_GROUP(msiof3_ss2),
4059	SH_PFC_PIN_GROUP(msiof3_rx),
4060	SH_PFC_PIN_GROUP(msiof3_tx),
4061	SH_PFC_PIN_GROUP(msiof3_clk_b),
4062	SH_PFC_PIN_GROUP(msiof3_sync_b),
4063	SH_PFC_PIN_GROUP(msiof3_rx_b),
4064	SH_PFC_PIN_GROUP(msiof3_tx_b),
4065	SH_PFC_PIN_GROUP(pwm0),
4066	SH_PFC_PIN_GROUP(pwm0_b),
4067	SH_PFC_PIN_GROUP(pwm1),
4068	SH_PFC_PIN_GROUP(pwm1_b),
4069	SH_PFC_PIN_GROUP(pwm2),
4070	SH_PFC_PIN_GROUP(pwm3),
4071	SH_PFC_PIN_GROUP(pwm4),
4072	SH_PFC_PIN_GROUP(pwm5),
4073	SH_PFC_PIN_GROUP(pwm6),
4074	SH_PFC_PIN_GROUP(qspi_ctrl),
4075	SH_PFC_PIN_GROUP(qspi_data2),
4076	SH_PFC_PIN_GROUP(qspi_data4),
4077	SH_PFC_PIN_GROUP(scif0_data),
4078	SH_PFC_PIN_GROUP(scif0_clk),
4079	SH_PFC_PIN_GROUP(scif0_ctrl),
4080	SH_PFC_PIN_GROUP(scif0_data_b),
4081	SH_PFC_PIN_GROUP(scif1_data),
4082	SH_PFC_PIN_GROUP(scif1_clk),
4083	SH_PFC_PIN_GROUP(scif1_ctrl),
4084	SH_PFC_PIN_GROUP(scif1_data_b),
4085	SH_PFC_PIN_GROUP(scif1_data_c),
4086	SH_PFC_PIN_GROUP(scif1_data_d),
4087	SH_PFC_PIN_GROUP(scif1_clk_d),
4088	SH_PFC_PIN_GROUP(scif1_data_e),
4089	SH_PFC_PIN_GROUP(scif1_clk_e),
4090	SH_PFC_PIN_GROUP(scif2_data),
4091	SH_PFC_PIN_GROUP(scif2_clk),
4092	SH_PFC_PIN_GROUP(scif2_data_b),
4093	SH_PFC_PIN_GROUP(scifa0_data),
4094	SH_PFC_PIN_GROUP(scifa0_clk),
4095	SH_PFC_PIN_GROUP(scifa0_ctrl),
4096	SH_PFC_PIN_GROUP(scifa0_data_b),
4097	SH_PFC_PIN_GROUP(scifa0_clk_b),
4098	SH_PFC_PIN_GROUP(scifa0_ctrl_b),
4099	SH_PFC_PIN_GROUP(scifa1_data),
4100	SH_PFC_PIN_GROUP(scifa1_clk),
4101	SH_PFC_PIN_GROUP(scifa1_ctrl),
4102	SH_PFC_PIN_GROUP(scifa1_data_b),
4103	SH_PFC_PIN_GROUP(scifa1_clk_b),
4104	SH_PFC_PIN_GROUP(scifa1_ctrl_b),
4105	SH_PFC_PIN_GROUP(scifa1_data_c),
4106	SH_PFC_PIN_GROUP(scifa1_clk_c),
4107	SH_PFC_PIN_GROUP(scifa1_ctrl_c),
4108	SH_PFC_PIN_GROUP(scifa1_data_d),
4109	SH_PFC_PIN_GROUP(scifa1_clk_d),
4110	SH_PFC_PIN_GROUP(scifa1_ctrl_d),
4111	SH_PFC_PIN_GROUP(scifa2_data),
4112	SH_PFC_PIN_GROUP(scifa2_clk),
4113	SH_PFC_PIN_GROUP(scifa2_ctrl),
4114	SH_PFC_PIN_GROUP(scifa2_data_b),
4115	SH_PFC_PIN_GROUP(scifa2_data_c),
4116	SH_PFC_PIN_GROUP(scifa2_clk_c),
4117	SH_PFC_PIN_GROUP(scifb0_data),
4118	SH_PFC_PIN_GROUP(scifb0_clk),
4119	SH_PFC_PIN_GROUP(scifb0_ctrl),
4120	SH_PFC_PIN_GROUP(scifb0_data_b),
4121	SH_PFC_PIN_GROUP(scifb0_clk_b),
4122	SH_PFC_PIN_GROUP(scifb0_ctrl_b),
4123	SH_PFC_PIN_GROUP(scifb0_data_c),
4124	SH_PFC_PIN_GROUP(scifb1_data),
4125	SH_PFC_PIN_GROUP(scifb1_clk),
4126	SH_PFC_PIN_GROUP(scifb1_ctrl),
4127	SH_PFC_PIN_GROUP(scifb1_data_b),
4128	SH_PFC_PIN_GROUP(scifb1_clk_b),
4129	SH_PFC_PIN_GROUP(scifb1_ctrl_b),
4130	SH_PFC_PIN_GROUP(scifb1_data_c),
4131	SH_PFC_PIN_GROUP(scifb1_data_d),
4132	SH_PFC_PIN_GROUP(scifb1_data_e),
4133	SH_PFC_PIN_GROUP(scifb1_clk_e),
4134	SH_PFC_PIN_GROUP(scifb1_data_f),
4135	SH_PFC_PIN_GROUP(scifb1_data_g),
4136	SH_PFC_PIN_GROUP(scifb1_clk_g),
4137	SH_PFC_PIN_GROUP(scifb2_data),
4138	SH_PFC_PIN_GROUP(scifb2_clk),
4139	SH_PFC_PIN_GROUP(scifb2_ctrl),
4140	SH_PFC_PIN_GROUP(scifb2_data_b),
4141	SH_PFC_PIN_GROUP(scifb2_clk_b),
4142	SH_PFC_PIN_GROUP(scifb2_ctrl_b),
4143	SH_PFC_PIN_GROUP(scifb2_data_c),
4144	SH_PFC_PIN_GROUP(scif_clk),
4145	SH_PFC_PIN_GROUP(scif_clk_b),
4146	SH_PFC_PIN_GROUP(sdhi0_data1),
4147	SH_PFC_PIN_GROUP(sdhi0_data4),
4148	SH_PFC_PIN_GROUP(sdhi0_ctrl),
4149	SH_PFC_PIN_GROUP(sdhi0_cd),
4150	SH_PFC_PIN_GROUP(sdhi0_wp),
4151	SH_PFC_PIN_GROUP(sdhi1_data1),
4152	SH_PFC_PIN_GROUP(sdhi1_data4),
4153	SH_PFC_PIN_GROUP(sdhi1_ctrl),
4154	SH_PFC_PIN_GROUP(sdhi1_cd),
4155	SH_PFC_PIN_GROUP(sdhi1_wp),
4156	SH_PFC_PIN_GROUP(sdhi2_data1),
4157	SH_PFC_PIN_GROUP(sdhi2_data4),
4158	SH_PFC_PIN_GROUP(sdhi2_ctrl),
4159	SH_PFC_PIN_GROUP(sdhi2_cd),
4160	SH_PFC_PIN_GROUP(sdhi2_wp),
4161	SH_PFC_PIN_GROUP(sdhi3_data1),
4162	SH_PFC_PIN_GROUP(sdhi3_data4),
4163	SH_PFC_PIN_GROUP(sdhi3_ctrl),
4164	SH_PFC_PIN_GROUP(sdhi3_cd),
4165	SH_PFC_PIN_GROUP(sdhi3_wp),
4166	SH_PFC_PIN_GROUP(ssi0_data),
4167	SH_PFC_PIN_GROUP(ssi0129_ctrl),
4168	SH_PFC_PIN_GROUP(ssi1_data),
4169	SH_PFC_PIN_GROUP(ssi1_ctrl),
4170	SH_PFC_PIN_GROUP(ssi2_data),
4171	SH_PFC_PIN_GROUP(ssi2_ctrl),
4172	SH_PFC_PIN_GROUP(ssi3_data),
4173	SH_PFC_PIN_GROUP(ssi34_ctrl),
4174	SH_PFC_PIN_GROUP(ssi4_data),
4175	SH_PFC_PIN_GROUP(ssi4_ctrl),
4176	SH_PFC_PIN_GROUP(ssi5),
4177	SH_PFC_PIN_GROUP(ssi5_b),
4178	SH_PFC_PIN_GROUP(ssi5_c),
4179	SH_PFC_PIN_GROUP(ssi6),
4180	SH_PFC_PIN_GROUP(ssi6_b),
4181	SH_PFC_PIN_GROUP(ssi7_data),
4182	SH_PFC_PIN_GROUP(ssi7_b_data),
4183	SH_PFC_PIN_GROUP(ssi7_c_data),
4184	SH_PFC_PIN_GROUP(ssi78_ctrl),
4185	SH_PFC_PIN_GROUP(ssi78_b_ctrl),
4186	SH_PFC_PIN_GROUP(ssi78_c_ctrl),
4187	SH_PFC_PIN_GROUP(ssi8_data),
4188	SH_PFC_PIN_GROUP(ssi8_b_data),
4189	SH_PFC_PIN_GROUP(ssi8_c_data),
4190	SH_PFC_PIN_GROUP(ssi9_data),
4191	SH_PFC_PIN_GROUP(ssi9_ctrl),
4192	SH_PFC_PIN_GROUP(tpu0_to0),
4193	SH_PFC_PIN_GROUP(tpu0_to1),
4194	SH_PFC_PIN_GROUP(tpu0_to2),
4195	SH_PFC_PIN_GROUP(tpu0_to3),
4196	SH_PFC_PIN_GROUP(usb0),
4197	SH_PFC_PIN_GROUP(usb0_ovc_vbus),
4198	SH_PFC_PIN_GROUP(usb1),
4199	SH_PFC_PIN_GROUP(usb2),
4200	VIN_DATA_PIN_GROUP(vin0_data, 24),
4201	VIN_DATA_PIN_GROUP(vin0_data, 20),
4202	SH_PFC_PIN_GROUP(vin0_data18),
4203	VIN_DATA_PIN_GROUP(vin0_data, 16),
4204	VIN_DATA_PIN_GROUP(vin0_data, 12),
4205	VIN_DATA_PIN_GROUP(vin0_data, 10),
4206	VIN_DATA_PIN_GROUP(vin0_data, 8),
4207	VIN_DATA_PIN_GROUP(vin0_data, 4),
4208	SH_PFC_PIN_GROUP(vin0_sync),
4209	SH_PFC_PIN_GROUP(vin0_field),
4210	SH_PFC_PIN_GROUP(vin0_clkenb),
4211	SH_PFC_PIN_GROUP(vin0_clk),
4212	VIN_DATA_PIN_GROUP(vin1_data, 24),
4213	VIN_DATA_PIN_GROUP(vin1_data, 20),
4214	SH_PFC_PIN_GROUP(vin1_data18),
4215	VIN_DATA_PIN_GROUP(vin1_data, 16),
4216	VIN_DATA_PIN_GROUP(vin1_data, 12),
4217	VIN_DATA_PIN_GROUP(vin1_data, 10),
4218	VIN_DATA_PIN_GROUP(vin1_data, 8),
4219	VIN_DATA_PIN_GROUP(vin1_data, 4),
4220	SH_PFC_PIN_GROUP(vin1_sync),
4221	SH_PFC_PIN_GROUP(vin1_field),
4222	SH_PFC_PIN_GROUP(vin1_clkenb),
4223	SH_PFC_PIN_GROUP(vin1_clk),
4224	VIN_DATA_PIN_GROUP(vin2_data, 24),
4225	SH_PFC_PIN_GROUP(vin2_data18),
4226	VIN_DATA_PIN_GROUP(vin2_data, 16),
4227	VIN_DATA_PIN_GROUP(vin2_data, 8),
4228	VIN_DATA_PIN_GROUP(vin2_data, 4),
4229	SH_PFC_PIN_GROUP(vin2_sync),
4230	SH_PFC_PIN_GROUP(vin2_field),
4231	SH_PFC_PIN_GROUP(vin2_clkenb),
4232	SH_PFC_PIN_GROUP(vin2_clk),
4233	SH_PFC_PIN_GROUP(vin3_data8),
4234	SH_PFC_PIN_GROUP(vin3_sync),
4235	SH_PFC_PIN_GROUP(vin3_field),
4236	SH_PFC_PIN_GROUP(vin3_clkenb),
4237	SH_PFC_PIN_GROUP(vin3_clk),
4238};
4239
4240static const char * const audio_clk_groups[] = {
4241	"audio_clk_a",
4242	"audio_clk_b",
4243	"audio_clk_c",
4244	"audio_clkout",
4245	"audio_clkout_b",
4246	"audio_clkout_c",
4247	"audio_clkout_d",
4248};
4249
4250static const char * const avb_groups[] = {
4251	"avb_link",
4252	"avb_magic",
4253	"avb_phy_int",
4254	"avb_mdio",
4255	"avb_mii",
4256	"avb_gmii",
4257};
4258
4259static const char * const du_groups[] = {
4260	"du_rgb666",
4261	"du_rgb888",
4262	"du_clk_out_0",
4263	"du_clk_out_1",
4264	"du_sync_0",
4265	"du_sync_1",
4266	"du_cde",
4267};
4268
4269static const char * const du0_groups[] = {
4270	"du0_clk_in",
4271};
4272
4273static const char * const du1_groups[] = {
4274	"du1_clk_in",
4275};
4276
4277static const char * const du2_groups[] = {
4278	"du2_clk_in",
4279};
4280
4281static const char * const eth_groups[] = {
4282	"eth_link",
4283	"eth_magic",
4284	"eth_mdio",
4285	"eth_rmii",
4286};
4287
4288static const char * const hscif0_groups[] = {
4289	"hscif0_data",
4290	"hscif0_clk",
4291	"hscif0_ctrl",
4292	"hscif0_data_b",
4293	"hscif0_ctrl_b",
4294	"hscif0_data_c",
4295	"hscif0_ctrl_c",
4296	"hscif0_data_d",
4297	"hscif0_ctrl_d",
4298	"hscif0_data_e",
4299	"hscif0_ctrl_e",
4300	"hscif0_data_f",
4301	"hscif0_ctrl_f",
4302};
4303
4304static const char * const hscif1_groups[] = {
4305	"hscif1_data",
4306	"hscif1_clk",
4307	"hscif1_ctrl",
4308	"hscif1_data_b",
4309	"hscif1_clk_b",
4310	"hscif1_ctrl_b",
4311};
4312
4313static const char * const i2c0_groups[] = {
4314	"i2c0",
4315};
4316
4317static const char * const i2c1_groups[] = {
4318	"i2c1",
4319	"i2c1_b",
4320	"i2c1_c",
4321};
4322
4323static const char * const i2c2_groups[] = {
4324	"i2c2",
4325	"i2c2_b",
4326	"i2c2_c",
4327	"i2c2_d",
4328	"i2c2_e",
4329};
4330
4331static const char * const i2c3_groups[] = {
4332	"i2c3",
4333};
4334
4335static const char * const iic0_groups[] = {
4336	"iic0",
4337};
4338
4339static const char * const iic1_groups[] = {
4340	"iic1",
4341	"iic1_b",
4342	"iic1_c",
4343};
4344
4345static const char * const iic2_groups[] = {
4346	"iic2",
4347	"iic2_b",
4348	"iic2_c",
4349	"iic2_d",
4350	"iic2_e",
4351};
4352
4353static const char * const iic3_groups[] = {
4354	"iic3",
4355};
4356
4357static const char * const intc_groups[] = {
4358	"intc_irq0",
4359	"intc_irq1",
4360	"intc_irq2",
4361	"intc_irq3",
4362};
4363
4364static const char * const mlb_groups[] = {
4365	"mlb_3pin",
4366};
4367
4368static const char * const mmc0_groups[] = {
4369	"mmc0_data1",
4370	"mmc0_data4",
4371	"mmc0_data8",
4372	"mmc0_ctrl",
4373};
4374
4375static const char * const mmc1_groups[] = {
4376	"mmc1_data1",
4377	"mmc1_data4",
4378	"mmc1_data8",
4379	"mmc1_ctrl",
4380};
4381
4382static const char * const msiof0_groups[] = {
4383	"msiof0_clk",
4384	"msiof0_sync",
4385	"msiof0_ss1",
4386	"msiof0_ss2",
4387	"msiof0_rx",
4388	"msiof0_tx",
4389	"msiof0_clk_b",
4390	"msiof0_ss1_b",
4391	"msiof0_ss2_b",
4392	"msiof0_rx_b",
4393	"msiof0_tx_b",
4394};
4395
4396static const char * const msiof1_groups[] = {
4397	"msiof1_clk",
4398	"msiof1_sync",
4399	"msiof1_ss1",
4400	"msiof1_ss2",
4401	"msiof1_rx",
4402	"msiof1_tx",
4403	"msiof1_clk_b",
4404	"msiof1_ss1_b",
4405	"msiof1_ss2_b",
4406	"msiof1_rx_b",
4407	"msiof1_tx_b",
4408};
4409
4410static const char * const msiof2_groups[] = {
4411	"msiof2_clk",
4412	"msiof2_sync",
4413	"msiof2_ss1",
4414	"msiof2_ss2",
4415	"msiof2_rx",
4416	"msiof2_tx",
4417};
4418
4419static const char * const msiof3_groups[] = {
4420	"msiof3_clk",
4421	"msiof3_sync",
4422	"msiof3_ss1",
4423	"msiof3_ss2",
4424	"msiof3_rx",
4425	"msiof3_tx",
4426	"msiof3_clk_b",
4427	"msiof3_sync_b",
4428	"msiof3_rx_b",
4429	"msiof3_tx_b",
4430};
4431
4432static const char * const pwm0_groups[] = {
4433	"pwm0",
4434	"pwm0_b",
4435};
4436
4437static const char * const pwm1_groups[] = {
4438	"pwm1",
4439	"pwm1_b",
4440};
4441
4442static const char * const pwm2_groups[] = {
4443	"pwm2",
4444};
4445
4446static const char * const pwm3_groups[] = {
4447	"pwm3",
4448};
4449
4450static const char * const pwm4_groups[] = {
4451	"pwm4",
4452};
4453
4454static const char * const pwm5_groups[] = {
4455	"pwm5",
4456};
4457
4458static const char * const pwm6_groups[] = {
4459	"pwm6",
4460};
4461
4462static const char * const qspi_groups[] = {
4463	"qspi_ctrl",
4464	"qspi_data2",
4465	"qspi_data4",
4466};
4467
4468static const char * const scif0_groups[] = {
4469	"scif0_data",
4470	"scif0_clk",
4471	"scif0_ctrl",
4472	"scif0_data_b",
4473};
4474
4475static const char * const scif1_groups[] = {
4476	"scif1_data",
4477	"scif1_clk",
4478	"scif1_ctrl",
4479	"scif1_data_b",
4480	"scif1_data_c",
4481	"scif1_data_d",
4482	"scif1_clk_d",
4483	"scif1_data_e",
4484	"scif1_clk_e",
4485};
4486
4487static const char * const scif2_groups[] = {
4488	"scif2_data",
4489	"scif2_clk",
4490	"scif2_data_b",
4491};
4492
4493static const char * const scifa0_groups[] = {
4494	"scifa0_data",
4495	"scifa0_clk",
4496	"scifa0_ctrl",
4497	"scifa0_data_b",
4498	"scifa0_clk_b",
4499	"scifa0_ctrl_b",
4500};
4501
4502static const char * const scifa1_groups[] = {
4503	"scifa1_data",
4504	"scifa1_clk",
4505	"scifa1_ctrl",
4506	"scifa1_data_b",
4507	"scifa1_clk_b",
4508	"scifa1_ctrl_b",
4509	"scifa1_data_c",
4510	"scifa1_clk_c",
4511	"scifa1_ctrl_c",
4512	"scifa1_data_d",
4513	"scifa1_clk_d",
4514	"scifa1_ctrl_d",
4515};
4516
4517static const char * const scifa2_groups[] = {
4518	"scifa2_data",
4519	"scifa2_clk",
4520	"scifa2_ctrl",
4521	"scifa2_data_b",
4522	"scifa2_data_c",
4523	"scifa2_clk_c",
4524};
4525
4526static const char * const scifb0_groups[] = {
4527	"scifb0_data",
4528	"scifb0_clk",
4529	"scifb0_ctrl",
4530	"scifb0_data_b",
4531	"scifb0_clk_b",
4532	"scifb0_ctrl_b",
4533	"scifb0_data_c",
4534};
4535
4536static const char * const scifb1_groups[] = {
4537	"scifb1_data",
4538	"scifb1_clk",
4539	"scifb1_ctrl",
4540	"scifb1_data_b",
4541	"scifb1_clk_b",
4542	"scifb1_ctrl_b",
4543	"scifb1_data_c",
4544	"scifb1_data_d",
4545	"scifb1_data_e",
4546	"scifb1_clk_e",
4547	"scifb1_data_f",
4548	"scifb1_data_g",
4549	"scifb1_clk_g",
4550};
4551
4552static const char * const scifb2_groups[] = {
4553	"scifb2_data",
4554	"scifb2_clk",
4555	"scifb2_ctrl",
4556	"scifb2_data_b",
4557	"scifb2_clk_b",
4558	"scifb2_ctrl_b",
4559	"scifb2_data_c",
4560};
4561
4562static const char * const scif_clk_groups[] = {
4563	"scif_clk",
4564	"scif_clk_b",
4565};
4566
4567static const char * const sdhi0_groups[] = {
4568	"sdhi0_data1",
4569	"sdhi0_data4",
4570	"sdhi0_ctrl",
4571	"sdhi0_cd",
4572	"sdhi0_wp",
4573};
4574
4575static const char * const sdhi1_groups[] = {
4576	"sdhi1_data1",
4577	"sdhi1_data4",
4578	"sdhi1_ctrl",
4579	"sdhi1_cd",
4580	"sdhi1_wp",
4581};
4582
4583static const char * const sdhi2_groups[] = {
4584	"sdhi2_data1",
4585	"sdhi2_data4",
4586	"sdhi2_ctrl",
4587	"sdhi2_cd",
4588	"sdhi2_wp",
4589};
4590
4591static const char * const sdhi3_groups[] = {
4592	"sdhi3_data1",
4593	"sdhi3_data4",
4594	"sdhi3_ctrl",
4595	"sdhi3_cd",
4596	"sdhi3_wp",
4597};
4598
4599static const char * const ssi_groups[] = {
4600	"ssi0_data",
4601	"ssi0129_ctrl",
4602	"ssi1_data",
4603	"ssi1_ctrl",
4604	"ssi2_data",
4605	"ssi2_ctrl",
4606	"ssi3_data",
4607	"ssi34_ctrl",
4608	"ssi4_data",
4609	"ssi4_ctrl",
4610	"ssi5",
4611	"ssi5_b",
4612	"ssi5_c",
4613	"ssi6",
4614	"ssi6_b",
4615	"ssi7_data",
4616	"ssi7_b_data",
4617	"ssi7_c_data",
4618	"ssi78_ctrl",
4619	"ssi78_b_ctrl",
4620	"ssi78_c_ctrl",
4621	"ssi8_data",
4622	"ssi8_b_data",
4623	"ssi8_c_data",
4624	"ssi9_data",
4625	"ssi9_ctrl",
4626};
4627
4628static const char * const tpu0_groups[] = {
4629	"tpu0_to0",
4630	"tpu0_to1",
4631	"tpu0_to2",
4632	"tpu0_to3",
4633};
4634
4635static const char * const usb0_groups[] = {
4636	"usb0",
4637	"usb0_ovc_vbus",
4638};
4639
4640static const char * const usb1_groups[] = {
4641	"usb1",
4642};
4643
4644static const char * const usb2_groups[] = {
4645	"usb2",
4646};
4647
4648static const char * const vin0_groups[] = {
4649	"vin0_data24",
4650	"vin0_data20",
4651	"vin0_data18",
4652	"vin0_data16",
4653	"vin0_data12",
4654	"vin0_data10",
4655	"vin0_data8",
4656	"vin0_data4",
4657	"vin0_sync",
4658	"vin0_field",
4659	"vin0_clkenb",
4660	"vin0_clk",
4661};
4662
4663static const char * const vin1_groups[] = {
4664	"vin1_data24",
4665	"vin1_data20",
4666	"vin1_data18",
4667	"vin1_data16",
4668	"vin1_data12",
4669	"vin1_data10",
4670	"vin1_data8",
4671	"vin1_data4",
4672	"vin1_sync",
4673	"vin1_field",
4674	"vin1_clkenb",
4675	"vin1_clk",
4676};
4677
4678static const char * const vin2_groups[] = {
4679	"vin2_data24",
4680	"vin2_data18",
4681	"vin2_data16",
4682	"vin2_data8",
4683	"vin2_data4",
4684	"vin2_sync",
4685	"vin2_field",
4686	"vin2_clkenb",
4687	"vin2_clk",
4688};
4689
4690static const char * const vin3_groups[] = {
4691	"vin3_data8",
4692	"vin3_sync",
4693	"vin3_field",
4694	"vin3_clkenb",
4695	"vin3_clk",
4696};
4697
4698static const struct sh_pfc_function pinmux_functions[] = {
4699	SH_PFC_FUNCTION(audio_clk),
4700	SH_PFC_FUNCTION(avb),
4701	SH_PFC_FUNCTION(du),
4702	SH_PFC_FUNCTION(du0),
4703	SH_PFC_FUNCTION(du1),
4704	SH_PFC_FUNCTION(du2),
4705	SH_PFC_FUNCTION(eth),
4706	SH_PFC_FUNCTION(hscif0),
4707	SH_PFC_FUNCTION(hscif1),
4708	SH_PFC_FUNCTION(i2c0),
4709	SH_PFC_FUNCTION(i2c1),
4710	SH_PFC_FUNCTION(i2c2),
4711	SH_PFC_FUNCTION(i2c3),
4712	SH_PFC_FUNCTION(iic0),
4713	SH_PFC_FUNCTION(iic1),
4714	SH_PFC_FUNCTION(iic2),
4715	SH_PFC_FUNCTION(iic3),
4716	SH_PFC_FUNCTION(intc),
4717	SH_PFC_FUNCTION(mlb),
4718	SH_PFC_FUNCTION(mmc0),
4719	SH_PFC_FUNCTION(mmc1),
4720	SH_PFC_FUNCTION(msiof0),
4721	SH_PFC_FUNCTION(msiof1),
4722	SH_PFC_FUNCTION(msiof2),
4723	SH_PFC_FUNCTION(msiof3),
4724	SH_PFC_FUNCTION(pwm0),
4725	SH_PFC_FUNCTION(pwm1),
4726	SH_PFC_FUNCTION(pwm2),
4727	SH_PFC_FUNCTION(pwm3),
4728	SH_PFC_FUNCTION(pwm4),
4729	SH_PFC_FUNCTION(pwm5),
4730	SH_PFC_FUNCTION(pwm6),
4731	SH_PFC_FUNCTION(qspi),
4732	SH_PFC_FUNCTION(scif0),
4733	SH_PFC_FUNCTION(scif1),
4734	SH_PFC_FUNCTION(scif2),
4735	SH_PFC_FUNCTION(scifa0),
4736	SH_PFC_FUNCTION(scifa1),
4737	SH_PFC_FUNCTION(scifa2),
4738	SH_PFC_FUNCTION(scifb0),
4739	SH_PFC_FUNCTION(scifb1),
4740	SH_PFC_FUNCTION(scifb2),
4741	SH_PFC_FUNCTION(scif_clk),
4742	SH_PFC_FUNCTION(sdhi0),
4743	SH_PFC_FUNCTION(sdhi1),
4744	SH_PFC_FUNCTION(sdhi2),
4745	SH_PFC_FUNCTION(sdhi3),
4746	SH_PFC_FUNCTION(ssi),
4747	SH_PFC_FUNCTION(tpu0),
4748	SH_PFC_FUNCTION(usb0),
4749	SH_PFC_FUNCTION(usb1),
4750	SH_PFC_FUNCTION(usb2),
4751	SH_PFC_FUNCTION(vin0),
4752	SH_PFC_FUNCTION(vin1),
4753	SH_PFC_FUNCTION(vin2),
4754	SH_PFC_FUNCTION(vin3),
4755};
4756
4757static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4758	{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
4759		GP_0_31_FN, FN_IP3_17_15,
4760		GP_0_30_FN, FN_IP3_14_12,
4761		GP_0_29_FN, FN_IP3_11_8,
4762		GP_0_28_FN, FN_IP3_7_4,
4763		GP_0_27_FN, FN_IP3_3_0,
4764		GP_0_26_FN, FN_IP2_28_26,
4765		GP_0_25_FN, FN_IP2_25_22,
4766		GP_0_24_FN, FN_IP2_21_18,
4767		GP_0_23_FN, FN_IP2_17_15,
4768		GP_0_22_FN, FN_IP2_14_12,
4769		GP_0_21_FN, FN_IP2_11_9,
4770		GP_0_20_FN, FN_IP2_8_6,
4771		GP_0_19_FN, FN_IP2_5_3,
4772		GP_0_18_FN, FN_IP2_2_0,
4773		GP_0_17_FN, FN_IP1_29_28,
4774		GP_0_16_FN, FN_IP1_27_26,
4775		GP_0_15_FN, FN_IP1_25_22,
4776		GP_0_14_FN, FN_IP1_21_18,
4777		GP_0_13_FN, FN_IP1_17_15,
4778		GP_0_12_FN, FN_IP1_14_12,
4779		GP_0_11_FN, FN_IP1_11_8,
4780		GP_0_10_FN, FN_IP1_7_4,
4781		GP_0_9_FN, FN_IP1_3_0,
4782		GP_0_8_FN, FN_IP0_30_27,
4783		GP_0_7_FN, FN_IP0_26_23,
4784		GP_0_6_FN, FN_IP0_22_20,
4785		GP_0_5_FN, FN_IP0_19_16,
4786		GP_0_4_FN, FN_IP0_15_12,
4787		GP_0_3_FN, FN_IP0_11_9,
4788		GP_0_2_FN, FN_IP0_8_6,
4789		GP_0_1_FN, FN_IP0_5_3,
4790		GP_0_0_FN, FN_IP0_2_0 }
4791	},
4792	{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
4793		0, 0,
4794		0, 0,
4795		GP_1_29_FN, FN_IP6_13_11,
4796		GP_1_28_FN, FN_IP6_10_9,
4797		GP_1_27_FN, FN_IP6_8_6,
4798		GP_1_26_FN, FN_IP6_5_3,
4799		GP_1_25_FN, FN_IP6_2_0,
4800		GP_1_24_FN, FN_IP5_29_27,
4801		GP_1_23_FN, FN_IP5_26_24,
4802		GP_1_22_FN, FN_IP5_23_21,
4803		GP_1_21_FN, FN_IP5_20_18,
4804		GP_1_20_FN, FN_IP5_17_15,
4805		GP_1_19_FN, FN_IP5_14_13,
4806		GP_1_18_FN, FN_IP5_12_10,
4807		GP_1_17_FN, FN_IP5_9_6,
4808		GP_1_16_FN, FN_IP5_5_3,
4809		GP_1_15_FN, FN_IP5_2_0,
4810		GP_1_14_FN, FN_IP4_29_27,
4811		GP_1_13_FN, FN_IP4_26_24,
4812		GP_1_12_FN, FN_IP4_23_21,
4813		GP_1_11_FN, FN_IP4_20_18,
4814		GP_1_10_FN, FN_IP4_17_15,
4815		GP_1_9_FN, FN_IP4_14_12,
4816		GP_1_8_FN, FN_IP4_11_9,
4817		GP_1_7_FN, FN_IP4_8_6,
4818		GP_1_6_FN, FN_IP4_5_3,
4819		GP_1_5_FN, FN_IP4_2_0,
4820		GP_1_4_FN, FN_IP3_31_29,
4821		GP_1_3_FN, FN_IP3_28_26,
4822		GP_1_2_FN, FN_IP3_25_23,
4823		GP_1_1_FN, FN_IP3_22_20,
4824		GP_1_0_FN, FN_IP3_19_18, }
4825	},
4826	{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
4827		0, 0,
4828		0, 0,
4829		GP_2_29_FN, FN_IP7_15_13,
4830		GP_2_28_FN, FN_IP7_12_10,
4831		GP_2_27_FN, FN_IP7_9_8,
4832		GP_2_26_FN, FN_IP7_7_6,
4833		GP_2_25_FN, FN_IP7_5_3,
4834		GP_2_24_FN, FN_IP7_2_0,
4835		GP_2_23_FN, FN_IP6_31_29,
4836		GP_2_22_FN, FN_IP6_28_26,
4837		GP_2_21_FN, FN_IP6_25_23,
4838		GP_2_20_FN, FN_IP6_22_20,
4839		GP_2_19_FN, FN_IP6_19_17,
4840		GP_2_18_FN, FN_IP6_16_14,
4841		GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
4842		GP_2_16_FN, FN_IP8_27,
4843		GP_2_15_FN, FN_IP8_26,
4844		GP_2_14_FN, FN_IP8_25_24,
4845		GP_2_13_FN, FN_IP8_23_22,
4846		GP_2_12_FN, FN_IP8_21_20,
4847		GP_2_11_FN, FN_IP8_19_18,
4848		GP_2_10_FN, FN_IP8_17_16,
4849		GP_2_9_FN, FN_IP8_15_14,
4850		GP_2_8_FN, FN_IP8_13_12,
4851		GP_2_7_FN, FN_IP8_11_10,
4852		GP_2_6_FN, FN_IP8_9_8,
4853		GP_2_5_FN, FN_IP8_7_6,
4854		GP_2_4_FN, FN_IP8_5_4,
4855		GP_2_3_FN, FN_IP8_3_2,
4856		GP_2_2_FN, FN_IP8_1_0,
4857		GP_2_1_FN, FN_IP7_30_29,
4858		GP_2_0_FN, FN_IP7_28_27 }
4859	},
4860	{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
4861		GP_3_31_FN, FN_IP11_21_18,
4862		GP_3_30_FN, FN_IP11_17_15,
4863		GP_3_29_FN, FN_IP11_14_13,
4864		GP_3_28_FN, FN_IP11_12_11,
4865		GP_3_27_FN, FN_IP11_10_9,
4866		GP_3_26_FN, FN_IP11_8_7,
4867		GP_3_25_FN, FN_IP11_6_5,
4868		GP_3_24_FN, FN_IP11_4,
4869		GP_3_23_FN, FN_IP11_3_0,
4870		GP_3_22_FN, FN_IP10_29_26,
4871		GP_3_21_FN, FN_IP10_25_23,
4872		GP_3_20_FN, FN_IP10_22_19,
4873		GP_3_19_FN, FN_IP10_18_15,
4874		GP_3_18_FN, FN_IP10_14_11,
4875		GP_3_17_FN, FN_IP10_10_7,
4876		GP_3_16_FN, FN_IP10_6_4,
4877		GP_3_15_FN, FN_IP10_3_0,
4878		GP_3_14_FN, FN_IP9_31_28,
4879		GP_3_13_FN, FN_IP9_27_26,
4880		GP_3_12_FN, FN_IP9_25_24,
4881		GP_3_11_FN, FN_IP9_23_22,
4882		GP_3_10_FN, FN_IP9_21_20,
4883		GP_3_9_FN, FN_IP9_19_18,
4884		GP_3_8_FN, FN_IP9_17_16,
4885		GP_3_7_FN, FN_IP9_15_12,
4886		GP_3_6_FN, FN_IP9_11_8,
4887		GP_3_5_FN, FN_IP9_7_6,
4888		GP_3_4_FN, FN_IP9_5_4,
4889		GP_3_3_FN, FN_IP9_3_2,
4890		GP_3_2_FN, FN_IP9_1_0,
4891		GP_3_1_FN, FN_IP8_30_29,
4892		GP_3_0_FN, FN_IP8_28 }
4893	},
4894	{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
4895		GP_4_31_FN, FN_IP14_18_16,
4896		GP_4_30_FN, FN_IP14_15_12,
4897		GP_4_29_FN, FN_IP14_11_9,
4898		GP_4_28_FN, FN_IP14_8_6,
4899		GP_4_27_FN, FN_IP14_5_3,
4900		GP_4_26_FN, FN_IP14_2_0,
4901		GP_4_25_FN, FN_IP13_30_29,
4902		GP_4_24_FN, FN_IP13_28_26,
4903		GP_4_23_FN, FN_IP13_25_23,
4904		GP_4_22_FN, FN_IP13_22_19,
4905		GP_4_21_FN, FN_IP13_18_16,
4906		GP_4_20_FN, FN_IP13_15_13,
4907		GP_4_19_FN, FN_IP13_12_10,
4908		GP_4_18_FN, FN_IP13_9_7,
4909		GP_4_17_FN, FN_IP13_6_3,
4910		GP_4_16_FN, FN_IP13_2_0,
4911		GP_4_15_FN, FN_IP12_30_28,
4912		GP_4_14_FN, FN_IP12_27_25,
4913		GP_4_13_FN, FN_IP12_24_23,
4914		GP_4_12_FN, FN_IP12_22_20,
4915		GP_4_11_FN, FN_IP12_19_17,
4916		GP_4_10_FN, FN_IP12_16_14,
4917		GP_4_9_FN, FN_IP12_13_11,
4918		GP_4_8_FN, FN_IP12_10_8,
4919		GP_4_7_FN, FN_IP12_7_6,
4920		GP_4_6_FN, FN_IP12_5_4,
4921		GP_4_5_FN, FN_IP12_3_2,
4922		GP_4_4_FN, FN_IP12_1_0,
4923		GP_4_3_FN, FN_IP11_31_30,
4924		GP_4_2_FN, FN_IP11_29_27,
4925		GP_4_1_FN, FN_IP11_26_24,
4926		GP_4_0_FN, FN_IP11_23_22 }
4927	},
4928	{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
4929		GP_5_31_FN, FN_IP7_24_22,
4930		GP_5_30_FN, FN_IP7_21_19,
4931		GP_5_29_FN, FN_IP7_18_16,
4932		GP_5_28_FN, FN_DU_DOTCLKIN2,
4933		GP_5_27_FN, FN_IP7_26_25,
4934		GP_5_26_FN, FN_DU_DOTCLKIN0,
4935		GP_5_25_FN, FN_AVS2,
4936		GP_5_24_FN, FN_AVS1,
4937		GP_5_23_FN, FN_USB2_OVC,
4938		GP_5_22_FN, FN_USB2_PWEN,
4939		GP_5_21_FN, FN_IP16_7,
4940		GP_5_20_FN, FN_IP16_6,
4941		GP_5_19_FN, FN_USB0_OVC_VBUS,
4942		GP_5_18_FN, FN_USB0_PWEN,
4943		GP_5_17_FN, FN_IP16_5_3,
4944		GP_5_16_FN, FN_IP16_2_0,
4945		GP_5_15_FN, FN_IP15_29_28,
4946		GP_5_14_FN, FN_IP15_27_26,
4947		GP_5_13_FN, FN_IP15_25_23,
4948		GP_5_12_FN, FN_IP15_22_20,
4949		GP_5_11_FN, FN_IP15_19_18,
4950		GP_5_10_FN, FN_IP15_17_16,
4951		GP_5_9_FN, FN_IP15_15_14,
4952		GP_5_8_FN, FN_IP15_13_12,
4953		GP_5_7_FN, FN_IP15_11_9,
4954		GP_5_6_FN, FN_IP15_8_6,
4955		GP_5_5_FN, FN_IP15_5_3,
4956		GP_5_4_FN, FN_IP15_2_0,
4957		GP_5_3_FN, FN_IP14_30_28,
4958		GP_5_2_FN, FN_IP14_27_25,
4959		GP_5_1_FN, FN_IP14_24_22,
4960		GP_5_0_FN, FN_IP14_21_19 }
4961	},
4962	{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4963			     1, 4, 4, 3, 4, 4, 3, 3, 3, 3) {
4964		/* IP0_31 [1] */
4965		0, 0,
4966		/* IP0_30_27 [4] */
4967		FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0,
4968		FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
4969		0, 0, 0, 0, 0, 0, 0, 0, 0,
4970		/* IP0_26_23 [4] */
4971		FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
4972		FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C,
4973		FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0,
4974		/* IP0_22_20 [3] */
4975		FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
4976		FN_I2C2_SCL_C, 0, 0,
4977		/* IP0_19_16 [4] */
4978		FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
4979		FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B,
4980		0, 0, 0, 0, 0, 0, 0, 0, 0,
4981		/* IP0_15_12 [4] */
4982		FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
4983		FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B,
4984		0, 0, 0, 0, 0, 0, 0, 0, 0,
4985		/* IP0_11_9 [3] */
4986		FN_D3, FN_MSIOF3_TXD_B,	FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B,
4987		0, 0, 0,
4988		/* IP0_8_6 [3] */
4989		FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B,
4990		0, 0, 0,
4991		/* IP0_5_3 [3] */
4992		FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B,
4993		0, 0, 0,
4994		/* IP0_2_0 [3] */
4995		FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
4996		0, 0, 0, }
4997	},
4998	{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4999			     2, 2, 2, 4, 4, 3, 3, 4, 4, 4) {
5000		/* IP1_31_30 [2] */
5001		0, 0, 0, 0,
5002		/* IP1_29_28 [2] */
5003		FN_A1, FN_PWM4, 0, 0,
5004		/* IP1_27_26 [2] */
5005		FN_A0, FN_PWM3, 0, 0,
5006		/* IP1_25_22 [4] */
5007		FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
5008		FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
5009		0, 0, 0, 0, 0, 0, 0, 0, 0,
5010		/* IP1_21_18 [4] */
5011		FN_D14,	FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
5012		FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
5013		0, 0, 0, 0, 0, 0, 0, 0, 0,
5014		/* IP1_17_15 [3] */
5015		FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
5016		FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5,
5017		0, 0, 0,
5018		/* IP1_14_12 [3] */
5019		FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
5020		FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
5021		0, 0,
5022		/* IP1_11_8 [4] */
5023		FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0,
5024		FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
5025		0, 0, 0, 0, 0, 0, 0, 0, 0,
5026		/* IP1_7_4 [4] */
5027		FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0,
5028		FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,
5029		0, 0, 0, 0, 0, 0, 0, 0, 0,
5030		/* IP1_3_0 [4] */
5031		FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0,
5032		FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
5033		0, 0, 0, 0, 0, 0, 0, 0, 0, }
5034	},
5035	{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5036			     3, 3, 4, 4, 3, 3, 3, 3, 3, 3) {
5037		/* IP2_31_29 [3] */
5038		0, 0, 0, 0, 0, 0, 0, 0,
5039		/* IP2_28_26 [3] */
5040		FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
5041		FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
5042		/* IP2_25_22 [4] */
5043		FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
5044		FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
5045		0, 0, 0, 0, 0, 0, 0, 0,
5046		/* IP2_21_18 [4] */
5047		FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
5048		FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
5049		0, 0, 0, 0, 0, 0, 0, 0,
5050		/* IP2_17_15 [3] */
5051		FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
5052		0, 0, 0, 0,
5053		/* IP2_14_12 [3] */
5054		FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0,
5055		/* IP2_11_9 [3] */
5056		FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0,
5057		/* IP2_8_6 [3] */
5058		FN_A4, FN_MSIOF1_TXD_B,	FN_TPU0TO0, 0, 0, 0, 0, 0,
5059		/* IP2_5_3 [3] */
5060		FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
5061		/* IP2_2_0 [3] */
5062		FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0,	}
5063	},
5064	{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5065			     3, 3, 3, 3, 2, 3, 3, 4, 4, 4) {
5066		/* IP3_31_29 [3] */
5067		FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
5068		0, 0, 0,
5069		/* IP3_28_26 [3] */
5070		FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B,
5071		0, 0, 0, 0,
5072		/* IP3_25_23 [3] */
5073		FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0,
5074		/* IP3_22_20 [3] */
5075		FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0,
5076		/* IP3_19_18 [2] */
5077		FN_A16, FN_ATAWR1_N, 0, 0,
5078		/* IP3_17_15 [3] */
5079		FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2,
5080		0, 0, 0, 0,
5081		/* IP3_14_12 [3] */
5082		FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1,
5083		0, 0, 0, 0,
5084		/* IP3_11_8 [4] */
5085		FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
5086		FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
5087		FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0,
5088		/* IP3_7_4 [4] */
5089		FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
5090		FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
5091		0, 0, 0, 0, 0, 0, 0, 0, 0,
5092		/* IP3_3_0 [4] */
5093		FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
5094		FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
5095		0, 0, 0, 0, 0, 0, 0, 0, }
5096	},
5097	{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5098			     2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
5099		/* IP4_31_30 [2] */
5100		0, 0, 0, 0,
5101		/* IP4_29_27 [3] */
5102		FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
5103		FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
5104		/* IP4_26_24 [3] */
5105		FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD,
5106		FN_VI1_FIELD_B, FN_VI2_R1, 0, 0,
5107		/* IP4_23_21 [3] */
5108		FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0,
5109		FN_HTX0_B, FN_MSIOF0_SS1_B, 0,
5110		/* IP4_20_18 [3] */
5111		FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
5112		FN_VI2_CLK, FN_VI2_CLK_B, 0, 0,
5113		/* IP4_17_15 [3] */
5114		FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
5115		0, 0, 0,
5116		/* IP4_14_12 [3] */
5117		FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD,
5118		FN_VI2_FIELD_B, 0, 0,
5119		/* IP4_11_9 [3] */
5120		FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
5121		FN_VI2_CLKENB_B, 0, 0,
5122		/* IP4_8_6 [3] */
5123		FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0,
5124		/* IP4_5_3 [3] */
5125		FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
5126		/* IP4_2_0 [3] */
5127		FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
5128		}
5129	},
5130	{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5131			     2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) {
5132		/* IP5_31_30 [2] */
5133		0, 0, 0, 0,
5134		/* IP5_29_27 [3] */
5135		FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
5136		FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
5137		/* IP5_26_24 [3] */
5138		FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
5139		FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
5140		FN_MSIOF0_SCK_B, 0,
5141		/* IP5_23_21 [3] */
5142		FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
5143		FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C,
5144		/* IP5_20_18 [3] */
5145		FN_WE0_N, FN_IECLK, FN_CAN_CLK,
5146		FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
5147		/* IP5_17_15 [3] */
5148		FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
5149		FN_INTC_IRQ4_N, 0, 0,
5150		/* IP5_14_13 [2] */
5151		FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
5152		/* IP5_12_10 [3] */
5153		FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C,
5154		0, 0,
5155		/* IP5_9_6 [4] */
5156		FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N,
5157		FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
5158		FN_I2C1_SDA, 0, 0, 0, 0, 0, 0,
5159		/* IP5_5_3 [3] */
5160		FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
5161		FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
5162		FN_INTC_EN0_N, FN_I2C1_SCL,
5163		/* IP5_2_0 [3] */
5164		FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
5165		FN_VI2_R3, 0, 0, }
5166	},
5167	{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5168			     3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
5169		/* IP6_31_29 [3] */
5170		FN_ETH_REF_CLK, 0, FN_HCTS0_N_E,
5171		FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
5172		/* IP6_28_26 [3] */
5173		FN_ETH_LINK, 0, FN_HTX0_E,
5174		FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
5175		/* IP6_25_23 [3] */
5176		FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B,
5177		FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
5178		/* IP6_22_20 [3] */
5179		FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
5180		FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
5181		/* IP6_19_17 [3] */
5182		FN_ETH_RX_ER, 0, FN_STP_ISD_0_B,
5183		FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0,
5184		/* IP6_16_14 [3] */
5185		FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B,
5186		FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
5187		FN_I2C2_SCL_E, 0,
5188		/* IP6_13_11 [3] */
5189		FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
5190		FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
5191		/* IP6_10_9 [2] */
5192		FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
5193		/* IP6_8_6 [3] */
5194		FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
5195		FN_SSI_SDATA8_C, 0, 0, 0,
5196		/* IP6_5_3 [3] */
5197		FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
5198		FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
5199		/* IP6_2_0 [3] */
5200		FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
5201		FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, }
5202	},
5203	{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5204			     1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
5205		/* IP7_31 [1] */
5206		0, 0,
5207		/* IP7_30_29 [2] */
5208		FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0,
5209		/* IP7_28_27 [2] */
5210		FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0,
5211		/* IP7_26_25 [2] */
5212		FN_DU_DOTCLKIN1, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
5213		/* IP7_24_22 [3] */
5214		FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
5215		0, 0, 0,
5216		/* IP7_21_19 [3] */
5217		FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
5218		FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
5219		/* IP7_18_16 [3] */
5220		FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
5221		FN_GLO_SS_C, 0, 0, 0,
5222		/* IP7_15_13 [3] */
5223		FN_ETH_MDC, 0, FN_STP_ISD_1_B,
5224		FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
5225		/* IP7_12_10 [3] */
5226		FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
5227		FN_GLO_SCLK_C, 0, 0, 0,
5228		/* IP7_9_8 [2] */
5229		FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0,
5230		/* IP7_7_6 [2] */
5231		FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F,
5232		/* IP7_5_3 [3] */
5233		FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0,
5234		/* IP7_2_0 [3] */
5235		FN_ETH_MDIO, 0, FN_HRTS0_N_E,
5236		FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
5237	},
5238	{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5239			     1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2,
5240			     2, 2, 2, 2, 2, 2, 2) {
5241		/* IP8_31 [1] */
5242		0, 0,
5243		/* IP8_30_29 [2] */
5244		FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
5245		/* IP8_28 [1] */
5246		FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
5247		/* IP8_27 [1] */
5248		FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
5249		/* IP8_26 [1] */
5250		FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
5251		/* IP8_25_24 [2] */
5252		FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
5253		FN_AVB_MAGIC, 0,
5254		/* IP8_23_22 [2] */
5255		FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
5256		/* IP8_21_20 [2] */
5257		FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0,
5258		/* IP8_19_18 [2] */
5259		FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0,
5260		/* IP8_17_16 [2] */
5261		FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0,
5262		/* IP8_15_14 [2] */
5263		FN_VI1_CLK, FN_AVB_RX_DV, 0, 0,
5264		/* IP8_13_12 [2] */
5265		FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0,
5266		/* IP8_11_10 [2] */
5267		FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0,
5268		/* IP8_9_8 [2] */
5269		FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
5270		/* IP8_7_6 [2] */
5271		FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
5272		/* IP8_5_4 [2] */
5273		FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
5274		/* IP8_3_2 [2] */
5275		FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
5276		/* IP8_1_0 [2] */
5277		FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, }
5278	},
5279	{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
5280			     4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
5281		/* IP9_31_28 [4] */
5282		FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
5283		FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D,
5284		FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
5285		/* IP9_27_26 [2] */
5286		FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B,
5287		/* IP9_25_24 [2] */
5288		FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B,
5289		/* IP9_23_22 [2] */
5290		FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B,
5291		/* IP9_21_20 [2] */
5292		FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B,
5293		/* IP9_19_18 [2] */
5294		FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B,
5295		/* IP9_17_16 [2] */
5296		FN_SD1_CLK, FN_AVB_TX_EN, 0, 0,
5297		/* IP9_15_12 [4] */
5298		FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
5299		FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
5300		FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
5301		/* IP9_11_8 [4] */
5302		FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
5303		FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
5304		FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
5305		/* IP9_7_6 [2] */
5306		FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
5307		/* IP9_5_4 [2] */
5308		FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
5309		/* IP9_3_2 [2] */
5310		FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
5311		/* IP9_1_0 [2] */
5312		FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, }
5313	},
5314	{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
5315			     2, 4, 3, 4, 4, 4, 4, 3, 4) {
5316		/* IP10_31_30 [2] */
5317		0, 0, 0, 0,
5318		/* IP10_29_26 [4] */
5319		FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
5320		FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
5321		FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
5322		/* IP10_25_23 [3] */
5323		FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
5324		FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
5325		/* IP10_22_19 [4] */
5326		FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0,
5327		FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
5328		FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
5329		/* IP10_18_15 [4] */
5330		FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0,
5331		FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
5332		FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
5333		0, 0, 0, 0, 0, 0,
5334		/* IP10_14_11 [4] */
5335		FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
5336		FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
5337		FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
5338		0, 0, 0, 0, 0, 0, 0,
5339		/* IP10_10_7 [4] */
5340		FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
5341		FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
5342		FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
5343		0, 0, 0, 0, 0, 0, 0,
5344		/* IP10_6_4 [3] */
5345		FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
5346		FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
5347		FN_VI3_DATA0_B, 0,
5348		/* IP10_3_0 [4] */
5349		FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
5350		FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
5351		FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, }
5352	},
5353	{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
5354			     2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) {
5355		/* IP11_31_30 [2] */
5356		FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
5357		/* IP11_29_27 [3] */
5358		FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
5359		0, 0, 0,
5360		/* IP11_26_24 [3] */
5361		FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B,
5362		0, 0, 0,
5363		/* IP11_23_22 [2] */
5364		FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0,
5365		/* IP11_21_18 [4] */
5366		FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
5367		0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0,
5368		/* IP11_17_15 [3] */
5369		FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
5370		FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
5371		/* IP11_14_13 [2] */
5372		FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
5373		/* IP11_12_11 [2] */
5374		FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
5375		/* IP11_10_9 [2] */
5376		FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
5377		/* IP11_8_7 [2] */
5378		FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
5379		/* IP11_6_5 [2] */
5380		FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
5381		/* IP11_4 [1] */
5382		FN_SD3_CLK, FN_MMC1_CLK,
5383		/* IP11_3_0 [4] */
5384		FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
5385		FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
5386		FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, }
5387	},
5388	{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
5389			     1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
5390		/* IP12_31 [1] */
5391		0, 0,
5392		/* IP12_30_28 [3] */
5393		FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
5394		FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
5395		FN_CAN_DEBUGOUT4, 0, 0,
5396		/* IP12_27_25 [3] */
5397		FN_SSI_SCK5, FN_SCIFB1_SCK,
5398		FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
5399		FN_CAN_DEBUGOUT3, 0, 0,
5400		/* IP12_24_23 [2] */
5401		FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
5402		FN_CAN_DEBUGOUT2,
5403		/* IP12_22_20 [3] */
5404		FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
5405		FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0,
5406		/* IP12_19_17 [3] */
5407		FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
5408		FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0,
5409		/* IP12_16_14 [3] */
5410		FN_SSI_SDATA3, FN_STP_ISCLK_0,
5411		FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0,
5412		/* IP12_13_11 [3] */
5413		FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
5414		FN_CAN_STEP0, 0, 0, 0,
5415		/* IP12_10_8 [3] */
5416		FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
5417		FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0,
5418		/* IP12_7_6 [2] */
5419		FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
5420		/* IP12_5_4 [2] */
5421		FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0,
5422		/* IP12_3_2 [2] */
5423		FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
5424		/* IP12_1_0 [2] */
5425		FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, }
5426	},
5427	{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5428			     1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) {
5429		/* IP13_31 [1] */
5430		0, 0,
5431		/* IP13_30_29 [2] */
5432		FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
5433		/* IP13_28_26 [3] */
5434		FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
5435		FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0,
5436		/* IP13_25_23 [3] */
5437		FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
5438		FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0,
5439		/* IP13_22_19 [4] */
5440		FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
5441		FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
5442		0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0,
5443		/* IP13_18_16 [3] */
5444		FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
5445		FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
5446		/* IP13_15_13 [3] */
5447		FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
5448		FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
5449		/* IP13_12_10 [3] */
5450		FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5,
5451		FN_CAN_DEBUGOUT8, 0, 0,
5452		/* IP13_9_7 [3] */
5453		FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
5454		FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
5455		/* IP13_6_3 [4] */
5456		FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0,
5457		FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
5458		FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0,
5459		/* IP13_2_0 [3] */
5460		FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
5461		FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, }
5462	},
5463	{ PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
5464			     1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) {
5465		/* IP14_30 [1] */
5466		0, 0,
5467		/* IP14_30_28 [3] */
5468		FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
5469		FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
5470		FN_HRTS0_N_C, 0,
5471		/* IP14_27_25 [3] */
5472		FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD,
5473		FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0,
5474		/* IP14_24_22 [3] */
5475		FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
5476		FN_LCDOUT9, 0, 0, 0,
5477		/* IP14_21_19 [3] */
5478		FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
5479		FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
5480		/* IP14_18_16 [3] */
5481		FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
5482		FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
5483		/* IP14_15_12 [4] */
5484		FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC,
5485		FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
5486		0, 0, 0, 0, 0, 0, 0,
5487		/* IP14_11_9 [3] */
5488		FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1,
5489		0, 0, 0,
5490		/* IP14_8_6 [3] */
5491		FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0,
5492		0, 0, 0,
5493		/* IP14_5_3 [3] */
5494		FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2,
5495		FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C,
5496		/* IP14_2_0 [3] */
5497		FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
5498		FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
5499		FN_REMOCON, 0, }
5500	},
5501	{ PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
5502			     2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) {
5503		/* IP15_31_30 [2] */
5504		0, 0, 0, 0,
5505		/* IP15_29_28 [2] */
5506		FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
5507		/* IP15_27_26 [2] */
5508		FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13,
5509		/* IP15_25_23 [3] */
5510		FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA,
5511		FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0,
5512		/* IP15_22_20 [3] */
5513		FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
5514		FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
5515		/* IP15_19_18 [2] */
5516		FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21,
5517		/* IP15_17_16 [2] */
5518		FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20,
5519		/* IP15_15_14 [2] */
5520		FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0,
5521		/* IP15_13_12 [2] */
5522		FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0,
5523		/* IP15_11_9 [3] */
5524		FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C,
5525		0, 0, 0,
5526		/* IP15_8_6 [3] */
5527		FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
5528		FN_IIC2_SDA, FN_I2C2_SDA, 0,
5529		/* IP15_5_3 [3] */
5530		FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16,
5531		FN_IIC2_SCL, FN_I2C2_SCL, 0,
5532		/* IP15_2_0 [3] */
5533		FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
5534		FN_LCDOUT15, FN_SCIF_CLK_B, 0, }
5535	},
5536	{ PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
5537			     4, 4, 4, 4, 4, 4, 1, 1, 3, 3) {
5538		/* IP16_31_28 [4] */
5539		0, 0, 0, 0, 0, 0, 0, 0,
5540		0, 0, 0, 0, 0, 0, 0, 0,
5541		/* IP16_27_24 [4] */
5542		0, 0, 0, 0, 0, 0, 0, 0,
5543		0, 0, 0, 0, 0, 0, 0, 0,
5544		/* IP16_23_20 [4] */
5545		0, 0, 0, 0, 0, 0, 0, 0,
5546		0, 0, 0, 0, 0, 0, 0, 0,
5547		/* IP16_19_16 [4] */
5548		0, 0, 0, 0, 0, 0, 0, 0,
5549		0, 0, 0, 0, 0, 0, 0, 0,
5550		/* IP16_15_12 [4] */
5551		0, 0, 0, 0, 0, 0, 0, 0,
5552		0, 0, 0, 0, 0, 0, 0, 0,
5553		/* IP16_11_8 [4] */
5554		0, 0, 0, 0, 0, 0, 0, 0,
5555		0, 0, 0, 0, 0, 0, 0, 0,
5556		/* IP16_7 [1] */
5557		FN_USB1_OVC, FN_TCLK1_B,
5558		/* IP16_6 [1] */
5559		FN_USB1_PWEN, FN_AUDIO_CLKOUT_D,
5560		/* IP16_5_3 [3] */
5561		FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
5562		FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0,
5563		/* IP16_2_0 [3] */
5564		FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
5565		FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, }
5566	},
5567	{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5568			     3, 2, 2, 3, 2, 1, 1, 1, 2, 1,
5569			     2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) {
5570		/* SEL_SCIF1 [3] */
5571		FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
5572		FN_SEL_SCIF1_4, 0, 0, 0,
5573		/* SEL_SCIFB [2] */
5574		FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
5575		/* SEL_SCIFB2 [2] */
5576		FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
5577		/* SEL_SCIFB1 [3] */
5578		FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
5579		FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
5580		FN_SEL_SCIFB1_6, 0,
5581		/* SEL_SCIFA1 [2] */
5582		FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
5583		FN_SEL_SCIFA1_3,
5584		/* SEL_SCIF0 [1] */
5585		FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
5586		/* SEL_SCIFA [1] */
5587		FN_SEL_SCFA_0, FN_SEL_SCFA_1,
5588		/* SEL_SOF1 [1] */
5589		FN_SEL_SOF1_0, FN_SEL_SOF1_1,
5590		/* SEL_SSI7 [2] */
5591		FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
5592		/* SEL_SSI6 [1] */
5593		FN_SEL_SSI6_0, FN_SEL_SSI6_1,
5594		/* SEL_SSI5 [2] */
5595		FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
5596		/* SEL_VI3 [1] */
5597		FN_SEL_VI3_0, FN_SEL_VI3_1,
5598		/* SEL_VI2 [1] */
5599		FN_SEL_VI2_0, FN_SEL_VI2_1,
5600		/* SEL_VI1 [1] */
5601		FN_SEL_VI1_0, FN_SEL_VI1_1,
5602		/* SEL_VI0 [1] */
5603		FN_SEL_VI0_0, FN_SEL_VI0_1,
5604		/* SEL_TSIF1 [2] */
5605		FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
5606		/* RESERVED [1] */
5607		0, 0,
5608		/* SEL_LBS [1] */
5609		FN_SEL_LBS_0, FN_SEL_LBS_1,
5610		/* SEL_TSIF0 [2] */
5611		FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
5612		/* SEL_SOF3 [1] */
5613		FN_SEL_SOF3_0, FN_SEL_SOF3_1,
5614		/* SEL_SOF0 [1] */
5615		FN_SEL_SOF0_0, FN_SEL_SOF0_1, }
5616	},
5617	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
5618			     3, 1, 1, 1, 2, 1, 2, 1, 2,
5619			     1, 1, 1, 3, 3, 2, 3, 2, 2) {
5620		/* RESERVED [3] */
5621		0, 0, 0, 0, 0, 0, 0, 0,
5622		/* SEL_TMU1 [1] */
5623		FN_SEL_TMU1_0, FN_SEL_TMU1_1,
5624		/* SEL_HSCIF1 [1] */
5625		FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
5626		/* SEL_SCIFCLK [1] */
5627		FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
5628		/* SEL_CAN0 [2] */
5629		FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
5630		/* SEL_CANCLK [1] */
5631		FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
5632		/* SEL_SCIFA2 [2] */
5633		FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
5634		/* SEL_CAN1 [1] */
5635		FN_SEL_CAN1_0, FN_SEL_CAN1_1,
5636		/* RESERVED [2] */
5637		0, 0, 0, 0,
5638		/* SEL_SCIF2 [1] */
5639		FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
5640		/* SEL_ADI [1] */
5641		FN_SEL_ADI_0, FN_SEL_ADI_1,
5642		/* SEL_SSP [1] */
5643		FN_SEL_SSP_0, FN_SEL_SSP_1,
5644		/* SEL_FM [3] */
5645		FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
5646		FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
5647		/* SEL_HSCIF0 [3] */
5648		FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
5649		FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
5650		/* SEL_GPS [2] */
5651		FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
5652		/* RESERVED [3] */
5653		0, 0, 0, 0, 0, 0, 0, 0,
5654		/* SEL_SIM [2] */
5655		FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
5656		/* SEL_SSI8 [2] */
5657		FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, }
5658	},
5659	{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5660			     1, 1, 2, 4, 4, 2, 2,
5661			     4, 2, 3, 2, 3, 2) {
5662		/* SEL_IICDVFS [1] */
5663		FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
5664		/* SEL_IIC0 [1] */
5665		FN_SEL_IIC0_0, FN_SEL_IIC0_1,
5666		/* RESERVED [2] */
5667		0, 0, 0, 0,
5668		/* RESERVED [4] */
5669		0, 0, 0, 0, 0, 0, 0, 0,
5670		0, 0, 0, 0, 0, 0, 0, 0,
5671		/* RESERVED [4] */
5672		0, 0, 0, 0, 0, 0, 0, 0,
5673		0, 0, 0, 0, 0, 0, 0, 0,
5674		/* RESERVED [2] */
5675		0, 0, 0, 0,
5676		/* SEL_IEB [2] */
5677		FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
5678		/* RESERVED [4] */
5679		0, 0, 0, 0, 0, 0, 0, 0,
5680		0, 0, 0, 0, 0, 0, 0, 0,
5681		/* RESERVED [2] */
5682		0, 0, 0, 0,
5683		/* SEL_IIC2 [3] */
5684		FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
5685		FN_SEL_IIC2_4, 0, 0, 0,
5686		/* SEL_IIC1 [2] */
5687		FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
5688		/* SEL_I2C2 [3] */
5689		FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
5690		FN_SEL_I2C2_4, 0, 0, 0,
5691		/* SEL_I2C1 [2] */
5692		FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, }
5693	},
5694	{ },
5695};
5696
5697static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5698{
5699	if (pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31))
5700		return -EINVAL;
5701
5702	*pocctrl = 0xe606008c;
5703
5704	return 31 - (pin & 0x1f);
5705}
5706
5707static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = {
5708	.pin_to_pocctrl = r8a7790_pin_to_pocctrl,
5709};
5710
5711const struct sh_pfc_soc_info r8a7790_pinmux_info = {
5712	.name = "r8a77900_pfc",
5713	.ops = &r8a7790_pinmux_ops,
5714	.unlock_reg = 0xe6060000, /* PMMR */
5715
5716	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5717
5718	.pins = pinmux_pins,
5719	.nr_pins = ARRAY_SIZE(pinmux_pins),
5720	.groups = pinmux_groups,
5721	.nr_groups = ARRAY_SIZE(pinmux_groups),
5722	.functions = pinmux_functions,
5723	.nr_functions = ARRAY_SIZE(pinmux_functions),
5724
5725	.cfg_regs = pinmux_config_regs,
5726
5727	.pinmux_data = pinmux_data,
5728	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
5729};
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