tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*
2 * Copyright 2005-2009 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU Lesser General
5 * Public License. You may obtain a copy of the GNU Lesser General
6 * Public License Version 2.1 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/lgpl-license.html
9 * http://www.gnu.org/copyleft/lgpl.html
10 */
11
12#ifndef __DRM_IPU_H__
13#define __DRM_IPU_H__
14
15#include <linux/types.h>
16#include <linux/videodev2.h>
17#include <linux/bitmap.h>
18#include <linux/fb.h>
19#include <linux/of.h>
20#include <media/v4l2-mediabus.h>
21#include <video/videomode.h>
22
23struct ipu_soc;
24
25enum ipuv3_type {
26 IPUV3EX,
27 IPUV3M,
28 IPUV3H,
29};
30
31#define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3')
32
33/*
34 * Bitfield of Display Interface signal polarities.
35 */
36struct ipu_di_signal_cfg {
37 unsigned data_pol:1; /* true = inverted */
38 unsigned clk_pol:1; /* true = rising edge */
39 unsigned enable_pol:1;
40
41 struct videomode mode;
42
43 u32 bus_format;
44 u32 v_to_h_sync;
45
46#define IPU_DI_CLKMODE_SYNC (1 << 0)
47#define IPU_DI_CLKMODE_EXT (1 << 1)
48 unsigned long clkflags;
49
50 u8 hsync_pin;
51 u8 vsync_pin;
52};
53
54/*
55 * Enumeration of CSI destinations
56 */
57enum ipu_csi_dest {
58 IPU_CSI_DEST_IDMAC, /* to memory via SMFC */
59 IPU_CSI_DEST_IC, /* to Image Converter */
60 IPU_CSI_DEST_VDIC, /* to VDIC */
61};
62
63/*
64 * Enumeration of IPU rotation modes
65 */
66#define IPU_ROT_BIT_VFLIP (1 << 0)
67#define IPU_ROT_BIT_HFLIP (1 << 1)
68#define IPU_ROT_BIT_90 (1 << 2)
69
70enum ipu_rotate_mode {
71 IPU_ROTATE_NONE = 0,
72 IPU_ROTATE_VERT_FLIP = IPU_ROT_BIT_VFLIP,
73 IPU_ROTATE_HORIZ_FLIP = IPU_ROT_BIT_HFLIP,
74 IPU_ROTATE_180 = (IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP),
75 IPU_ROTATE_90_RIGHT = IPU_ROT_BIT_90,
76 IPU_ROTATE_90_RIGHT_VFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_VFLIP),
77 IPU_ROTATE_90_RIGHT_HFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_HFLIP),
78 IPU_ROTATE_90_LEFT = (IPU_ROT_BIT_90 |
79 IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP),
80};
81
82/* 90-degree rotations require the IRT unit */
83#define ipu_rot_mode_is_irt(m) (((m) & IPU_ROT_BIT_90) != 0)
84
85enum ipu_color_space {
86 IPUV3_COLORSPACE_RGB,
87 IPUV3_COLORSPACE_YUV,
88 IPUV3_COLORSPACE_UNKNOWN,
89};
90
91/*
92 * Enumeration of VDI MOTION select
93 */
94enum ipu_motion_sel {
95 MOTION_NONE = 0,
96 LOW_MOTION,
97 MED_MOTION,
98 HIGH_MOTION,
99};
100
101struct ipuv3_channel;
102
103enum ipu_channel_irq {
104 IPU_IRQ_EOF = 0,
105 IPU_IRQ_NFACK = 64,
106 IPU_IRQ_NFB4EOF = 128,
107 IPU_IRQ_EOS = 192,
108};
109
110/*
111 * Enumeration of IDMAC channels
112 */
113#define IPUV3_CHANNEL_CSI0 0
114#define IPUV3_CHANNEL_CSI1 1
115#define IPUV3_CHANNEL_CSI2 2
116#define IPUV3_CHANNEL_CSI3 3
117#define IPUV3_CHANNEL_VDI_MEM_IC_VF 5
118/*
119 * NOTE: channels 6,7 are unused in the IPU and are not IDMAC channels,
120 * but the direct CSI->VDI linking is handled the same way as IDMAC
121 * channel linking in the FSU via the IPU_FS_PROC_FLOW registers, so
122 * these channel names are used to support the direct CSI->VDI link.
123 */
124#define IPUV3_CHANNEL_CSI_DIRECT 6
125#define IPUV3_CHANNEL_CSI_VDI_PREV 7
126#define IPUV3_CHANNEL_MEM_VDI_PREV 8
127#define IPUV3_CHANNEL_MEM_VDI_CUR 9
128#define IPUV3_CHANNEL_MEM_VDI_NEXT 10
129#define IPUV3_CHANNEL_MEM_IC_PP 11
130#define IPUV3_CHANNEL_MEM_IC_PRP_VF 12
131#define IPUV3_CHANNEL_VDI_MEM_RECENT 13
132#define IPUV3_CHANNEL_G_MEM_IC_PRP_VF 14
133#define IPUV3_CHANNEL_G_MEM_IC_PP 15
134#define IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA 17
135#define IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA 18
136#define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA 19
137#define IPUV3_CHANNEL_IC_PRP_ENC_MEM 20
138#define IPUV3_CHANNEL_IC_PRP_VF_MEM 21
139#define IPUV3_CHANNEL_IC_PP_MEM 22
140#define IPUV3_CHANNEL_MEM_BG_SYNC 23
141#define IPUV3_CHANNEL_MEM_BG_ASYNC 24
142#define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB 25
143#define IPUV3_CHANNEL_MEM_VDI_PLANE3_COMB 26
144#define IPUV3_CHANNEL_MEM_FG_SYNC 27
145#define IPUV3_CHANNEL_MEM_DC_SYNC 28
146#define IPUV3_CHANNEL_MEM_FG_ASYNC 29
147#define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA 31
148#define IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA 33
149#define IPUV3_CHANNEL_DC_MEM_READ 40
150#define IPUV3_CHANNEL_MEM_DC_ASYNC 41
151#define IPUV3_CHANNEL_MEM_DC_COMMAND 42
152#define IPUV3_CHANNEL_MEM_DC_COMMAND2 43
153#define IPUV3_CHANNEL_MEM_DC_OUTPUT_MASK 44
154#define IPUV3_CHANNEL_MEM_ROT_ENC 45
155#define IPUV3_CHANNEL_MEM_ROT_VF 46
156#define IPUV3_CHANNEL_MEM_ROT_PP 47
157#define IPUV3_CHANNEL_ROT_ENC_MEM 48
158#define IPUV3_CHANNEL_ROT_VF_MEM 49
159#define IPUV3_CHANNEL_ROT_PP_MEM 50
160#define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA 51
161#define IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA 52
162#define IPUV3_NUM_CHANNELS 64
163
164int ipu_map_irq(struct ipu_soc *ipu, int irq);
165int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
166 enum ipu_channel_irq irq);
167
168#define IPU_IRQ_DP_SF_START (448 + 2)
169#define IPU_IRQ_DP_SF_END (448 + 3)
170#define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END,
171#define IPU_IRQ_DC_FC_0 (448 + 8)
172#define IPU_IRQ_DC_FC_1 (448 + 9)
173#define IPU_IRQ_DC_FC_2 (448 + 10)
174#define IPU_IRQ_DC_FC_3 (448 + 11)
175#define IPU_IRQ_DC_FC_4 (448 + 12)
176#define IPU_IRQ_DC_FC_6 (448 + 13)
177#define IPU_IRQ_VSYNC_PRE_0 (448 + 14)
178#define IPU_IRQ_VSYNC_PRE_1 (448 + 15)
179
180/*
181 * IPU Common functions
182 */
183int ipu_get_num(struct ipu_soc *ipu);
184void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2);
185void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi);
186void ipu_dump(struct ipu_soc *ipu);
187
188/*
189 * IPU Image DMA Controller (idmac) functions
190 */
191struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel);
192void ipu_idmac_put(struct ipuv3_channel *);
193
194int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
195int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
196void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable);
197int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts);
198int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);
199
200void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
201 bool doublebuffer);
202int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
203bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num);
204void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
205void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num);
206int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch);
207int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch);
208int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink);
209int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink);
210
211/*
212 * IPU Channel Parameter Memory (cpmem) functions
213 */
214struct ipu_rgb {
215 struct fb_bitfield red;
216 struct fb_bitfield green;
217 struct fb_bitfield blue;
218 struct fb_bitfield transp;
219 int bits_per_pixel;
220};
221
222struct ipu_image {
223 struct v4l2_pix_format pix;
224 struct v4l2_rect rect;
225 dma_addr_t phys0;
226 dma_addr_t phys1;
227};
228
229void ipu_cpmem_zero(struct ipuv3_channel *ch);
230void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
231void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
232void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
233void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
234void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off);
235void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride);
236void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id);
237int ipu_cpmem_get_burstsize(struct ipuv3_channel *ch);
238void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
239void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch);
240void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
241 enum ipu_rotate_mode rot);
242int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
243 const struct ipu_rgb *rgb);
244int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width);
245void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format);
246void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
247 unsigned int uv_stride,
248 unsigned int u_offset,
249 unsigned int v_offset);
250void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
251 u32 pixel_format, int stride, int height);
252int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc);
253int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image);
254void ipu_cpmem_dump(struct ipuv3_channel *ch);
255
256/*
257 * IPU Display Controller (dc) functions
258 */
259struct ipu_dc;
260struct ipu_di;
261struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
262void ipu_dc_put(struct ipu_dc *dc);
263int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
264 u32 pixel_fmt, u32 width);
265void ipu_dc_enable(struct ipu_soc *ipu);
266void ipu_dc_enable_channel(struct ipu_dc *dc);
267void ipu_dc_disable_channel(struct ipu_dc *dc);
268void ipu_dc_disable(struct ipu_soc *ipu);
269
270/*
271 * IPU Display Interface (di) functions
272 */
273struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp);
274void ipu_di_put(struct ipu_di *);
275int ipu_di_disable(struct ipu_di *);
276int ipu_di_enable(struct ipu_di *);
277int ipu_di_get_num(struct ipu_di *);
278int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode);
279int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig);
280
281/*
282 * IPU Display Multi FIFO Controller (dmfc) functions
283 */
284struct dmfc_channel;
285int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
286void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
287void ipu_dmfc_config_wait4eot(struct dmfc_channel *dmfc, int width);
288struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel);
289void ipu_dmfc_put(struct dmfc_channel *dmfc);
290
291/*
292 * IPU Display Processor (dp) functions
293 */
294#define IPU_DP_FLOW_SYNC_BG 0
295#define IPU_DP_FLOW_SYNC_FG 1
296#define IPU_DP_FLOW_ASYNC0_BG 2
297#define IPU_DP_FLOW_ASYNC0_FG 3
298#define IPU_DP_FLOW_ASYNC1_BG 4
299#define IPU_DP_FLOW_ASYNC1_FG 5
300
301struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
302void ipu_dp_put(struct ipu_dp *);
303int ipu_dp_enable(struct ipu_soc *ipu);
304int ipu_dp_enable_channel(struct ipu_dp *dp);
305void ipu_dp_disable_channel(struct ipu_dp *dp);
306void ipu_dp_disable(struct ipu_soc *ipu);
307int ipu_dp_setup_channel(struct ipu_dp *dp,
308 enum ipu_color_space in, enum ipu_color_space out);
309int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
310int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
311 bool bg_chan);
312
313/*
314 * IPU CMOS Sensor Interface (csi) functions
315 */
316struct ipu_csi;
317int ipu_csi_init_interface(struct ipu_csi *csi,
318 struct v4l2_mbus_config *mbus_cfg,
319 struct v4l2_mbus_framefmt *mbus_fmt);
320bool ipu_csi_is_interlaced(struct ipu_csi *csi);
321void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w);
322void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w);
323void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
324 u32 r_value, u32 g_value, u32 b_value,
325 u32 pix_clk);
326int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
327 struct v4l2_mbus_framefmt *mbus_fmt);
328int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
329 u32 max_ratio, u32 id);
330int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest);
331int ipu_csi_enable(struct ipu_csi *csi);
332int ipu_csi_disable(struct ipu_csi *csi);
333struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id);
334void ipu_csi_put(struct ipu_csi *csi);
335void ipu_csi_dump(struct ipu_csi *csi);
336
337/*
338 * IPU Image Converter (ic) functions
339 */
340enum ipu_ic_task {
341 IC_TASK_ENCODER,
342 IC_TASK_VIEWFINDER,
343 IC_TASK_POST_PROCESSOR,
344 IC_NUM_TASKS,
345};
346
347struct ipu_ic;
348int ipu_ic_task_init(struct ipu_ic *ic,
349 int in_width, int in_height,
350 int out_width, int out_height,
351 enum ipu_color_space in_cs,
352 enum ipu_color_space out_cs);
353int ipu_ic_task_graphics_init(struct ipu_ic *ic,
354 enum ipu_color_space in_g_cs,
355 bool galpha_en, u32 galpha,
356 bool colorkey_en, u32 colorkey);
357void ipu_ic_task_enable(struct ipu_ic *ic);
358void ipu_ic_task_disable(struct ipu_ic *ic);
359int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel,
360 u32 width, u32 height, int burst_size,
361 enum ipu_rotate_mode rot);
362int ipu_ic_enable(struct ipu_ic *ic);
363int ipu_ic_disable(struct ipu_ic *ic);
364struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task);
365void ipu_ic_put(struct ipu_ic *ic);
366void ipu_ic_dump(struct ipu_ic *ic);
367
368/*
369 * IPU Video De-Interlacer (vdi) functions
370 */
371struct ipu_vdi;
372void ipu_vdi_set_field_order(struct ipu_vdi *vdi, v4l2_std_id std, u32 field);
373void ipu_vdi_set_motion(struct ipu_vdi *vdi, enum ipu_motion_sel motion_sel);
374void ipu_vdi_setup(struct ipu_vdi *vdi, u32 code, int xres, int yres);
375void ipu_vdi_unsetup(struct ipu_vdi *vdi);
376int ipu_vdi_enable(struct ipu_vdi *vdi);
377int ipu_vdi_disable(struct ipu_vdi *vdi);
378struct ipu_vdi *ipu_vdi_get(struct ipu_soc *ipu);
379void ipu_vdi_put(struct ipu_vdi *vdi);
380
381/*
382 * IPU Sensor Multiple FIFO Controller (SMFC) functions
383 */
384struct ipu_smfc *ipu_smfc_get(struct ipu_soc *ipu, unsigned int chno);
385void ipu_smfc_put(struct ipu_smfc *smfc);
386int ipu_smfc_enable(struct ipu_smfc *smfc);
387int ipu_smfc_disable(struct ipu_smfc *smfc);
388int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id);
389int ipu_smfc_set_burstsize(struct ipu_smfc *smfc, int burstsize);
390int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level);
391
392enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
393enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
394enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code);
395int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat);
396bool ipu_pixelformat_is_planar(u32 pixelformat);
397int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
398 bool hflip, bool vflip);
399int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
400 bool hflip, bool vflip);
401
402struct ipu_client_platformdata {
403 int csi;
404 int di;
405 int dc;
406 int dp;
407 int dma[2];
408 struct device_node *of_node;
409};
410
411#endif /* __DRM_IPU_H__ */