Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
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linux
1/* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
3 *
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
6 * this source tree.
7 */
8
9#ifndef __ETH_COMMON__
10#define __ETH_COMMON__
11
12/********************/
13/* ETH FW CONSTANTS */
14/********************/
15#define ETH_HSI_VER_MAJOR 3
16#define ETH_HSI_VER_MINOR 0
17#define ETH_CACHE_LINE_SIZE 64
18
19#define ETH_MAX_RAMROD_PER_CON 8
20#define ETH_TX_BD_PAGE_SIZE_BYTES 4096
21#define ETH_RX_BD_PAGE_SIZE_BYTES 4096
22#define ETH_RX_CQE_PAGE_SIZE_BYTES 4096
23#define ETH_RX_NUM_NEXT_PAGE_BDS 2
24
25#define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1
26#define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18
27#define ETH_TX_MAX_LSO_HDR_NBD 4
28#define ETH_TX_MIN_BDS_PER_LSO_PKT 3
29#define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3
30#define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2
31#define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2
32#define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 12 + 8))
33#define ETH_TX_MAX_LSO_HDR_BYTES 510
34
35#define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
36
37/* Maximum number of buffers, used for RX packet placement */
38#define ETH_RX_MAX_BUFF_PER_PKT 5
39
40/* num of MAC/VLAN filters */
41#define ETH_NUM_MAC_FILTERS 512
42#define ETH_NUM_VLAN_FILTERS 512
43
44/* approx. multicast constants */
45#define ETH_MULTICAST_BIN_FROM_MAC_SEED 0
46#define ETH_MULTICAST_MAC_BINS 256
47#define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32)
48
49/* ethernet vport update constants */
50#define ETH_FILTER_RULES_COUNT 10
51#define ETH_RSS_IND_TABLE_ENTRIES_NUM 128
52#define ETH_RSS_KEY_SIZE_REGS 10
53#define ETH_RSS_ENGINE_NUM_K2 207
54#define ETH_RSS_ENGINE_NUM_BB 127
55
56/* TPA constants */
57#define ETH_TPA_MAX_AGGS_NUM 64
58#define ETH_TPA_CQE_START_LEN_LIST_SIZE ETH_RX_MAX_BUFF_PER_PKT
59#define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6
60#define ETH_TPA_CQE_END_LEN_LIST_SIZE 4
61
62
63struct eth_tx_1st_bd_flags {
64 u8 bitfields;
65#define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1
66#define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT 0
67#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1
68#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 1
69#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1
70#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT 2
71#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1
72#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT 3
73#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1
74#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT 4
75#define ETH_TX_1ST_BD_FLAGS_LSO_MASK 0x1
76#define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT 5
77#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK 0x1
78#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6
79#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1
80#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7
81};
82
83/* The parsing information data fo rthe first tx bd of a given packet. */
84struct eth_tx_data_1st_bd {
85 __le16 vlan;
86 u8 nbds;
87 struct eth_tx_1st_bd_flags bd_flags;
88 __le16 bitfields;
89#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK 0x1
90#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT 0
91#define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1
92#define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1
93#define ETH_TX_DATA_1ST_BD_PKT_LEN_MASK 0x3FFF
94#define ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT 2
95};
96
97/* The parsing information data for the second tx bd of a given packet. */
98struct eth_tx_data_2nd_bd {
99 __le16 tunn_ip_size;
100 __le16 bitfields1;
101#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF
102#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0
103#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK 0x3
104#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT 4
105#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_MASK 0x3
106#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_SHIFT 6
107#define ETH_TX_DATA_2ND_BD_START_BD_MASK 0x1
108#define ETH_TX_DATA_2ND_BD_START_BD_SHIFT 8
109#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK 0x3
110#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT 9
111#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK 0x1
112#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT 11
113#define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK 0x1
114#define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT 12
115#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK 0x1
116#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT 13
117#define ETH_TX_DATA_2ND_BD_L4_UDP_MASK 0x1
118#define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT 14
119#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK 0x1
120#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT 15
121 __le16 bitfields2;
122#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK 0x1FFF
123#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT 0
124#define ETH_TX_DATA_2ND_BD_RESERVED0_MASK 0x7
125#define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13
126};
127
128struct eth_fast_path_cqe_fw_debug {
129 u8 reserved0;
130 u8 reserved1;
131 __le16 reserved2;
132};
133
134/* tunneling parsing flags */
135struct eth_tunnel_parsing_flags {
136 u8 flags;
137#define ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK 0x3
138#define ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT 0
139#define ETH_TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_MASK 0x1
140#define ETH_TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_SHIFT 2
141#define ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK 0x3
142#define ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT 3
143#define ETH_TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_MASK 0x1
144#define ETH_TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_SHIFT 5
145#define ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_MASK 0x1
146#define ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_SHIFT 6
147#define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_MASK 0x1
148#define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_SHIFT 7
149};
150
151/* Regular ETH Rx FP CQE. */
152struct eth_fast_path_rx_reg_cqe {
153 u8 type;
154 u8 bitfields;
155#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK 0x7
156#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0
157#define ETH_FAST_PATH_RX_REG_CQE_TC_MASK 0xF
158#define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT 3
159#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK 0x1
160#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT 7
161 __le16 pkt_len;
162 struct parsing_and_err_flags pars_flags;
163 __le16 vlan_tag;
164 __le32 rss_hash;
165 __le16 len_on_first_bd;
166 u8 placement_offset;
167 struct eth_tunnel_parsing_flags tunnel_pars_flags;
168 u8 bd_num;
169 u8 reserved[7];
170 struct eth_fast_path_cqe_fw_debug fw_debug;
171 u8 reserved1[3];
172 u8 flags;
173#define ETH_FAST_PATH_RX_REG_CQE_VALID_MASK 0x1
174#define ETH_FAST_PATH_RX_REG_CQE_VALID_SHIFT 0
175#define ETH_FAST_PATH_RX_REG_CQE_VALID_TOGGLE_MASK 0x1
176#define ETH_FAST_PATH_RX_REG_CQE_VALID_TOGGLE_SHIFT 1
177#define ETH_FAST_PATH_RX_REG_CQE_RESERVED2_MASK 0x3F
178#define ETH_FAST_PATH_RX_REG_CQE_RESERVED2_SHIFT 2
179};
180
181/* TPA-continue ETH Rx FP CQE. */
182struct eth_fast_path_rx_tpa_cont_cqe {
183 u8 type;
184 u8 tpa_agg_index;
185 __le16 len_list[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
186 u8 reserved[5];
187 u8 reserved1;
188 __le16 reserved2[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
189};
190
191/* TPA-end ETH Rx FP CQE. */
192struct eth_fast_path_rx_tpa_end_cqe {
193 u8 type;
194 u8 tpa_agg_index;
195 __le16 total_packet_len;
196 u8 num_of_bds;
197 u8 end_reason;
198 __le16 num_of_coalesced_segs;
199 __le32 ts_delta;
200 __le16 len_list[ETH_TPA_CQE_END_LEN_LIST_SIZE];
201 u8 reserved1[3];
202 u8 reserved2;
203 __le16 reserved3[ETH_TPA_CQE_END_LEN_LIST_SIZE];
204};
205
206/* TPA-start ETH Rx FP CQE. */
207struct eth_fast_path_rx_tpa_start_cqe {
208 u8 type;
209 u8 bitfields;
210#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK 0x7
211#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0
212#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK 0xF
213#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT 3
214#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK 0x1
215#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT 7
216 __le16 seg_len;
217 struct parsing_and_err_flags pars_flags;
218 __le16 vlan_tag;
219 __le32 rss_hash;
220 __le16 len_on_first_bd;
221 u8 placement_offset;
222 struct eth_tunnel_parsing_flags tunnel_pars_flags;
223 u8 tpa_agg_index;
224 u8 header_len;
225 __le16 ext_bd_len_list[ETH_TPA_CQE_START_LEN_LIST_SIZE];
226 struct eth_fast_path_cqe_fw_debug fw_debug;
227};
228
229/* The L4 pseudo checksum mode for Ethernet */
230enum eth_l4_pseudo_checksum_mode {
231 ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH,
232 ETH_L4_PSEUDO_CSUM_ZERO_LENGTH,
233 MAX_ETH_L4_PSEUDO_CHECKSUM_MODE
234};
235
236struct eth_rx_bd {
237 struct regpair addr;
238};
239
240/* regular ETH Rx SP CQE */
241struct eth_slow_path_rx_cqe {
242 u8 type;
243 u8 ramrod_cmd_id;
244 u8 error_flag;
245 u8 reserved[25];
246 __le16 echo;
247 u8 reserved1;
248 u8 flags;
249/* for PMD mode - valid indication */
250#define ETH_SLOW_PATH_RX_CQE_VALID_MASK 0x1
251#define ETH_SLOW_PATH_RX_CQE_VALID_SHIFT 0
252/* for PMD mode - valid toggle indication */
253#define ETH_SLOW_PATH_RX_CQE_VALID_TOGGLE_MASK 0x1
254#define ETH_SLOW_PATH_RX_CQE_VALID_TOGGLE_SHIFT 1
255#define ETH_SLOW_PATH_RX_CQE_RESERVED2_MASK 0x3F
256#define ETH_SLOW_PATH_RX_CQE_RESERVED2_SHIFT 2
257};
258
259/* union for all ETH Rx CQE types */
260union eth_rx_cqe {
261 struct eth_fast_path_rx_reg_cqe fast_path_regular;
262 struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start;
263 struct eth_fast_path_rx_tpa_cont_cqe fast_path_tpa_cont;
264 struct eth_fast_path_rx_tpa_end_cqe fast_path_tpa_end;
265 struct eth_slow_path_rx_cqe slow_path;
266};
267
268/* ETH Rx CQE type */
269enum eth_rx_cqe_type {
270 ETH_RX_CQE_TYPE_UNUSED,
271 ETH_RX_CQE_TYPE_REGULAR,
272 ETH_RX_CQE_TYPE_SLOW_PATH,
273 ETH_RX_CQE_TYPE_TPA_START,
274 ETH_RX_CQE_TYPE_TPA_CONT,
275 ETH_RX_CQE_TYPE_TPA_END,
276 MAX_ETH_RX_CQE_TYPE
277};
278
279enum eth_rx_tunn_type {
280 ETH_RX_NO_TUNN,
281 ETH_RX_TUNN_GENEVE,
282 ETH_RX_TUNN_GRE,
283 ETH_RX_TUNN_VXLAN,
284 MAX_ETH_RX_TUNN_TYPE
285};
286
287/* Aggregation end reason. */
288enum eth_tpa_end_reason {
289 ETH_AGG_END_UNUSED,
290 ETH_AGG_END_SP_UPDATE,
291 ETH_AGG_END_MAX_LEN,
292 ETH_AGG_END_LAST_SEG,
293 ETH_AGG_END_TIMEOUT,
294 ETH_AGG_END_NOT_CONSISTENT,
295 ETH_AGG_END_OUT_OF_ORDER,
296 ETH_AGG_END_NON_TPA_SEG,
297 MAX_ETH_TPA_END_REASON
298};
299
300/* The first tx bd of a given packet */
301struct eth_tx_1st_bd {
302 struct regpair addr;
303 __le16 nbytes;
304 struct eth_tx_data_1st_bd data;
305};
306
307/* The second tx bd of a given packet */
308struct eth_tx_2nd_bd {
309 struct regpair addr;
310 __le16 nbytes;
311 struct eth_tx_data_2nd_bd data;
312};
313
314/* The parsing information data for the third tx bd of a given packet. */
315struct eth_tx_data_3rd_bd {
316 __le16 lso_mss;
317 __le16 bitfields;
318#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF
319#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0
320#define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF
321#define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT 4
322#define ETH_TX_DATA_3RD_BD_START_BD_MASK 0x1
323#define ETH_TX_DATA_3RD_BD_START_BD_SHIFT 8
324#define ETH_TX_DATA_3RD_BD_RESERVED0_MASK 0x7F
325#define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT 9
326 u8 tunn_l4_hdr_start_offset_w;
327 u8 tunn_hdr_size_w;
328};
329
330/* The third tx bd of a given packet */
331struct eth_tx_3rd_bd {
332 struct regpair addr;
333 __le16 nbytes;
334 struct eth_tx_data_3rd_bd data;
335};
336
337/* Complementary information for the regular tx bd of a given packet. */
338struct eth_tx_data_bd {
339 __le16 reserved0;
340 __le16 bitfields;
341#define ETH_TX_DATA_BD_RESERVED1_MASK 0xFF
342#define ETH_TX_DATA_BD_RESERVED1_SHIFT 0
343#define ETH_TX_DATA_BD_START_BD_MASK 0x1
344#define ETH_TX_DATA_BD_START_BD_SHIFT 8
345#define ETH_TX_DATA_BD_RESERVED2_MASK 0x7F
346#define ETH_TX_DATA_BD_RESERVED2_SHIFT 9
347 __le16 reserved3;
348};
349
350/* The common non-special TX BD ring element */
351struct eth_tx_bd {
352 struct regpair addr;
353 __le16 nbytes;
354 struct eth_tx_data_bd data;
355};
356
357union eth_tx_bd_types {
358 struct eth_tx_1st_bd first_bd;
359 struct eth_tx_2nd_bd second_bd;
360 struct eth_tx_3rd_bd third_bd;
361 struct eth_tx_bd reg_bd;
362};
363
364/* Mstorm Queue Zone */
365enum eth_tx_tunn_type {
366 ETH_TX_TUNN_GENEVE,
367 ETH_TX_TUNN_TTAG,
368 ETH_TX_TUNN_GRE,
369 ETH_TX_TUNN_VXLAN,
370 MAX_ETH_TX_TUNN_TYPE
371};
372
373/* Ystorm Queue Zone */
374struct xstorm_eth_queue_zone {
375 struct coalescing_timeset int_coalescing_timeset;
376 u8 reserved[7];
377};
378
379/* ETH doorbell data */
380struct eth_db_data {
381 u8 params;
382#define ETH_DB_DATA_DEST_MASK 0x3
383#define ETH_DB_DATA_DEST_SHIFT 0
384#define ETH_DB_DATA_AGG_CMD_MASK 0x3
385#define ETH_DB_DATA_AGG_CMD_SHIFT 2
386#define ETH_DB_DATA_BYPASS_EN_MASK 0x1
387#define ETH_DB_DATA_BYPASS_EN_SHIFT 4
388#define ETH_DB_DATA_RESERVED_MASK 0x1
389#define ETH_DB_DATA_RESERVED_SHIFT 5
390#define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3
391#define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6
392 u8 agg_flags;
393 __le16 bd_prod;
394};
395
396#endif /* __ETH_COMMON__ */