tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Synopsys Designware PCIe host controller driver
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Author: Jingoo Han <jg1.han@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/irq.h>
15#include <linux/irqdomain.h>
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/msi.h>
19#include <linux/of_address.h>
20#include <linux/of_pci.h>
21#include <linux/pci.h>
22#include <linux/pci_regs.h>
23#include <linux/platform_device.h>
24#include <linux/types.h>
25#include <linux/delay.h>
26
27#include "pcie-designware.h"
28
29/* Synopsis specific PCIE configuration registers */
30#define PCIE_PORT_LINK_CONTROL 0x710
31#define PORT_LINK_MODE_MASK (0x3f << 16)
32#define PORT_LINK_MODE_1_LANES (0x1 << 16)
33#define PORT_LINK_MODE_2_LANES (0x3 << 16)
34#define PORT_LINK_MODE_4_LANES (0x7 << 16)
35#define PORT_LINK_MODE_8_LANES (0xf << 16)
36
37#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
38#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
39#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
40#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
41#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
42#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
43#define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8)
44
45#define PCIE_MSI_ADDR_LO 0x820
46#define PCIE_MSI_ADDR_HI 0x824
47#define PCIE_MSI_INTR0_ENABLE 0x828
48#define PCIE_MSI_INTR0_MASK 0x82C
49#define PCIE_MSI_INTR0_STATUS 0x830
50
51#define PCIE_ATU_VIEWPORT 0x900
52#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
53#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
54#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
55#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
56#define PCIE_ATU_CR1 0x904
57#define PCIE_ATU_TYPE_MEM (0x0 << 0)
58#define PCIE_ATU_TYPE_IO (0x2 << 0)
59#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
60#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
61#define PCIE_ATU_CR2 0x908
62#define PCIE_ATU_ENABLE (0x1 << 31)
63#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
64#define PCIE_ATU_LOWER_BASE 0x90C
65#define PCIE_ATU_UPPER_BASE 0x910
66#define PCIE_ATU_LIMIT 0x914
67#define PCIE_ATU_LOWER_TARGET 0x918
68#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
69#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
70#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
71#define PCIE_ATU_UPPER_TARGET 0x91C
72
73/* PCIe Port Logic registers */
74#define PLR_OFFSET 0x700
75#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
76#define PCIE_PHY_DEBUG_R1_LINK_UP 0x00000010
77
78static struct pci_ops dw_pcie_ops;
79
80int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
81{
82 if ((uintptr_t)addr & (size - 1)) {
83 *val = 0;
84 return PCIBIOS_BAD_REGISTER_NUMBER;
85 }
86
87 if (size == 4)
88 *val = readl(addr);
89 else if (size == 2)
90 *val = readw(addr);
91 else if (size == 1)
92 *val = readb(addr);
93 else {
94 *val = 0;
95 return PCIBIOS_BAD_REGISTER_NUMBER;
96 }
97
98 return PCIBIOS_SUCCESSFUL;
99}
100
101int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val)
102{
103 if ((uintptr_t)addr & (size - 1))
104 return PCIBIOS_BAD_REGISTER_NUMBER;
105
106 if (size == 4)
107 writel(val, addr);
108 else if (size == 2)
109 writew(val, addr);
110 else if (size == 1)
111 writeb(val, addr);
112 else
113 return PCIBIOS_BAD_REGISTER_NUMBER;
114
115 return PCIBIOS_SUCCESSFUL;
116}
117
118static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
119{
120 if (pp->ops->readl_rc)
121 pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
122 else
123 *val = readl(pp->dbi_base + reg);
124}
125
126static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
127{
128 if (pp->ops->writel_rc)
129 pp->ops->writel_rc(pp, val, pp->dbi_base + reg);
130 else
131 writel(val, pp->dbi_base + reg);
132}
133
134static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
135 u32 *val)
136{
137 if (pp->ops->rd_own_conf)
138 return pp->ops->rd_own_conf(pp, where, size, val);
139
140 return dw_pcie_cfg_read(pp->dbi_base + where, size, val);
141}
142
143static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
144 u32 val)
145{
146 if (pp->ops->wr_own_conf)
147 return pp->ops->wr_own_conf(pp, where, size, val);
148
149 return dw_pcie_cfg_write(pp->dbi_base + where, size, val);
150}
151
152static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
153 int type, u64 cpu_addr, u64 pci_addr, u32 size)
154{
155 u32 val;
156
157 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index,
158 PCIE_ATU_VIEWPORT);
159 dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), PCIE_ATU_LOWER_BASE);
160 dw_pcie_writel_rc(pp, upper_32_bits(cpu_addr), PCIE_ATU_UPPER_BASE);
161 dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr + size - 1),
162 PCIE_ATU_LIMIT);
163 dw_pcie_writel_rc(pp, lower_32_bits(pci_addr), PCIE_ATU_LOWER_TARGET);
164 dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET);
165 dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1);
166 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
167
168 /*
169 * Make sure ATU enable takes effect before any subsequent config
170 * and I/O accesses.
171 */
172 dw_pcie_readl_rc(pp, PCIE_ATU_CR2, &val);
173}
174
175static struct irq_chip dw_msi_irq_chip = {
176 .name = "PCI-MSI",
177 .irq_enable = pci_msi_unmask_irq,
178 .irq_disable = pci_msi_mask_irq,
179 .irq_mask = pci_msi_mask_irq,
180 .irq_unmask = pci_msi_unmask_irq,
181};
182
183/* MSI int handler */
184irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
185{
186 unsigned long val;
187 int i, pos, irq;
188 irqreturn_t ret = IRQ_NONE;
189
190 for (i = 0; i < MAX_MSI_CTRLS; i++) {
191 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
192 (u32 *)&val);
193 if (val) {
194 ret = IRQ_HANDLED;
195 pos = 0;
196 while ((pos = find_next_bit(&val, 32, pos)) != 32) {
197 irq = irq_find_mapping(pp->irq_domain,
198 i * 32 + pos);
199 dw_pcie_wr_own_conf(pp,
200 PCIE_MSI_INTR0_STATUS + i * 12,
201 4, 1 << pos);
202 generic_handle_irq(irq);
203 pos++;
204 }
205 }
206 }
207
208 return ret;
209}
210
211void dw_pcie_msi_init(struct pcie_port *pp)
212{
213 u64 msi_target;
214
215 pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
216 msi_target = virt_to_phys((void *)pp->msi_data);
217
218 /* program the msi_data */
219 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
220 (u32)(msi_target & 0xffffffff));
221 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4,
222 (u32)(msi_target >> 32 & 0xffffffff));
223}
224
225static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
226{
227 unsigned int res, bit, val;
228
229 res = (irq / 32) * 12;
230 bit = irq % 32;
231 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
232 val &= ~(1 << bit);
233 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
234}
235
236static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
237 unsigned int nvec, unsigned int pos)
238{
239 unsigned int i;
240
241 for (i = 0; i < nvec; i++) {
242 irq_set_msi_desc_off(irq_base, i, NULL);
243 /* Disable corresponding interrupt on MSI controller */
244 if (pp->ops->msi_clear_irq)
245 pp->ops->msi_clear_irq(pp, pos + i);
246 else
247 dw_pcie_msi_clear_irq(pp, pos + i);
248 }
249
250 bitmap_release_region(pp->msi_irq_in_use, pos, order_base_2(nvec));
251}
252
253static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
254{
255 unsigned int res, bit, val;
256
257 res = (irq / 32) * 12;
258 bit = irq % 32;
259 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
260 val |= 1 << bit;
261 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
262}
263
264static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
265{
266 int irq, pos0, i;
267 struct pcie_port *pp = (struct pcie_port *) msi_desc_to_pci_sysdata(desc);
268
269 pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS,
270 order_base_2(no_irqs));
271 if (pos0 < 0)
272 goto no_valid_irq;
273
274 irq = irq_find_mapping(pp->irq_domain, pos0);
275 if (!irq)
276 goto no_valid_irq;
277
278 /*
279 * irq_create_mapping (called from dw_pcie_host_init) pre-allocates
280 * descs so there is no need to allocate descs here. We can therefore
281 * assume that if irq_find_mapping above returns non-zero, then the
282 * descs are also successfully allocated.
283 */
284
285 for (i = 0; i < no_irqs; i++) {
286 if (irq_set_msi_desc_off(irq, i, desc) != 0) {
287 clear_irq_range(pp, irq, i, pos0);
288 goto no_valid_irq;
289 }
290 /*Enable corresponding interrupt in MSI interrupt controller */
291 if (pp->ops->msi_set_irq)
292 pp->ops->msi_set_irq(pp, pos0 + i);
293 else
294 dw_pcie_msi_set_irq(pp, pos0 + i);
295 }
296
297 *pos = pos0;
298 desc->nvec_used = no_irqs;
299 desc->msi_attrib.multiple = order_base_2(no_irqs);
300
301 return irq;
302
303no_valid_irq:
304 *pos = pos0;
305 return -ENOSPC;
306}
307
308static void dw_msi_setup_msg(struct pcie_port *pp, unsigned int irq, u32 pos)
309{
310 struct msi_msg msg;
311 u64 msi_target;
312
313 if (pp->ops->get_msi_addr)
314 msi_target = pp->ops->get_msi_addr(pp);
315 else
316 msi_target = virt_to_phys((void *)pp->msi_data);
317
318 msg.address_lo = (u32)(msi_target & 0xffffffff);
319 msg.address_hi = (u32)(msi_target >> 32 & 0xffffffff);
320
321 if (pp->ops->get_msi_data)
322 msg.data = pp->ops->get_msi_data(pp, pos);
323 else
324 msg.data = pos;
325
326 pci_write_msi_msg(irq, &msg);
327}
328
329static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
330 struct msi_desc *desc)
331{
332 int irq, pos;
333 struct pcie_port *pp = pdev->bus->sysdata;
334
335 if (desc->msi_attrib.is_msix)
336 return -EINVAL;
337
338 irq = assign_irq(1, desc, &pos);
339 if (irq < 0)
340 return irq;
341
342 dw_msi_setup_msg(pp, irq, pos);
343
344 return 0;
345}
346
347static int dw_msi_setup_irqs(struct msi_controller *chip, struct pci_dev *pdev,
348 int nvec, int type)
349{
350#ifdef CONFIG_PCI_MSI
351 int irq, pos;
352 struct msi_desc *desc;
353 struct pcie_port *pp = pdev->bus->sysdata;
354
355 /* MSI-X interrupts are not supported */
356 if (type == PCI_CAP_ID_MSIX)
357 return -EINVAL;
358
359 WARN_ON(!list_is_singular(&pdev->dev.msi_list));
360 desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list);
361
362 irq = assign_irq(nvec, desc, &pos);
363 if (irq < 0)
364 return irq;
365
366 dw_msi_setup_msg(pp, irq, pos);
367
368 return 0;
369#else
370 return -EINVAL;
371#endif
372}
373
374static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
375{
376 struct irq_data *data = irq_get_irq_data(irq);
377 struct msi_desc *msi = irq_data_get_msi_desc(data);
378 struct pcie_port *pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
379
380 clear_irq_range(pp, irq, 1, data->hwirq);
381}
382
383static struct msi_controller dw_pcie_msi_chip = {
384 .setup_irq = dw_msi_setup_irq,
385 .setup_irqs = dw_msi_setup_irqs,
386 .teardown_irq = dw_msi_teardown_irq,
387};
388
389int dw_pcie_wait_for_link(struct pcie_port *pp)
390{
391 int retries;
392
393 /* check if the link is up or not */
394 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
395 if (dw_pcie_link_up(pp)) {
396 dev_info(pp->dev, "link up\n");
397 return 0;
398 }
399 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
400 }
401
402 dev_err(pp->dev, "phy link never came up\n");
403
404 return -ETIMEDOUT;
405}
406
407int dw_pcie_link_up(struct pcie_port *pp)
408{
409 u32 val;
410
411 if (pp->ops->link_up)
412 return pp->ops->link_up(pp);
413
414 val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
415 return val & PCIE_PHY_DEBUG_R1_LINK_UP;
416}
417
418static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
419 irq_hw_number_t hwirq)
420{
421 irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
422 irq_set_chip_data(irq, domain->host_data);
423
424 return 0;
425}
426
427static const struct irq_domain_ops msi_domain_ops = {
428 .map = dw_pcie_msi_map,
429};
430
431int dw_pcie_host_init(struct pcie_port *pp)
432{
433 struct device_node *np = pp->dev->of_node;
434 struct platform_device *pdev = to_platform_device(pp->dev);
435 struct pci_bus *bus, *child;
436 struct resource *cfg_res;
437 int i, ret;
438 LIST_HEAD(res);
439 struct resource_entry *win;
440
441 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
442 if (cfg_res) {
443 pp->cfg0_size = resource_size(cfg_res)/2;
444 pp->cfg1_size = resource_size(cfg_res)/2;
445 pp->cfg0_base = cfg_res->start;
446 pp->cfg1_base = cfg_res->start + pp->cfg0_size;
447 } else if (!pp->va_cfg0_base) {
448 dev_err(pp->dev, "missing *config* reg space\n");
449 }
450
451 ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp->io_base);
452 if (ret)
453 return ret;
454
455 ret = devm_request_pci_bus_resources(&pdev->dev, &res);
456 if (ret)
457 goto error;
458
459 /* Get the I/O and memory ranges from DT */
460 resource_list_for_each_entry(win, &res) {
461 switch (resource_type(win->res)) {
462 case IORESOURCE_IO:
463 pp->io = win->res;
464 pp->io->name = "I/O";
465 pp->io_size = resource_size(pp->io);
466 pp->io_bus_addr = pp->io->start - win->offset;
467 ret = pci_remap_iospace(pp->io, pp->io_base);
468 if (ret)
469 dev_warn(pp->dev, "error %d: failed to map resource %pR\n",
470 ret, pp->io);
471 break;
472 case IORESOURCE_MEM:
473 pp->mem = win->res;
474 pp->mem->name = "MEM";
475 pp->mem_size = resource_size(pp->mem);
476 pp->mem_bus_addr = pp->mem->start - win->offset;
477 break;
478 case 0:
479 pp->cfg = win->res;
480 pp->cfg0_size = resource_size(pp->cfg)/2;
481 pp->cfg1_size = resource_size(pp->cfg)/2;
482 pp->cfg0_base = pp->cfg->start;
483 pp->cfg1_base = pp->cfg->start + pp->cfg0_size;
484 break;
485 case IORESOURCE_BUS:
486 pp->busn = win->res;
487 break;
488 }
489 }
490
491 if (!pp->dbi_base) {
492 pp->dbi_base = devm_ioremap(pp->dev, pp->cfg->start,
493 resource_size(pp->cfg));
494 if (!pp->dbi_base) {
495 dev_err(pp->dev, "error with ioremap\n");
496 ret = -ENOMEM;
497 goto error;
498 }
499 }
500
501 pp->mem_base = pp->mem->start;
502
503 if (!pp->va_cfg0_base) {
504 pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
505 pp->cfg0_size);
506 if (!pp->va_cfg0_base) {
507 dev_err(pp->dev, "error with ioremap in function\n");
508 ret = -ENOMEM;
509 goto error;
510 }
511 }
512
513 if (!pp->va_cfg1_base) {
514 pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
515 pp->cfg1_size);
516 if (!pp->va_cfg1_base) {
517 dev_err(pp->dev, "error with ioremap\n");
518 ret = -ENOMEM;
519 goto error;
520 }
521 }
522
523 ret = of_property_read_u32(np, "num-lanes", &pp->lanes);
524 if (ret)
525 pp->lanes = 0;
526
527 if (IS_ENABLED(CONFIG_PCI_MSI)) {
528 if (!pp->ops->msi_host_init) {
529 pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
530 MAX_MSI_IRQS, &msi_domain_ops,
531 &dw_pcie_msi_chip);
532 if (!pp->irq_domain) {
533 dev_err(pp->dev, "irq domain init failed\n");
534 ret = -ENXIO;
535 goto error;
536 }
537
538 for (i = 0; i < MAX_MSI_IRQS; i++)
539 irq_create_mapping(pp->irq_domain, i);
540 } else {
541 ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip);
542 if (ret < 0)
543 goto error;
544 }
545 }
546
547 if (pp->ops->host_init)
548 pp->ops->host_init(pp);
549
550 pp->root_bus_nr = pp->busn->start;
551 if (IS_ENABLED(CONFIG_PCI_MSI)) {
552 bus = pci_scan_root_bus_msi(pp->dev, pp->root_bus_nr,
553 &dw_pcie_ops, pp, &res,
554 &dw_pcie_msi_chip);
555 dw_pcie_msi_chip.dev = pp->dev;
556 } else
557 bus = pci_scan_root_bus(pp->dev, pp->root_bus_nr, &dw_pcie_ops,
558 pp, &res);
559 if (!bus) {
560 ret = -ENOMEM;
561 goto error;
562 }
563
564 if (pp->ops->scan_bus)
565 pp->ops->scan_bus(pp);
566
567#ifdef CONFIG_ARM
568 /* support old dtbs that incorrectly describe IRQs */
569 pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
570#endif
571
572 pci_bus_size_bridges(bus);
573 pci_bus_assign_resources(bus);
574
575 list_for_each_entry(child, &bus->children, node)
576 pcie_bus_configure_settings(child);
577
578 pci_bus_add_devices(bus);
579 return 0;
580
581error:
582 pci_free_resource_list(&res);
583 return ret;
584}
585
586static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
587 u32 devfn, int where, int size, u32 *val)
588{
589 int ret, type;
590 u32 busdev, cfg_size;
591 u64 cpu_addr;
592 void __iomem *va_cfg_base;
593
594 if (pp->ops->rd_other_conf)
595 return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
596
597 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
598 PCIE_ATU_FUNC(PCI_FUNC(devfn));
599
600 if (bus->parent->number == pp->root_bus_nr) {
601 type = PCIE_ATU_TYPE_CFG0;
602 cpu_addr = pp->cfg0_base;
603 cfg_size = pp->cfg0_size;
604 va_cfg_base = pp->va_cfg0_base;
605 } else {
606 type = PCIE_ATU_TYPE_CFG1;
607 cpu_addr = pp->cfg1_base;
608 cfg_size = pp->cfg1_size;
609 va_cfg_base = pp->va_cfg1_base;
610 }
611
612 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
613 type, cpu_addr,
614 busdev, cfg_size);
615 ret = dw_pcie_cfg_read(va_cfg_base + where, size, val);
616 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
617 PCIE_ATU_TYPE_IO, pp->io_base,
618 pp->io_bus_addr, pp->io_size);
619
620 return ret;
621}
622
623static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
624 u32 devfn, int where, int size, u32 val)
625{
626 int ret, type;
627 u32 busdev, cfg_size;
628 u64 cpu_addr;
629 void __iomem *va_cfg_base;
630
631 if (pp->ops->wr_other_conf)
632 return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val);
633
634 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
635 PCIE_ATU_FUNC(PCI_FUNC(devfn));
636
637 if (bus->parent->number == pp->root_bus_nr) {
638 type = PCIE_ATU_TYPE_CFG0;
639 cpu_addr = pp->cfg0_base;
640 cfg_size = pp->cfg0_size;
641 va_cfg_base = pp->va_cfg0_base;
642 } else {
643 type = PCIE_ATU_TYPE_CFG1;
644 cpu_addr = pp->cfg1_base;
645 cfg_size = pp->cfg1_size;
646 va_cfg_base = pp->va_cfg1_base;
647 }
648
649 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
650 type, cpu_addr,
651 busdev, cfg_size);
652 ret = dw_pcie_cfg_write(va_cfg_base + where, size, val);
653 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
654 PCIE_ATU_TYPE_IO, pp->io_base,
655 pp->io_bus_addr, pp->io_size);
656
657 return ret;
658}
659
660static int dw_pcie_valid_config(struct pcie_port *pp,
661 struct pci_bus *bus, int dev)
662{
663 /* If there is no link, then there is no device */
664 if (bus->number != pp->root_bus_nr) {
665 if (!dw_pcie_link_up(pp))
666 return 0;
667 }
668
669 /* access only one slot on each root port */
670 if (bus->number == pp->root_bus_nr && dev > 0)
671 return 0;
672
673 /*
674 * do not read more than one device on the bus directly attached
675 * to RC's (Virtual Bridge's) DS side.
676 */
677 if (bus->primary == pp->root_bus_nr && dev > 0)
678 return 0;
679
680 return 1;
681}
682
683static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
684 int size, u32 *val)
685{
686 struct pcie_port *pp = bus->sysdata;
687
688 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
689 *val = 0xffffffff;
690 return PCIBIOS_DEVICE_NOT_FOUND;
691 }
692
693 if (bus->number == pp->root_bus_nr)
694 return dw_pcie_rd_own_conf(pp, where, size, val);
695
696 return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
697}
698
699static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
700 int where, int size, u32 val)
701{
702 struct pcie_port *pp = bus->sysdata;
703
704 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
705 return PCIBIOS_DEVICE_NOT_FOUND;
706
707 if (bus->number == pp->root_bus_nr)
708 return dw_pcie_wr_own_conf(pp, where, size, val);
709
710 return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
711}
712
713static struct pci_ops dw_pcie_ops = {
714 .read = dw_pcie_rd_conf,
715 .write = dw_pcie_wr_conf,
716};
717
718void dw_pcie_setup_rc(struct pcie_port *pp)
719{
720 u32 val;
721
722 /* set the number of lanes */
723 dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
724 val &= ~PORT_LINK_MODE_MASK;
725 switch (pp->lanes) {
726 case 1:
727 val |= PORT_LINK_MODE_1_LANES;
728 break;
729 case 2:
730 val |= PORT_LINK_MODE_2_LANES;
731 break;
732 case 4:
733 val |= PORT_LINK_MODE_4_LANES;
734 break;
735 case 8:
736 val |= PORT_LINK_MODE_8_LANES;
737 break;
738 default:
739 dev_err(pp->dev, "num-lanes %u: invalid value\n", pp->lanes);
740 return;
741 }
742 dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
743
744 /* set link width speed control register */
745 dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
746 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
747 switch (pp->lanes) {
748 case 1:
749 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
750 break;
751 case 2:
752 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
753 break;
754 case 4:
755 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
756 break;
757 case 8:
758 val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
759 break;
760 }
761 dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
762
763 /* setup RC BARs */
764 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
765 dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
766
767 /* setup interrupt pins */
768 dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
769 val &= 0xffff00ff;
770 val |= 0x00000100;
771 dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
772
773 /* setup bus numbers */
774 dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
775 val &= 0xff000000;
776 val |= 0x00010100;
777 dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
778
779 /* setup command register */
780 dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
781 val &= 0xffff0000;
782 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
783 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
784 dw_pcie_writel_rc(pp, val, PCI_COMMAND);
785
786 /*
787 * If the platform provides ->rd_other_conf, it means the platform
788 * uses its own address translation component rather than ATU, so
789 * we should not program the ATU here.
790 */
791 if (!pp->ops->rd_other_conf)
792 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
793 PCIE_ATU_TYPE_MEM, pp->mem_base,
794 pp->mem_bus_addr, pp->mem_size);
795
796 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
797
798 /* program correct class for RC */
799 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
800
801 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
802 val |= PORT_LOGIC_SPEED_CHANGE;
803 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
804}
805
806MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
807MODULE_DESCRIPTION("Designware PCIe host controller driver");
808MODULE_LICENSE("GPL v2");