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1/*
2 * Copyright 2009 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * provides masks and opcode images for use by code generation, emulation
10 * and for instructions that older assemblers might not know about
11 */
12#ifndef _ASM_POWERPC_PPC_OPCODE_H
13#define _ASM_POWERPC_PPC_OPCODE_H
14
15#include <linux/stringify.h>
16#include <asm/asm-compat.h>
17
18#define __REG_R0 0
19#define __REG_R1 1
20#define __REG_R2 2
21#define __REG_R3 3
22#define __REG_R4 4
23#define __REG_R5 5
24#define __REG_R6 6
25#define __REG_R7 7
26#define __REG_R8 8
27#define __REG_R9 9
28#define __REG_R10 10
29#define __REG_R11 11
30#define __REG_R12 12
31#define __REG_R13 13
32#define __REG_R14 14
33#define __REG_R15 15
34#define __REG_R16 16
35#define __REG_R17 17
36#define __REG_R18 18
37#define __REG_R19 19
38#define __REG_R20 20
39#define __REG_R21 21
40#define __REG_R22 22
41#define __REG_R23 23
42#define __REG_R24 24
43#define __REG_R25 25
44#define __REG_R26 26
45#define __REG_R27 27
46#define __REG_R28 28
47#define __REG_R29 29
48#define __REG_R30 30
49#define __REG_R31 31
50
51#define __REGA0_0 0
52#define __REGA0_R1 1
53#define __REGA0_R2 2
54#define __REGA0_R3 3
55#define __REGA0_R4 4
56#define __REGA0_R5 5
57#define __REGA0_R6 6
58#define __REGA0_R7 7
59#define __REGA0_R8 8
60#define __REGA0_R9 9
61#define __REGA0_R10 10
62#define __REGA0_R11 11
63#define __REGA0_R12 12
64#define __REGA0_R13 13
65#define __REGA0_R14 14
66#define __REGA0_R15 15
67#define __REGA0_R16 16
68#define __REGA0_R17 17
69#define __REGA0_R18 18
70#define __REGA0_R19 19
71#define __REGA0_R20 20
72#define __REGA0_R21 21
73#define __REGA0_R22 22
74#define __REGA0_R23 23
75#define __REGA0_R24 24
76#define __REGA0_R25 25
77#define __REGA0_R26 26
78#define __REGA0_R27 27
79#define __REGA0_R28 28
80#define __REGA0_R29 29
81#define __REGA0_R30 30
82#define __REGA0_R31 31
83
84/* opcode and xopcode for instructions */
85#define OP_TRAP 3
86#define OP_TRAP_64 2
87
88#define OP_31_XOP_TRAP 4
89#define OP_31_XOP_LWZX 23
90#define OP_31_XOP_DCBST 54
91#define OP_31_XOP_LWZUX 55
92#define OP_31_XOP_TRAP_64 68
93#define OP_31_XOP_DCBF 86
94#define OP_31_XOP_LBZX 87
95#define OP_31_XOP_STWX 151
96#define OP_31_XOP_STBX 215
97#define OP_31_XOP_LBZUX 119
98#define OP_31_XOP_STBUX 247
99#define OP_31_XOP_LHZX 279
100#define OP_31_XOP_LHZUX 311
101#define OP_31_XOP_MFSPR 339
102#define OP_31_XOP_LHAX 343
103#define OP_31_XOP_LHAUX 375
104#define OP_31_XOP_STHX 407
105#define OP_31_XOP_STHUX 439
106#define OP_31_XOP_MTSPR 467
107#define OP_31_XOP_DCBI 470
108#define OP_31_XOP_LWBRX 534
109#define OP_31_XOP_TLBSYNC 566
110#define OP_31_XOP_STWBRX 662
111#define OP_31_XOP_LHBRX 790
112#define OP_31_XOP_STHBRX 918
113
114#define OP_LWZ 32
115#define OP_LD 58
116#define OP_LWZU 33
117#define OP_LBZ 34
118#define OP_LBZU 35
119#define OP_STW 36
120#define OP_STWU 37
121#define OP_STD 62
122#define OP_STB 38
123#define OP_STBU 39
124#define OP_LHZ 40
125#define OP_LHZU 41
126#define OP_LHA 42
127#define OP_LHAU 43
128#define OP_STH 44
129#define OP_STHU 45
130
131/* sorted alphabetically */
132#define PPC_INST_BHRBE 0x7c00025c
133#define PPC_INST_CLRBHRB 0x7c00035c
134#define PPC_INST_COPY 0x7c00060c
135#define PPC_INST_COPY_FIRST 0x7c20060c
136#define PPC_INST_CP_ABORT 0x7c00068c
137#define PPC_INST_DCBA 0x7c0005ec
138#define PPC_INST_DCBA_MASK 0xfc0007fe
139#define PPC_INST_DCBAL 0x7c2005ec
140#define PPC_INST_DCBZL 0x7c2007ec
141#define PPC_INST_ICBT 0x7c00002c
142#define PPC_INST_ICSWX 0x7c00032d
143#define PPC_INST_ICSWEPX 0x7c00076d
144#define PPC_INST_ISEL 0x7c00001e
145#define PPC_INST_ISEL_MASK 0xfc00003e
146#define PPC_INST_LDARX 0x7c0000a8
147#define PPC_INST_STDCX 0x7c0001ad
148#define PPC_INST_LSWI 0x7c0004aa
149#define PPC_INST_LSWX 0x7c00042a
150#define PPC_INST_LWARX 0x7c000028
151#define PPC_INST_STWCX 0x7c00012d
152#define PPC_INST_LWSYNC 0x7c2004ac
153#define PPC_INST_SYNC 0x7c0004ac
154#define PPC_INST_SYNC_MASK 0xfc0007fe
155#define PPC_INST_LXVD2X 0x7c000698
156#define PPC_INST_MCRXR 0x7c000400
157#define PPC_INST_MCRXR_MASK 0xfc0007fe
158#define PPC_INST_MFSPR_PVR 0x7c1f42a6
159#define PPC_INST_MFSPR_PVR_MASK 0xfc1fffff
160#define PPC_INST_MFTMR 0x7c0002dc
161#define PPC_INST_MSGSND 0x7c00019c
162#define PPC_INST_MSGCLR 0x7c0001dc
163#define PPC_INST_MSGSNDP 0x7c00011c
164#define PPC_INST_MTTMR 0x7c0003dc
165#define PPC_INST_NOP 0x60000000
166#define PPC_INST_PASTE 0x7c00070c
167#define PPC_INST_PASTE_LAST 0x7c20070d
168#define PPC_INST_POPCNTB 0x7c0000f4
169#define PPC_INST_POPCNTB_MASK 0xfc0007fe
170#define PPC_INST_POPCNTD 0x7c0003f4
171#define PPC_INST_POPCNTW 0x7c0002f4
172#define PPC_INST_RFCI 0x4c000066
173#define PPC_INST_RFDI 0x4c00004e
174#define PPC_INST_RFMCI 0x4c00004c
175#define PPC_INST_MFSPR_DSCR 0x7c1102a6
176#define PPC_INST_MFSPR_DSCR_MASK 0xfc1fffff
177#define PPC_INST_MTSPR_DSCR 0x7c1103a6
178#define PPC_INST_MTSPR_DSCR_MASK 0xfc1fffff
179#define PPC_INST_MFSPR_DSCR_USER 0x7c0302a6
180#define PPC_INST_MFSPR_DSCR_USER_MASK 0xfc1fffff
181#define PPC_INST_MTSPR_DSCR_USER 0x7c0303a6
182#define PPC_INST_MTSPR_DSCR_USER_MASK 0xfc1fffff
183#define PPC_INST_MFVSRD 0x7c000066
184#define PPC_INST_MTVSRD 0x7c000166
185#define PPC_INST_SLBFEE 0x7c0007a7
186#define PPC_INST_SLBIA 0x7c0003e4
187
188#define PPC_INST_STRING 0x7c00042a
189#define PPC_INST_STRING_MASK 0xfc0007fe
190#define PPC_INST_STRING_GEN_MASK 0xfc00067e
191
192#define PPC_INST_STSWI 0x7c0005aa
193#define PPC_INST_STSWX 0x7c00052a
194#define PPC_INST_STXVD2X 0x7c000798
195#define PPC_INST_TLBIE 0x7c000264
196#define PPC_INST_TLBIEL 0x7c000224
197#define PPC_INST_TLBILX 0x7c000024
198#define PPC_INST_WAIT 0x7c00007c
199#define PPC_INST_TLBIVAX 0x7c000624
200#define PPC_INST_TLBSRX_DOT 0x7c0006a5
201#define PPC_INST_VPMSUMW 0x10000488
202#define PPC_INST_VPMSUMD 0x100004c8
203#define PPC_INST_XXLOR 0xf0000510
204#define PPC_INST_XXSWAPD 0xf0000250
205#define PPC_INST_XVCPSGNDP 0xf0000780
206#define PPC_INST_TRECHKPT 0x7c0007dd
207#define PPC_INST_TRECLAIM 0x7c00075d
208#define PPC_INST_TABORT 0x7c00071d
209
210#define PPC_INST_NAP 0x4c000364
211#define PPC_INST_SLEEP 0x4c0003a4
212#define PPC_INST_WINKLE 0x4c0003e4
213
214#define PPC_INST_STOP 0x4c0002e4
215
216/* A2 specific instructions */
217#define PPC_INST_ERATWE 0x7c0001a6
218#define PPC_INST_ERATRE 0x7c000166
219#define PPC_INST_ERATILX 0x7c000066
220#define PPC_INST_ERATIVAX 0x7c000666
221#define PPC_INST_ERATSX 0x7c000126
222#define PPC_INST_ERATSX_DOT 0x7c000127
223
224/* Misc instructions for BPF compiler */
225#define PPC_INST_LBZ 0x88000000
226#define PPC_INST_LD 0xe8000000
227#define PPC_INST_LHZ 0xa0000000
228#define PPC_INST_LWZ 0x80000000
229#define PPC_INST_LHBRX 0x7c00062c
230#define PPC_INST_LDBRX 0x7c000428
231#define PPC_INST_STB 0x98000000
232#define PPC_INST_STH 0xb0000000
233#define PPC_INST_STD 0xf8000000
234#define PPC_INST_STDU 0xf8000001
235#define PPC_INST_STW 0x90000000
236#define PPC_INST_STWU 0x94000000
237#define PPC_INST_MFLR 0x7c0802a6
238#define PPC_INST_MTLR 0x7c0803a6
239#define PPC_INST_CMPWI 0x2c000000
240#define PPC_INST_CMPDI 0x2c200000
241#define PPC_INST_CMPW 0x7c000000
242#define PPC_INST_CMPD 0x7c200000
243#define PPC_INST_CMPLW 0x7c000040
244#define PPC_INST_CMPLD 0x7c200040
245#define PPC_INST_CMPLWI 0x28000000
246#define PPC_INST_CMPLDI 0x28200000
247#define PPC_INST_ADDI 0x38000000
248#define PPC_INST_ADDIS 0x3c000000
249#define PPC_INST_ADD 0x7c000214
250#define PPC_INST_SUB 0x7c000050
251#define PPC_INST_BLR 0x4e800020
252#define PPC_INST_BLRL 0x4e800021
253#define PPC_INST_MULLD 0x7c0001d2
254#define PPC_INST_MULLW 0x7c0001d6
255#define PPC_INST_MULHWU 0x7c000016
256#define PPC_INST_MULLI 0x1c000000
257#define PPC_INST_DIVWU 0x7c000396
258#define PPC_INST_DIVD 0x7c0003d2
259#define PPC_INST_RLWINM 0x54000000
260#define PPC_INST_RLWIMI 0x50000000
261#define PPC_INST_RLDICL 0x78000000
262#define PPC_INST_RLDICR 0x78000004
263#define PPC_INST_SLW 0x7c000030
264#define PPC_INST_SLD 0x7c000036
265#define PPC_INST_SRW 0x7c000430
266#define PPC_INST_SRD 0x7c000436
267#define PPC_INST_SRAD 0x7c000634
268#define PPC_INST_SRADI 0x7c000674
269#define PPC_INST_AND 0x7c000038
270#define PPC_INST_ANDDOT 0x7c000039
271#define PPC_INST_OR 0x7c000378
272#define PPC_INST_XOR 0x7c000278
273#define PPC_INST_ANDI 0x70000000
274#define PPC_INST_ORI 0x60000000
275#define PPC_INST_ORIS 0x64000000
276#define PPC_INST_XORI 0x68000000
277#define PPC_INST_XORIS 0x6c000000
278#define PPC_INST_NEG 0x7c0000d0
279#define PPC_INST_EXTSW 0x7c0007b4
280#define PPC_INST_BRANCH 0x48000000
281#define PPC_INST_BRANCH_COND 0x40800000
282#define PPC_INST_LBZCIX 0x7c0006aa
283#define PPC_INST_STBCIX 0x7c0007aa
284
285/* macros to insert fields into opcodes */
286#define ___PPC_RA(a) (((a) & 0x1f) << 16)
287#define ___PPC_RB(b) (((b) & 0x1f) << 11)
288#define ___PPC_RS(s) (((s) & 0x1f) << 21)
289#define ___PPC_RT(t) ___PPC_RS(t)
290#define ___PPC_R(r) (((r) & 0x1) << 16)
291#define ___PPC_PRS(prs) (((prs) & 0x1) << 17)
292#define ___PPC_RIC(ric) (((ric) & 0x3) << 18)
293#define __PPC_RA(a) ___PPC_RA(__REG_##a)
294#define __PPC_RA0(a) ___PPC_RA(__REGA0_##a)
295#define __PPC_RB(b) ___PPC_RB(__REG_##b)
296#define __PPC_RS(s) ___PPC_RS(__REG_##s)
297#define __PPC_RT(t) ___PPC_RT(__REG_##t)
298#define __PPC_XA(a) ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3))
299#define __PPC_XB(b) ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4))
300#define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
301#define __PPC_XT(s) __PPC_XS(s)
302#define __PPC_T_TLB(t) (((t) & 0x3) << 21)
303#define __PPC_WC(w) (((w) & 0x3) << 21)
304#define __PPC_WS(w) (((w) & 0x1f) << 11)
305#define __PPC_SH(s) __PPC_WS(s)
306#define __PPC_MB(s) (((s) & 0x1f) << 6)
307#define __PPC_ME(s) (((s) & 0x1f) << 1)
308#define __PPC_MB64(s) (__PPC_MB(s) | ((s) & 0x20))
309#define __PPC_ME64(s) __PPC_MB64(s)
310#define __PPC_BI(s) (((s) & 0x1f) << 16)
311#define __PPC_CT(t) (((t) & 0x0f) << 21)
312
313/*
314 * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
315 * larx with EH set as an illegal instruction.
316 */
317#ifdef CONFIG_PPC64
318#define __PPC_EH(eh) (((eh) & 0x1) << 0)
319#else
320#define __PPC_EH(eh) 0
321#endif
322
323/* Deal with instructions that older assemblers aren't aware of */
324#define PPC_CP_ABORT stringify_in_c(.long PPC_INST_CP_ABORT)
325#define PPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \
326 __PPC_RA(a) | __PPC_RB(b))
327#define PPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \
328 __PPC_RA(a) | __PPC_RB(b))
329#define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LDARX | \
330 ___PPC_RT(t) | ___PPC_RA(a) | \
331 ___PPC_RB(b) | __PPC_EH(eh))
332#define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LWARX | \
333 ___PPC_RT(t) | ___PPC_RA(a) | \
334 ___PPC_RB(b) | __PPC_EH(eh))
335#define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \
336 ___PPC_RB(b))
337#define PPC_MSGCLR(b) stringify_in_c(.long PPC_INST_MSGCLR | \
338 ___PPC_RB(b))
339#define PPC_MSGSNDP(b) stringify_in_c(.long PPC_INST_MSGSNDP | \
340 ___PPC_RB(b))
341#define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_INST_POPCNTB | \
342 __PPC_RA(a) | __PPC_RS(s))
343#define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_INST_POPCNTD | \
344 __PPC_RA(a) | __PPC_RS(s))
345#define PPC_POPCNTW(a, s) stringify_in_c(.long PPC_INST_POPCNTW | \
346 __PPC_RA(a) | __PPC_RS(s))
347#define PPC_RFCI stringify_in_c(.long PPC_INST_RFCI)
348#define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI)
349#define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI)
350#define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \
351 __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b))
352#define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b)
353#define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b)
354#define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b)
355#define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \
356 __PPC_WC(w))
357#define PPC_TLBIE(lp,a) stringify_in_c(.long PPC_INST_TLBIE | \
358 ___PPC_RB(a) | ___PPC_RS(lp))
359#define PPC_TLBIE_5(rb,rs,ric,prs,r) \
360 stringify_in_c(.long PPC_INST_TLBIE | \
361 ___PPC_RB(rb) | ___PPC_RS(rs) | \
362 ___PPC_RIC(ric) | ___PPC_PRS(prs) | \
363 ___PPC_R(r))
364#define PPC_TLBIEL(rb,rs,ric,prs,r) \
365 stringify_in_c(.long PPC_INST_TLBIEL | \
366 ___PPC_RB(rb) | ___PPC_RS(rs) | \
367 ___PPC_RIC(ric) | ___PPC_PRS(prs) | \
368 ___PPC_R(r))
369#define PPC_TLBSRX_DOT(a,b) stringify_in_c(.long PPC_INST_TLBSRX_DOT | \
370 __PPC_RA0(a) | __PPC_RB(b))
371#define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX | \
372 __PPC_RA0(a) | __PPC_RB(b))
373
374#define PPC_ERATWE(s, a, w) stringify_in_c(.long PPC_INST_ERATWE | \
375 __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
376#define PPC_ERATRE(s, a, w) stringify_in_c(.long PPC_INST_ERATRE | \
377 __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
378#define PPC_ERATILX(t, a, b) stringify_in_c(.long PPC_INST_ERATILX | \
379 __PPC_T_TLB(t) | __PPC_RA0(a) | \
380 __PPC_RB(b))
381#define PPC_ERATIVAX(s, a, b) stringify_in_c(.long PPC_INST_ERATIVAX | \
382 __PPC_RS(s) | __PPC_RA0(a) | __PPC_RB(b))
383#define PPC_ERATSX(t, a, w) stringify_in_c(.long PPC_INST_ERATSX | \
384 __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
385#define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_INST_ERATSX_DOT | \
386 __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
387#define PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_INST_SLBFEE | \
388 __PPC_RT(t) | __PPC_RB(b))
389#define PPC_ICBT(c,a,b) stringify_in_c(.long PPC_INST_ICBT | \
390 __PPC_CT(c) | __PPC_RA0(a) | __PPC_RB(b))
391/* PASemi instructions */
392#define LBZCIX(t,a,b) stringify_in_c(.long PPC_INST_LBZCIX | \
393 __PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b))
394#define STBCIX(s,a,b) stringify_in_c(.long PPC_INST_STBCIX | \
395 __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
396
397/*
398 * Define what the VSX XX1 form instructions will look like, then add
399 * the 128 bit load store instructions based on that.
400 */
401#define VSX_XX1(s, a, b) (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
402#define VSX_XX3(t, a, b) (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b))
403#define STXVD2X(s, a, b) stringify_in_c(.long PPC_INST_STXVD2X | \
404 VSX_XX1((s), a, b))
405#define LXVD2X(s, a, b) stringify_in_c(.long PPC_INST_LXVD2X | \
406 VSX_XX1((s), a, b))
407#define MFVRD(a, t) stringify_in_c(.long PPC_INST_MFVSRD | \
408 VSX_XX1((t)+32, a, R0))
409#define MTVRD(t, a) stringify_in_c(.long PPC_INST_MTVSRD | \
410 VSX_XX1((t)+32, a, R0))
411#define VPMSUMW(t, a, b) stringify_in_c(.long PPC_INST_VPMSUMW | \
412 VSX_XX3((t), a, b))
413#define VPMSUMD(t, a, b) stringify_in_c(.long PPC_INST_VPMSUMD | \
414 VSX_XX3((t), a, b))
415#define XXLOR(t, a, b) stringify_in_c(.long PPC_INST_XXLOR | \
416 VSX_XX3((t), a, b))
417#define XXSWAPD(t, a) stringify_in_c(.long PPC_INST_XXSWAPD | \
418 VSX_XX3((t), a, a))
419#define XVCPSGNDP(t, a, b) stringify_in_c(.long (PPC_INST_XVCPSGNDP | \
420 VSX_XX3((t), (a), (b))))
421
422#define PPC_NAP stringify_in_c(.long PPC_INST_NAP)
423#define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP)
424#define PPC_WINKLE stringify_in_c(.long PPC_INST_WINKLE)
425
426#define PPC_STOP stringify_in_c(.long PPC_INST_STOP)
427
428/* BHRB instructions */
429#define PPC_CLRBHRB stringify_in_c(.long PPC_INST_CLRBHRB)
430#define PPC_MFBHRBE(r, n) stringify_in_c(.long PPC_INST_BHRBE | \
431 __PPC_RT(r) | \
432 (((n) & 0x3ff) << 11))
433
434/* Transactional memory instructions */
435#define TRECHKPT stringify_in_c(.long PPC_INST_TRECHKPT)
436#define TRECLAIM(r) stringify_in_c(.long PPC_INST_TRECLAIM \
437 | __PPC_RA(r))
438#define TABORT(r) stringify_in_c(.long PPC_INST_TABORT \
439 | __PPC_RA(r))
440
441/* book3e thread control instructions */
442#define TMRN(x) ((((x) & 0x1f) << 16) | (((x) & 0x3e0) << 6))
443#define MTTMR(tmr, r) stringify_in_c(.long PPC_INST_MTTMR | \
444 TMRN(tmr) | ___PPC_RS(r))
445#define MFTMR(tmr, r) stringify_in_c(.long PPC_INST_MFTMR | \
446 TMRN(tmr) | ___PPC_RT(r))
447
448/* Coprocessor instructions */
449#define PPC_ICSWX(s, a, b) stringify_in_c(.long PPC_INST_ICSWX | \
450 ___PPC_RS(s) | \
451 ___PPC_RA(a) | \
452 ___PPC_RB(b))
453#define PPC_ICSWEPX(s, a, b) stringify_in_c(.long PPC_INST_ICSWEPX | \
454 ___PPC_RS(s) | \
455 ___PPC_RA(a) | \
456 ___PPC_RB(b))
457
458#define PPC_SLBIA(IH) stringify_in_c(.long PPC_INST_SLBIA | \
459 ((IH & 0x7) << 21))
460
461#endif /* _ASM_POWERPC_PPC_OPCODE_H */