Linux kernel mirror (for testing)
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linux
1/*
2 * include/asm-parisc/cache.h
3 */
4
5#ifndef __ARCH_PARISC_CACHE_H
6#define __ARCH_PARISC_CACHE_H
7
8
9/*
10 * PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors
11 * have 32-byte cachelines. The L1 length appears to be 16 bytes but this
12 * is not clearly documented.
13 */
14#define L1_CACHE_BYTES 16
15#define L1_CACHE_SHIFT 4
16
17#ifndef __ASSEMBLY__
18
19#define SMP_CACHE_BYTES L1_CACHE_BYTES
20
21#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
22
23#define __read_mostly __attribute__((__section__(".data..read_mostly")))
24
25/* Read-only memory is marked before mark_rodata_ro() is called. */
26#define __ro_after_init __read_mostly
27
28void parisc_cache_init(void); /* initializes cache-flushing */
29void disable_sr_hashing_asm(int); /* low level support for above */
30void disable_sr_hashing(void); /* turns off space register hashing */
31void free_sid(unsigned long);
32unsigned long alloc_sid(void);
33
34struct seq_file;
35extern void show_cache_info(struct seq_file *m);
36
37extern int split_tlb;
38extern int dcache_stride;
39extern int icache_stride;
40extern struct pdc_cache_info cache_info;
41void parisc_setup_cache_timing(void);
42
43#define pdtlb(addr) asm volatile("pdtlb 0(%%sr1,%0)" : : "r" (addr));
44#define pitlb(addr) asm volatile("pitlb 0(%%sr1,%0)" : : "r" (addr));
45#define pdtlb_kernel(addr) asm volatile("pdtlb 0(%0)" : : "r" (addr));
46
47#endif /* ! __ASSEMBLY__ */
48
49/* Classes of processor wrt: disabling space register hashing */
50
51#define SRHASH_PCXST 0 /* pcxs, pcxt, pcxt_ */
52#define SRHASH_PCXL 1 /* pcxl */
53#define SRHASH_PA20 2 /* pcxu, pcxu_, pcxw, pcxw_ */
54
55#endif