tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
3 *
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46#include "skeleton.dtsi"
47#include <dt-bindings/dma/at91.h>
48#include <dt-bindings/interrupt-controller/irq.h>
49#include <dt-bindings/clock/at91.h>
50
51/ {
52 model = "Atmel SAMA5D2 family SoC";
53 compatible = "atmel,sama5d2";
54 interrupt-parent = <&aic>;
55
56 aliases {
57 serial0 = &uart1;
58 serial1 = &uart3;
59 tcb0 = &tcb0;
60 tcb1 = &tcb1;
61 };
62
63 cpus {
64 #address-cells = <1>;
65 #size-cells = <0>;
66
67 cpu@0 {
68 device_type = "cpu";
69 compatible = "arm,cortex-a5";
70 reg = <0>;
71 next-level-cache = <&L2>;
72 };
73 };
74
75 pmu {
76 compatible = "arm,cortex-a5-pmu";
77 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
78 };
79
80 memory {
81 reg = <0x20000000 0x20000000>;
82 };
83
84 clocks {
85 slow_xtal: slow_xtal {
86 compatible = "fixed-clock";
87 #clock-cells = <0>;
88 clock-frequency = <0>;
89 };
90
91 main_xtal: main_xtal {
92 compatible = "fixed-clock";
93 #clock-cells = <0>;
94 clock-frequency = <0>;
95 };
96 };
97
98 ns_sram: sram@00200000 {
99 compatible = "mmio-sram";
100 reg = <0x00200000 0x20000>;
101 };
102
103 ahb {
104 compatible = "simple-bus";
105 #address-cells = <1>;
106 #size-cells = <1>;
107 ranges;
108
109 usb0: gadget@00300000 {
110 #address-cells = <1>;
111 #size-cells = <0>;
112 compatible = "atmel,sama5d3-udc";
113 reg = <0x00300000 0x100000
114 0xfc02c000 0x400>;
115 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
116 clocks = <&udphs_clk>, <&utmi>;
117 clock-names = "pclk", "hclk";
118 status = "disabled";
119
120 ep@0 {
121 reg = <0>;
122 atmel,fifo-size = <64>;
123 atmel,nb-banks = <1>;
124 };
125
126 ep@1 {
127 reg = <1>;
128 atmel,fifo-size = <1024>;
129 atmel,nb-banks = <3>;
130 atmel,can-dma;
131 atmel,can-isoc;
132 };
133
134 ep@2 {
135 reg = <2>;
136 atmel,fifo-size = <1024>;
137 atmel,nb-banks = <3>;
138 atmel,can-dma;
139 atmel,can-isoc;
140 };
141
142 ep@3 {
143 reg = <3>;
144 atmel,fifo-size = <1024>;
145 atmel,nb-banks = <2>;
146 atmel,can-dma;
147 atmel,can-isoc;
148 };
149
150 ep@4 {
151 reg = <4>;
152 atmel,fifo-size = <1024>;
153 atmel,nb-banks = <2>;
154 atmel,can-dma;
155 atmel,can-isoc;
156 };
157
158 ep@5 {
159 reg = <5>;
160 atmel,fifo-size = <1024>;
161 atmel,nb-banks = <2>;
162 atmel,can-dma;
163 atmel,can-isoc;
164 };
165
166 ep@6 {
167 reg = <6>;
168 atmel,fifo-size = <1024>;
169 atmel,nb-banks = <2>;
170 atmel,can-dma;
171 atmel,can-isoc;
172 };
173
174 ep@7 {
175 reg = <7>;
176 atmel,fifo-size = <1024>;
177 atmel,nb-banks = <2>;
178 atmel,can-dma;
179 atmel,can-isoc;
180 };
181
182 ep@8 {
183 reg = <8>;
184 atmel,fifo-size = <1024>;
185 atmel,nb-banks = <2>;
186 atmel,can-isoc;
187 };
188
189 ep@9 {
190 reg = <9>;
191 atmel,fifo-size = <1024>;
192 atmel,nb-banks = <2>;
193 atmel,can-isoc;
194 };
195
196 ep@10 {
197 reg = <10>;
198 atmel,fifo-size = <1024>;
199 atmel,nb-banks = <2>;
200 atmel,can-isoc;
201 };
202
203 ep@11 {
204 reg = <11>;
205 atmel,fifo-size = <1024>;
206 atmel,nb-banks = <2>;
207 atmel,can-isoc;
208 };
209
210 ep@12 {
211 reg = <12>;
212 atmel,fifo-size = <1024>;
213 atmel,nb-banks = <2>;
214 atmel,can-isoc;
215 };
216
217 ep@13 {
218 reg = <13>;
219 atmel,fifo-size = <1024>;
220 atmel,nb-banks = <2>;
221 atmel,can-isoc;
222 };
223
224 ep@14 {
225 reg = <14>;
226 atmel,fifo-size = <1024>;
227 atmel,nb-banks = <2>;
228 atmel,can-isoc;
229 };
230
231 ep@15 {
232 reg = <15>;
233 atmel,fifo-size = <1024>;
234 atmel,nb-banks = <2>;
235 atmel,can-isoc;
236 };
237 };
238
239 usb1: ohci@00400000 {
240 compatible = "atmel,sama5d2-ohci", "usb-ohci";
241 reg = <0x00400000 0x100000>;
242 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
243 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
244 clock-names = "ohci_clk", "hclk", "uhpck";
245 status = "disabled";
246 };
247
248 usb2: ehci@00500000 {
249 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
250 reg = <0x00500000 0x100000>;
251 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
252 clocks = <&utmi>, <&uhphs_clk>;
253 clock-names = "usb_clk", "ehci_clk";
254 status = "disabled";
255 };
256
257 L2: cache-controller@00a00000 {
258 compatible = "arm,pl310-cache";
259 reg = <0x00a00000 0x1000>;
260 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
261 cache-unified;
262 cache-level = <2>;
263 };
264
265 nand0: nand@80000000 {
266 compatible = "atmel,sama5d2-nand";
267 #address-cells = <1>;
268 #size-cells = <1>;
269 ranges;
270 reg = < /* EBI CS3 */
271 0x80000000 0x08000000
272 /* SMC PMECC regs */
273 0xf8014070 0x00000490
274 /* SMC PMECC Error Location regs */
275 0xf8014500 0x00000200
276 /* ROM Galois tables */
277 0x00040000 0x00018000
278 >;
279 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
280 atmel,nand-addr-offset = <21>;
281 atmel,nand-cmd-offset = <22>;
282 atmel,nand-has-dma;
283 atmel,has-pmecc;
284 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
285 status = "disabled";
286
287 nfc@c0000000 {
288 compatible = "atmel,sama5d3-nfc";
289 #address-cells = <1>;
290 #size-cells = <1>;
291 reg = < /* NFC Command Registers */
292 0xc0000000 0x08000000
293 /* NFC HSMC regs */
294 0xf8014000 0x00000070
295 /* NFC SRAM banks */
296 0x00100000 0x00100000
297 >;
298 clocks = <&hsmc_clk>;
299 atmel,write-by-sram;
300 };
301 };
302
303 sdmmc0: sdio-host@a0000000 {
304 compatible = "atmel,sama5d2-sdhci";
305 reg = <0xa0000000 0x300>;
306 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
307 clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
308 clock-names = "hclock", "multclk", "baseclk";
309 status = "disabled";
310 };
311
312 sdmmc1: sdio-host@b0000000 {
313 compatible = "atmel,sama5d2-sdhci";
314 reg = <0xb0000000 0x300>;
315 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
316 clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
317 clock-names = "hclock", "multclk", "baseclk";
318 status = "disabled";
319 };
320
321 apb {
322 compatible = "simple-bus";
323 #address-cells = <1>;
324 #size-cells = <1>;
325 ranges;
326
327 hlcdc: hlcdc@f0000000 {
328 compatible = "atmel,sama5d2-hlcdc";
329 reg = <0xf0000000 0x2000>;
330 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
331 clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
332 clock-names = "periph_clk","sys_clk", "slow_clk";
333 status = "disabled";
334
335 hlcdc-display-controller {
336 compatible = "atmel,hlcdc-display-controller";
337 #address-cells = <1>;
338 #size-cells = <0>;
339
340 port@0 {
341 #address-cells = <1>;
342 #size-cells = <0>;
343 reg = <0>;
344 };
345 };
346
347 hlcdc_pwm: hlcdc-pwm {
348 compatible = "atmel,hlcdc-pwm";
349 #pwm-cells = <3>;
350 };
351 };
352
353 ramc0: ramc@f000c000 {
354 compatible = "atmel,sama5d3-ddramc";
355 reg = <0xf000c000 0x200>;
356 clocks = <&ddrck>, <&mpddr_clk>;
357 clock-names = "ddrck", "mpddr";
358 };
359
360 dma0: dma-controller@f0010000 {
361 compatible = "atmel,sama5d4-dma";
362 reg = <0xf0010000 0x1000>;
363 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
364 #dma-cells = <1>;
365 clocks = <&dma0_clk>;
366 clock-names = "dma_clk";
367 };
368
369 pmc: pmc@f0014000 {
370 compatible = "atmel,sama5d2-pmc", "syscon";
371 reg = <0xf0014000 0x160>;
372 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
373 interrupt-controller;
374 #address-cells = <1>;
375 #size-cells = <0>;
376 #interrupt-cells = <1>;
377
378 main_rc_osc: main_rc_osc {
379 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
380 #clock-cells = <0>;
381 interrupt-parent = <&pmc>;
382 interrupts = <AT91_PMC_MOSCRCS>;
383 clock-frequency = <12000000>;
384 clock-accuracy = <100000000>;
385 };
386
387 main_osc: main_osc {
388 compatible = "atmel,at91rm9200-clk-main-osc";
389 #clock-cells = <0>;
390 interrupt-parent = <&pmc>;
391 interrupts = <AT91_PMC_MOSCS>;
392 clocks = <&main_xtal>;
393 };
394
395 main: mainck {
396 compatible = "atmel,at91sam9x5-clk-main";
397 #clock-cells = <0>;
398 interrupt-parent = <&pmc>;
399 interrupts = <AT91_PMC_MOSCSELS>;
400 clocks = <&main_rc_osc &main_osc>;
401 };
402
403 plla: pllack {
404 compatible = "atmel,sama5d3-clk-pll";
405 #clock-cells = <0>;
406 interrupt-parent = <&pmc>;
407 interrupts = <AT91_PMC_LOCKA>;
408 clocks = <&main>;
409 reg = <0>;
410 atmel,clk-input-range = <12000000 12000000>;
411 #atmel,pll-clk-output-range-cells = <4>;
412 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
413 };
414
415 plladiv: plladivck {
416 compatible = "atmel,at91sam9x5-clk-plldiv";
417 #clock-cells = <0>;
418 clocks = <&plla>;
419 };
420
421 utmi: utmick {
422 compatible = "atmel,at91sam9x5-clk-utmi";
423 #clock-cells = <0>;
424 interrupt-parent = <&pmc>;
425 interrupts = <AT91_PMC_LOCKU>;
426 clocks = <&main>;
427 };
428
429 mck: masterck {
430 compatible = "atmel,at91sam9x5-clk-master";
431 #clock-cells = <0>;
432 interrupt-parent = <&pmc>;
433 interrupts = <AT91_PMC_MCKRDY>;
434 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
435 atmel,clk-output-range = <124000000 166000000>;
436 atmel,clk-divisors = <1 2 4 3>;
437 };
438
439 h32ck: h32mxck {
440 #clock-cells = <0>;
441 compatible = "atmel,sama5d4-clk-h32mx";
442 clocks = <&mck>;
443 };
444
445 usb: usbck {
446 compatible = "atmel,at91sam9x5-clk-usb";
447 #clock-cells = <0>;
448 clocks = <&plladiv>, <&utmi>;
449 };
450
451 prog: progck {
452 compatible = "atmel,at91sam9x5-clk-programmable";
453 #address-cells = <1>;
454 #size-cells = <0>;
455 interrupt-parent = <&pmc>;
456 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
457
458 prog0: prog0 {
459 #clock-cells = <0>;
460 reg = <0>;
461 interrupts = <AT91_PMC_PCKRDY(0)>;
462 };
463
464 prog1: prog1 {
465 #clock-cells = <0>;
466 reg = <1>;
467 interrupts = <AT91_PMC_PCKRDY(1)>;
468 };
469
470 prog2: prog2 {
471 #clock-cells = <0>;
472 reg = <2>;
473 interrupts = <AT91_PMC_PCKRDY(2)>;
474 };
475 };
476
477 systemck {
478 compatible = "atmel,at91rm9200-clk-system";
479 #address-cells = <1>;
480 #size-cells = <0>;
481
482 ddrck: ddrck {
483 #clock-cells = <0>;
484 reg = <2>;
485 clocks = <&mck>;
486 };
487
488 lcdck: lcdck {
489 #clock-cells = <0>;
490 reg = <3>;
491 clocks = <&mck>;
492 };
493
494 uhpck: uhpck {
495 #clock-cells = <0>;
496 reg = <6>;
497 clocks = <&usb>;
498 };
499
500 udpck: udpck {
501 #clock-cells = <0>;
502 reg = <7>;
503 clocks = <&usb>;
504 };
505
506 pck0: pck0 {
507 #clock-cells = <0>;
508 reg = <8>;
509 clocks = <&prog0>;
510 };
511
512 pck1: pck1 {
513 #clock-cells = <0>;
514 reg = <9>;
515 clocks = <&prog1>;
516 };
517
518 pck2: pck2 {
519 #clock-cells = <0>;
520 reg = <10>;
521 clocks = <&prog2>;
522 };
523
524 iscck: iscck {
525 #clock-cells = <0>;
526 reg = <18>;
527 clocks = <&mck>;
528 };
529 };
530
531 periph32ck {
532 compatible = "atmel,at91sam9x5-clk-peripheral";
533 #address-cells = <1>;
534 #size-cells = <0>;
535 clocks = <&h32ck>;
536
537 macb0_clk: macb0_clk {
538 #clock-cells = <0>;
539 reg = <5>;
540 atmel,clk-output-range = <0 83000000>;
541 };
542
543 tdes_clk: tdes_clk {
544 #clock-cells = <0>;
545 reg = <11>;
546 atmel,clk-output-range = <0 83000000>;
547 };
548
549 matrix1_clk: matrix1_clk {
550 #clock-cells = <0>;
551 reg = <14>;
552 };
553
554 hsmc_clk: hsmc_clk {
555 #clock-cells = <0>;
556 reg = <17>;
557 };
558
559 pioA_clk: pioA_clk {
560 #clock-cells = <0>;
561 reg = <18>;
562 atmel,clk-output-range = <0 83000000>;
563 };
564
565 flx0_clk: flx0_clk {
566 #clock-cells = <0>;
567 reg = <19>;
568 atmel,clk-output-range = <0 83000000>;
569 };
570
571 flx1_clk: flx1_clk {
572 #clock-cells = <0>;
573 reg = <20>;
574 atmel,clk-output-range = <0 83000000>;
575 };
576
577 flx2_clk: flx2_clk {
578 #clock-cells = <0>;
579 reg = <21>;
580 atmel,clk-output-range = <0 83000000>;
581 };
582
583 flx3_clk: flx3_clk {
584 #clock-cells = <0>;
585 reg = <22>;
586 atmel,clk-output-range = <0 83000000>;
587 };
588
589 flx4_clk: flx4_clk {
590 #clock-cells = <0>;
591 reg = <23>;
592 atmel,clk-output-range = <0 83000000>;
593 };
594
595 uart0_clk: uart0_clk {
596 #clock-cells = <0>;
597 reg = <24>;
598 atmel,clk-output-range = <0 83000000>;
599 };
600
601 uart1_clk: uart1_clk {
602 #clock-cells = <0>;
603 reg = <25>;
604 atmel,clk-output-range = <0 83000000>;
605 };
606
607 uart2_clk: uart2_clk {
608 #clock-cells = <0>;
609 reg = <26>;
610 atmel,clk-output-range = <0 83000000>;
611 };
612
613 uart3_clk: uart3_clk {
614 #clock-cells = <0>;
615 reg = <27>;
616 atmel,clk-output-range = <0 83000000>;
617 };
618
619 uart4_clk: uart4_clk {
620 #clock-cells = <0>;
621 reg = <28>;
622 atmel,clk-output-range = <0 83000000>;
623 };
624
625 twi0_clk: twi0_clk {
626 reg = <29>;
627 #clock-cells = <0>;
628 atmel,clk-output-range = <0 83000000>;
629 };
630
631 twi1_clk: twi1_clk {
632 #clock-cells = <0>;
633 reg = <30>;
634 atmel,clk-output-range = <0 83000000>;
635 };
636
637 spi0_clk: spi0_clk {
638 #clock-cells = <0>;
639 reg = <33>;
640 atmel,clk-output-range = <0 83000000>;
641 };
642
643 spi1_clk: spi1_clk {
644 #clock-cells = <0>;
645 reg = <34>;
646 atmel,clk-output-range = <0 83000000>;
647 };
648
649 tcb0_clk: tcb0_clk {
650 #clock-cells = <0>;
651 reg = <35>;
652 atmel,clk-output-range = <0 83000000>;
653 };
654
655 tcb1_clk: tcb1_clk {
656 #clock-cells = <0>;
657 reg = <36>;
658 atmel,clk-output-range = <0 83000000>;
659 };
660
661 pwm_clk: pwm_clk {
662 #clock-cells = <0>;
663 reg = <38>;
664 atmel,clk-output-range = <0 83000000>;
665 };
666
667 adc_clk: adc_clk {
668 #clock-cells = <0>;
669 reg = <40>;
670 atmel,clk-output-range = <0 83000000>;
671 };
672
673 uhphs_clk: uhphs_clk {
674 #clock-cells = <0>;
675 reg = <41>;
676 atmel,clk-output-range = <0 83000000>;
677 };
678
679 udphs_clk: udphs_clk {
680 #clock-cells = <0>;
681 reg = <42>;
682 atmel,clk-output-range = <0 83000000>;
683 };
684
685 ssc0_clk: ssc0_clk {
686 #clock-cells = <0>;
687 reg = <43>;
688 atmel,clk-output-range = <0 83000000>;
689 };
690
691 ssc1_clk: ssc1_clk {
692 #clock-cells = <0>;
693 reg = <44>;
694 atmel,clk-output-range = <0 83000000>;
695 };
696
697 trng_clk: trng_clk {
698 #clock-cells = <0>;
699 reg = <47>;
700 atmel,clk-output-range = <0 83000000>;
701 };
702
703 pdmic_clk: pdmic_clk {
704 #clock-cells = <0>;
705 reg = <48>;
706 atmel,clk-output-range = <0 83000000>;
707 };
708
709 i2s0_clk: i2s0_clk {
710 #clock-cells = <0>;
711 reg = <54>;
712 atmel,clk-output-range = <0 83000000>;
713 };
714
715 i2s1_clk: i2s1_clk {
716 #clock-cells = <0>;
717 reg = <55>;
718 atmel,clk-output-range = <0 83000000>;
719 };
720
721 classd_clk: classd_clk {
722 #clock-cells = <0>;
723 reg = <59>;
724 atmel,clk-output-range = <0 83000000>;
725 };
726 };
727
728 periph64ck {
729 compatible = "atmel,at91sam9x5-clk-peripheral";
730 #address-cells = <1>;
731 #size-cells = <0>;
732 clocks = <&mck>;
733
734 dma0_clk: dma0_clk {
735 #clock-cells = <0>;
736 reg = <6>;
737 };
738
739 dma1_clk: dma1_clk {
740 #clock-cells = <0>;
741 reg = <7>;
742 };
743
744 aes_clk: aes_clk {
745 #clock-cells = <0>;
746 reg = <9>;
747 };
748
749 aesb_clk: aesb_clk {
750 #clock-cells = <0>;
751 reg = <10>;
752 };
753
754 sha_clk: sha_clk {
755 #clock-cells = <0>;
756 reg = <12>;
757 };
758
759 mpddr_clk: mpddr_clk {
760 #clock-cells = <0>;
761 reg = <13>;
762 };
763
764 matrix0_clk: matrix0_clk {
765 #clock-cells = <0>;
766 reg = <15>;
767 };
768
769 sdmmc0_hclk: sdmmc0_hclk {
770 #clock-cells = <0>;
771 reg = <31>;
772 };
773
774 sdmmc1_hclk: sdmmc1_hclk {
775 #clock-cells = <0>;
776 reg = <32>;
777 };
778
779 lcdc_clk: lcdc_clk {
780 #clock-cells = <0>;
781 reg = <45>;
782 };
783
784 isc_clk: isc_clk {
785 #clock-cells = <0>;
786 reg = <46>;
787 };
788
789 qspi0_clk: qspi0_clk {
790 #clock-cells = <0>;
791 reg = <52>;
792 };
793
794 qspi1_clk: qspi1_clk {
795 #clock-cells = <0>;
796 reg = <53>;
797 };
798 };
799
800 gck {
801 compatible = "atmel,sama5d2-clk-generated";
802 #address-cells = <1>;
803 #size-cells = <0>;
804 interrupt-parent = <&pmc>;
805 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
806
807 sdmmc0_gclk: sdmmc0_gclk {
808 #clock-cells = <0>;
809 reg = <31>;
810 };
811
812 sdmmc1_gclk: sdmmc1_gclk {
813 #clock-cells = <0>;
814 reg = <32>;
815 };
816
817 tcb0_gclk: tcb0_gclk {
818 #clock-cells = <0>;
819 reg = <35>;
820 atmel,clk-output-range = <0 83000000>;
821 };
822
823 tcb1_gclk: tcb1_gclk {
824 #clock-cells = <0>;
825 reg = <36>;
826 atmel,clk-output-range = <0 83000000>;
827 };
828
829 pwm_gclk: pwm_gclk {
830 #clock-cells = <0>;
831 reg = <38>;
832 atmel,clk-output-range = <0 83000000>;
833 };
834
835 pdmic_gclk: pdmic_gclk {
836 #clock-cells = <0>;
837 reg = <48>;
838 };
839
840 i2s0_gclk: i2s0_gclk {
841 #clock-cells = <0>;
842 reg = <54>;
843 };
844
845 i2s1_gclk: i2s1_gclk {
846 #clock-cells = <0>;
847 reg = <55>;
848 };
849 };
850 };
851
852 sha@f0028000 {
853 compatible = "atmel,at91sam9g46-sha";
854 reg = <0xf0028000 0x100>;
855 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
856 dmas = <&dma0
857 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
858 AT91_XDMAC_DT_PERID(30))>;
859 dma-names = "tx";
860 clocks = <&sha_clk>;
861 clock-names = "sha_clk";
862 status = "okay";
863 };
864
865 aes@f002c000 {
866 compatible = "atmel,at91sam9g46-aes";
867 reg = <0xf002c000 0x100>;
868 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
869 dmas = <&dma0
870 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
871 AT91_XDMAC_DT_PERID(26))>,
872 <&dma0
873 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
874 AT91_XDMAC_DT_PERID(27))>;
875 dma-names = "tx", "rx";
876 clocks = <&aes_clk>;
877 clock-names = "aes_clk";
878 status = "okay";
879 };
880
881 spi0: spi@f8000000 {
882 compatible = "atmel,at91rm9200-spi";
883 reg = <0xf8000000 0x100>;
884 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
885 dmas = <&dma0
886 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
887 AT91_XDMAC_DT_PERID(6))>,
888 <&dma0
889 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
890 AT91_XDMAC_DT_PERID(7))>;
891 dma-names = "tx", "rx";
892 clocks = <&spi0_clk>;
893 clock-names = "spi_clk";
894 atmel,fifo-size = <16>;
895 #address-cells = <1>;
896 #size-cells = <0>;
897 status = "disabled";
898 };
899
900 macb0: ethernet@f8008000 {
901 compatible = "atmel,sama5d2-gem";
902 reg = <0xf8008000 0x1000>;
903 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
904 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */
905 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
906 #address-cells = <1>;
907 #size-cells = <0>;
908 clocks = <&macb0_clk>, <&macb0_clk>;
909 clock-names = "hclk", "pclk";
910 status = "disabled";
911 };
912
913 tcb0: timer@f800c000 {
914 compatible = "atmel,at91sam9x5-tcb";
915 reg = <0xf800c000 0x100>;
916 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
917 clocks = <&tcb0_clk>, <&clk32k>;
918 clock-names = "t0_clk", "slow_clk";
919 };
920
921 tcb1: timer@f8010000 {
922 compatible = "atmel,at91sam9x5-tcb";
923 reg = <0xf8010000 0x100>;
924 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
925 clocks = <&tcb1_clk>, <&clk32k>;
926 clock-names = "t0_clk", "slow_clk";
927 };
928
929 pdmic: pdmic@f8018000 {
930 compatible = "atmel,sama5d2-pdmic";
931 reg = <0xf8018000 0x124>;
932 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
933 dmas = <&dma0
934 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
935 | AT91_XDMAC_DT_PERID(50))>;
936 dma-names = "rx";
937 clocks = <&pdmic_clk>, <&pdmic_gclk>;
938 clock-names = "pclk", "gclk";
939 status = "disabled";
940 };
941
942 uart0: serial@f801c000 {
943 compatible = "atmel,at91sam9260-usart";
944 reg = <0xf801c000 0x100>;
945 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
946 dmas = <&dma0
947 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
948 AT91_XDMAC_DT_PERID(35))>,
949 <&dma0
950 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
951 AT91_XDMAC_DT_PERID(36))>;
952 dma-names = "tx", "rx";
953 clocks = <&uart0_clk>;
954 clock-names = "usart";
955 status = "disabled";
956 };
957
958 uart1: serial@f8020000 {
959 compatible = "atmel,at91sam9260-usart";
960 reg = <0xf8020000 0x100>;
961 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
962 dmas = <&dma0
963 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
964 AT91_XDMAC_DT_PERID(37))>,
965 <&dma0
966 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
967 AT91_XDMAC_DT_PERID(38))>;
968 dma-names = "tx", "rx";
969 clocks = <&uart1_clk>;
970 clock-names = "usart";
971 status = "disabled";
972 };
973
974 uart2: serial@f8024000 {
975 compatible = "atmel,at91sam9260-usart";
976 reg = <0xf8024000 0x100>;
977 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
978 dmas = <&dma0
979 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
980 AT91_XDMAC_DT_PERID(39))>,
981 <&dma0
982 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
983 AT91_XDMAC_DT_PERID(40))>;
984 dma-names = "tx", "rx";
985 clocks = <&uart2_clk>;
986 clock-names = "usart";
987 status = "disabled";
988 };
989
990 i2c0: i2c@f8028000 {
991 compatible = "atmel,sama5d2-i2c";
992 reg = <0xf8028000 0x100>;
993 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
994 dmas = <&dma0
995 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
996 AT91_XDMAC_DT_PERID(0))>,
997 <&dma0
998 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
999 AT91_XDMAC_DT_PERID(1))>;
1000 dma-names = "tx", "rx";
1001 #address-cells = <1>;
1002 #size-cells = <0>;
1003 clocks = <&twi0_clk>;
1004 status = "disabled";
1005 };
1006
1007 sfr: sfr@f8030000 {
1008 compatible = "atmel,sama5d2-sfr", "syscon";
1009 reg = <0xf8030000 0x98>;
1010 };
1011
1012 flx0: flexcom@f8034000 {
1013 compatible = "atmel,sama5d2-flexcom";
1014 reg = <0xf8034000 0x200>;
1015 clocks = <&flx0_clk>;
1016 #address-cells = <1>;
1017 #size-cells = <1>;
1018 ranges = <0x0 0xf8034000 0x800>;
1019 status = "disabled";
1020 };
1021
1022 flx1: flexcom@f8038000 {
1023 compatible = "atmel,sama5d2-flexcom";
1024 reg = <0xf8038000 0x200>;
1025 clocks = <&flx1_clk>;
1026 #address-cells = <1>;
1027 #size-cells = <1>;
1028 ranges = <0x0 0xf8038000 0x800>;
1029 status = "disabled";
1030 };
1031
1032 rstc@f8048000 {
1033 compatible = "atmel,sama5d3-rstc";
1034 reg = <0xf8048000 0x10>;
1035 clocks = <&clk32k>;
1036 };
1037
1038 shdwc@f8048010 {
1039 compatible = "atmel,sama5d2-shdwc";
1040 reg = <0xf8048010 0x10>;
1041 clocks = <&clk32k>;
1042 #address-cells = <1>;
1043 #size-cells = <0>;
1044 atmel,wakeup-rtc-timer;
1045 };
1046
1047 pit: timer@f8048030 {
1048 compatible = "atmel,at91sam9260-pit";
1049 reg = <0xf8048030 0x10>;
1050 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1051 clocks = <&h32ck>;
1052 };
1053
1054 watchdog@f8048040 {
1055 compatible = "atmel,sama5d4-wdt";
1056 reg = <0xf8048040 0x10>;
1057 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1058 clocks = <&clk32k>;
1059 status = "disabled";
1060 };
1061
1062 sckc@f8048050 {
1063 compatible = "atmel,at91sam9x5-sckc";
1064 reg = <0xf8048050 0x4>;
1065
1066 slow_rc_osc: slow_rc_osc {
1067 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1068 #clock-cells = <0>;
1069 clock-frequency = <32768>;
1070 clock-accuracy = <250000000>;
1071 atmel,startup-time-usec = <75>;
1072 };
1073
1074 slow_osc: slow_osc {
1075 compatible = "atmel,at91sam9x5-clk-slow-osc";
1076 #clock-cells = <0>;
1077 clocks = <&slow_xtal>;
1078 atmel,startup-time-usec = <1200000>;
1079 };
1080
1081 clk32k: slowck {
1082 compatible = "atmel,at91sam9x5-clk-slow";
1083 #clock-cells = <0>;
1084 clocks = <&slow_rc_osc &slow_osc>;
1085 };
1086 };
1087
1088 rtc@f80480b0 {
1089 compatible = "atmel,at91rm9200-rtc";
1090 reg = <0xf80480b0 0x30>;
1091 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
1092 clocks = <&clk32k>;
1093 };
1094
1095 spi1: spi@fc000000 {
1096 compatible = "atmel,at91rm9200-spi";
1097 reg = <0xfc000000 0x100>;
1098 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
1099 dmas = <&dma0
1100 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1101 AT91_XDMAC_DT_PERID(8))>,
1102 <&dma0
1103 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1104 AT91_XDMAC_DT_PERID(9))>;
1105 dma-names = "tx", "rx";
1106 clocks = <&spi1_clk>;
1107 clock-names = "spi_clk";
1108 atmel,fifo-size = <16>;
1109 #address-cells = <1>;
1110 #size-cells = <0>;
1111 status = "disabled";
1112 };
1113
1114 uart3: serial@fc008000 {
1115 compatible = "atmel,at91sam9260-usart";
1116 reg = <0xfc008000 0x100>;
1117 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
1118 dmas = <&dma0
1119 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1120 AT91_XDMAC_DT_PERID(41))>,
1121 <&dma0
1122 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1123 AT91_XDMAC_DT_PERID(42))>;
1124 dma-names = "tx", "rx";
1125 clocks = <&uart3_clk>;
1126 clock-names = "usart";
1127 status = "disabled";
1128 };
1129
1130 uart4: serial@fc00c000 {
1131 compatible = "atmel,at91sam9260-usart";
1132 reg = <0xfc00c000 0x100>;
1133 dmas = <&dma0
1134 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1135 AT91_XDMAC_DT_PERID(43))>,
1136 <&dma0
1137 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1138 AT91_XDMAC_DT_PERID(44))>;
1139 dma-names = "tx", "rx";
1140 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
1141 clocks = <&uart4_clk>;
1142 clock-names = "usart";
1143 status = "disabled";
1144 };
1145
1146 flx2: flexcom@fc010000 {
1147 compatible = "atmel,sama5d2-flexcom";
1148 reg = <0xfc010000 0x200>;
1149 clocks = <&flx2_clk>;
1150 #address-cells = <1>;
1151 #size-cells = <1>;
1152 ranges = <0x0 0xfc010000 0x800>;
1153 status = "disabled";
1154 };
1155
1156 flx3: flexcom@fc014000 {
1157 compatible = "atmel,sama5d2-flexcom";
1158 reg = <0xfc014000 0x200>;
1159 clocks = <&flx3_clk>;
1160 #address-cells = <1>;
1161 #size-cells = <1>;
1162 ranges = <0x0 0xfc014000 0x800>;
1163 status = "disabled";
1164 };
1165
1166 flx4: flexcom@fc018000 {
1167 compatible = "atmel,sama5d2-flexcom";
1168 reg = <0xfc018000 0x200>;
1169 clocks = <&flx4_clk>;
1170 #address-cells = <1>;
1171 #size-cells = <1>;
1172 ranges = <0x0 0xfc018000 0x800>;
1173 status = "disabled";
1174 };
1175
1176 trng@fc01c000 {
1177 compatible = "atmel,at91sam9g45-trng";
1178 reg = <0xfc01c000 0x100>;
1179 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
1180 clocks = <&trng_clk>;
1181 };
1182
1183 aic: interrupt-controller@fc020000 {
1184 #interrupt-cells = <3>;
1185 compatible = "atmel,sama5d2-aic";
1186 interrupt-controller;
1187 reg = <0xfc020000 0x200>;
1188 atmel,external-irqs = <49>;
1189 };
1190
1191 i2c1: i2c@fc028000 {
1192 compatible = "atmel,sama5d2-i2c";
1193 reg = <0xfc028000 0x100>;
1194 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
1195 dmas = <&dma0
1196 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1197 AT91_XDMAC_DT_PERID(2))>,
1198 <&dma0
1199 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1200 AT91_XDMAC_DT_PERID(3))>;
1201 dma-names = "tx", "rx";
1202 #address-cells = <1>;
1203 #size-cells = <0>;
1204 clocks = <&twi1_clk>;
1205 status = "disabled";
1206 };
1207
1208 adc: adc@fc030000 {
1209 compatible = "atmel,sama5d2-adc";
1210 reg = <0xfc030000 0x100>;
1211 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
1212 clocks = <&adc_clk>;
1213 clock-names = "adc_clk";
1214 atmel,min-sample-rate-hz = <200000>;
1215 atmel,max-sample-rate-hz = <20000000>;
1216 atmel,startup-time-ms = <4>;
1217 status = "disabled";
1218 };
1219
1220 pioA: pinctrl@fc038000 {
1221 compatible = "atmel,sama5d2-pinctrl";
1222 reg = <0xfc038000 0x600>;
1223 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
1224 <68 IRQ_TYPE_LEVEL_HIGH 7>,
1225 <69 IRQ_TYPE_LEVEL_HIGH 7>,
1226 <70 IRQ_TYPE_LEVEL_HIGH 7>;
1227 interrupt-controller;
1228 #interrupt-cells = <2>;
1229 gpio-controller;
1230 #gpio-cells = <2>;
1231 clocks = <&pioA_clk>;
1232 };
1233
1234 tdes@fc044000 {
1235 compatible = "atmel,at91sam9g46-tdes";
1236 reg = <0xfc044000 0x100>;
1237 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1238 dmas = <&dma0
1239 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1240 AT91_XDMAC_DT_PERID(28))>,
1241 <&dma0
1242 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1243 AT91_XDMAC_DT_PERID(29))>;
1244 dma-names = "tx", "rx";
1245 clocks = <&tdes_clk>;
1246 clock-names = "tdes_clk";
1247 status = "okay";
1248 };
1249
1250 chipid@fc069000 {
1251 compatible = "atmel,sama5d2-chipid";
1252 reg = <0xfc069000 0x8>;
1253 };
1254 };
1255 };
1256};