tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Error Corrected Code Controller (ECC) - System peripherals regsters.
3 * Based on AT91SAM9260 datasheet revision B.
4 *
5 * Copyright (C) 2007 Andrew Victor
6 * Copyright (C) 2007 - 2012 Atmel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#ifndef ATMEL_NAND_ECC_H
15#define ATMEL_NAND_ECC_H
16
17#define ATMEL_ECC_CR 0x00 /* Control register */
18#define ATMEL_ECC_RST (1 << 0) /* Reset parity */
19
20#define ATMEL_ECC_MR 0x04 /* Mode register */
21#define ATMEL_ECC_PAGESIZE (3 << 0) /* Page Size */
22#define ATMEL_ECC_PAGESIZE_528 (0)
23#define ATMEL_ECC_PAGESIZE_1056 (1)
24#define ATMEL_ECC_PAGESIZE_2112 (2)
25#define ATMEL_ECC_PAGESIZE_4224 (3)
26
27#define ATMEL_ECC_SR 0x08 /* Status register */
28#define ATMEL_ECC_RECERR (1 << 0) /* Recoverable Error */
29#define ATMEL_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */
30#define ATMEL_ECC_MULERR (1 << 2) /* Multiple Errors */
31
32#define ATMEL_ECC_PR 0x0c /* Parity register */
33#define ATMEL_ECC_BITADDR (0xf << 0) /* Bit Error Address */
34#define ATMEL_ECC_WORDADDR (0xfff << 4) /* Word Error Address */
35
36#define ATMEL_ECC_NPR 0x10 /* NParity register */
37#define ATMEL_ECC_NPARITY (0xffff << 0) /* NParity */
38
39/* PMECC Register Definitions */
40#define ATMEL_PMECC_CFG 0x000 /* Configuration Register */
41#define PMECC_CFG_BCH_ERR2 (0 << 0)
42#define PMECC_CFG_BCH_ERR4 (1 << 0)
43#define PMECC_CFG_BCH_ERR8 (2 << 0)
44#define PMECC_CFG_BCH_ERR12 (3 << 0)
45#define PMECC_CFG_BCH_ERR24 (4 << 0)
46#define PMECC_CFG_BCH_ERR32 (5 << 0)
47
48#define PMECC_CFG_SECTOR512 (0 << 4)
49#define PMECC_CFG_SECTOR1024 (1 << 4)
50
51#define PMECC_CFG_PAGE_1SECTOR (0 << 8)
52#define PMECC_CFG_PAGE_2SECTORS (1 << 8)
53#define PMECC_CFG_PAGE_4SECTORS (2 << 8)
54#define PMECC_CFG_PAGE_8SECTORS (3 << 8)
55
56#define PMECC_CFG_READ_OP (0 << 12)
57#define PMECC_CFG_WRITE_OP (1 << 12)
58
59#define PMECC_CFG_SPARE_ENABLE (1 << 16)
60#define PMECC_CFG_SPARE_DISABLE (0 << 16)
61
62#define PMECC_CFG_AUTO_ENABLE (1 << 20)
63#define PMECC_CFG_AUTO_DISABLE (0 << 20)
64
65#define ATMEL_PMECC_SAREA 0x004 /* Spare area size */
66#define ATMEL_PMECC_SADDR 0x008 /* PMECC starting address */
67#define ATMEL_PMECC_EADDR 0x00c /* PMECC ending address */
68#define ATMEL_PMECC_CLK 0x010 /* PMECC clock control */
69#define PMECC_CLK_133MHZ (2 << 0)
70
71#define ATMEL_PMECC_CTRL 0x014 /* PMECC control register */
72#define PMECC_CTRL_RST (1 << 0)
73#define PMECC_CTRL_DATA (1 << 1)
74#define PMECC_CTRL_USER (1 << 2)
75#define PMECC_CTRL_ENABLE (1 << 4)
76#define PMECC_CTRL_DISABLE (1 << 5)
77
78#define ATMEL_PMECC_SR 0x018 /* PMECC status register */
79#define PMECC_SR_BUSY (1 << 0)
80#define PMECC_SR_ENABLE (1 << 4)
81
82#define ATMEL_PMECC_IER 0x01c /* PMECC interrupt enable */
83#define PMECC_IER_ENABLE (1 << 0)
84#define ATMEL_PMECC_IDR 0x020 /* PMECC interrupt disable */
85#define PMECC_IER_DISABLE (1 << 0)
86#define ATMEL_PMECC_IMR 0x024 /* PMECC interrupt mask */
87#define PMECC_IER_MASK (1 << 0)
88#define ATMEL_PMECC_ISR 0x028 /* PMECC interrupt status */
89#define ATMEL_PMECC_ECCx 0x040 /* PMECC ECC x */
90#define ATMEL_PMECC_REMx 0x240 /* PMECC REM x */
91
92/* PMERRLOC Register Definitions */
93#define ATMEL_PMERRLOC_ELCFG 0x000 /* Error location config */
94#define PMERRLOC_ELCFG_SECTOR_512 (0 << 0)
95#define PMERRLOC_ELCFG_SECTOR_1024 (1 << 0)
96#define PMERRLOC_ELCFG_NUM_ERRORS(n) ((n) << 16)
97
98#define ATMEL_PMERRLOC_ELPRIM 0x004 /* Error location primitive */
99#define ATMEL_PMERRLOC_ELEN 0x008 /* Error location enable */
100#define ATMEL_PMERRLOC_ELDIS 0x00c /* Error location disable */
101#define PMERRLOC_DISABLE (1 << 0)
102
103#define ATMEL_PMERRLOC_ELSR 0x010 /* Error location status */
104#define PMERRLOC_ELSR_BUSY (1 << 0)
105#define ATMEL_PMERRLOC_ELIER 0x014 /* Error location int enable */
106#define ATMEL_PMERRLOC_ELIDR 0x018 /* Error location int disable */
107#define ATMEL_PMERRLOC_ELIMR 0x01c /* Error location int mask */
108#define ATMEL_PMERRLOC_ELISR 0x020 /* Error location int status */
109#define PMERRLOC_ERR_NUM_MASK (0x1f << 8)
110#define PMERRLOC_CALC_DONE (1 << 0)
111#define ATMEL_PMERRLOC_SIGMAx 0x028 /* Error location SIGMA x */
112
113/*
114 * The ATMEL_PMERRLOC_ELx register location depends from the number of
115 * bits corrected by the PMECC controller. Do not use it.
116 */
117
118/* Register access macros for PMECC */
119#define pmecc_readl_relaxed(addr, reg) \
120 readl_relaxed((addr) + ATMEL_PMECC_##reg)
121
122#define pmecc_writel(addr, reg, value) \
123 writel((value), (addr) + ATMEL_PMECC_##reg)
124
125#define pmecc_readb_ecc_relaxed(addr, sector, n) \
126 readb_relaxed((addr) + ATMEL_PMECC_ECCx + ((sector) * 0x40) + (n))
127
128#define pmecc_readl_rem_relaxed(addr, sector, n) \
129 readl_relaxed((addr) + ATMEL_PMECC_REMx + ((sector) * 0x40) + ((n) * 4))
130
131#define pmerrloc_readl_relaxed(addr, reg) \
132 readl_relaxed((addr) + ATMEL_PMERRLOC_##reg)
133
134#define pmerrloc_writel(addr, reg, value) \
135 writel((value), (addr) + ATMEL_PMERRLOC_##reg)
136
137#define pmerrloc_writel_sigma_relaxed(addr, n, value) \
138 writel_relaxed((value), (addr) + ATMEL_PMERRLOC_SIGMAx + ((n) * 4))
139
140#define pmerrloc_readl_sigma_relaxed(addr, n) \
141 readl_relaxed((addr) + ATMEL_PMERRLOC_SIGMAx + ((n) * 4))
142
143#define pmerrloc_readl_el_relaxed(addr, n) \
144 readl_relaxed((addr) + ((n) * 4))
145
146/* Galois field dimension */
147#define PMECC_GF_DIMENSION_13 13
148#define PMECC_GF_DIMENSION_14 14
149
150/* Primitive Polynomial used by PMECC */
151#define PMECC_GF_13_PRIMITIVE_POLY 0x201b
152#define PMECC_GF_14_PRIMITIVE_POLY 0x4443
153
154#define PMECC_LOOKUP_TABLE_SIZE_512 0x2000
155#define PMECC_LOOKUP_TABLE_SIZE_1024 0x4000
156
157/* Time out value for reading PMECC status register */
158#define PMECC_MAX_TIMEOUT_MS 100
159
160/* Reserved bytes in oob area */
161#define PMECC_OOB_RESERVED_BYTES 2
162
163#endif