tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Macros for accessing system registers with older binutils.
3 *
4 * Copyright (C) 2014 ARM Ltd.
5 * Author: Catalin Marinas <catalin.marinas@arm.com>
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef __ASM_SYSREG_H
21#define __ASM_SYSREG_H
22
23#include <linux/stringify.h>
24
25#include <asm/opcodes.h>
26
27/*
28 * ARMv8 ARM reserves the following encoding for system registers:
29 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
30 * C5.2, version:ARM DDI 0487A.f)
31 * [20-19] : Op0
32 * [18-16] : Op1
33 * [15-12] : CRn
34 * [11-8] : CRm
35 * [7-5] : Op2
36 */
37#define sys_reg(op0, op1, crn, crm, op2) \
38 ((((op0)&3)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5))
39
40#define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
41#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
42#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
43
44#define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0)
45#define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1)
46#define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
47#define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4)
48#define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5)
49#define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6)
50#define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7)
51
52#define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0)
53#define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1)
54#define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2)
55#define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3)
56#define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4)
57#define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5)
58#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6)
59
60#define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
61#define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1)
62#define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2)
63
64#define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0)
65#define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1)
66
67#define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0)
68#define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1)
69
70#define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0)
71#define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1)
72
73#define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
74#define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
75#define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
76
77#define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
78#define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
79#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
80
81#define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4)
82#define REG_PSTATE_UAO_IMM sys_reg(0, 0, 4, 0, 3)
83
84#define SET_PSTATE_PAN(x) __inst_arm(0xd5000000 | REG_PSTATE_PAN_IMM |\
85 (!!x)<<8 | 0x1f)
86#define SET_PSTATE_UAO(x) __inst_arm(0xd5000000 | REG_PSTATE_UAO_IMM |\
87 (!!x)<<8 | 0x1f)
88
89/* Common SCTLR_ELx flags. */
90#define SCTLR_ELx_EE (1 << 25)
91#define SCTLR_ELx_I (1 << 12)
92#define SCTLR_ELx_SA (1 << 3)
93#define SCTLR_ELx_C (1 << 2)
94#define SCTLR_ELx_A (1 << 1)
95#define SCTLR_ELx_M 1
96
97#define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \
98 SCTLR_ELx_SA | SCTLR_ELx_I)
99
100/* SCTLR_EL1 specific flags. */
101#define SCTLR_EL1_UCI (1 << 26)
102#define SCTLR_EL1_SPAN (1 << 23)
103#define SCTLR_EL1_SED (1 << 8)
104#define SCTLR_EL1_CP15BEN (1 << 5)
105
106/* id_aa64isar0 */
107#define ID_AA64ISAR0_RDM_SHIFT 28
108#define ID_AA64ISAR0_ATOMICS_SHIFT 20
109#define ID_AA64ISAR0_CRC32_SHIFT 16
110#define ID_AA64ISAR0_SHA2_SHIFT 12
111#define ID_AA64ISAR0_SHA1_SHIFT 8
112#define ID_AA64ISAR0_AES_SHIFT 4
113
114/* id_aa64pfr0 */
115#define ID_AA64PFR0_GIC_SHIFT 24
116#define ID_AA64PFR0_ASIMD_SHIFT 20
117#define ID_AA64PFR0_FP_SHIFT 16
118#define ID_AA64PFR0_EL3_SHIFT 12
119#define ID_AA64PFR0_EL2_SHIFT 8
120#define ID_AA64PFR0_EL1_SHIFT 4
121#define ID_AA64PFR0_EL0_SHIFT 0
122
123#define ID_AA64PFR0_FP_NI 0xf
124#define ID_AA64PFR0_FP_SUPPORTED 0x0
125#define ID_AA64PFR0_ASIMD_NI 0xf
126#define ID_AA64PFR0_ASIMD_SUPPORTED 0x0
127#define ID_AA64PFR0_EL1_64BIT_ONLY 0x1
128#define ID_AA64PFR0_EL0_64BIT_ONLY 0x1
129#define ID_AA64PFR0_EL0_32BIT_64BIT 0x2
130
131/* id_aa64mmfr0 */
132#define ID_AA64MMFR0_TGRAN4_SHIFT 28
133#define ID_AA64MMFR0_TGRAN64_SHIFT 24
134#define ID_AA64MMFR0_TGRAN16_SHIFT 20
135#define ID_AA64MMFR0_BIGENDEL0_SHIFT 16
136#define ID_AA64MMFR0_SNSMEM_SHIFT 12
137#define ID_AA64MMFR0_BIGENDEL_SHIFT 8
138#define ID_AA64MMFR0_ASID_SHIFT 4
139#define ID_AA64MMFR0_PARANGE_SHIFT 0
140
141#define ID_AA64MMFR0_TGRAN4_NI 0xf
142#define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
143#define ID_AA64MMFR0_TGRAN64_NI 0xf
144#define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
145#define ID_AA64MMFR0_TGRAN16_NI 0x0
146#define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
147
148/* id_aa64mmfr1 */
149#define ID_AA64MMFR1_PAN_SHIFT 20
150#define ID_AA64MMFR1_LOR_SHIFT 16
151#define ID_AA64MMFR1_HPD_SHIFT 12
152#define ID_AA64MMFR1_VHE_SHIFT 8
153#define ID_AA64MMFR1_VMIDBITS_SHIFT 4
154#define ID_AA64MMFR1_HADBS_SHIFT 0
155
156#define ID_AA64MMFR1_VMIDBITS_8 0
157#define ID_AA64MMFR1_VMIDBITS_16 2
158
159/* id_aa64mmfr2 */
160#define ID_AA64MMFR2_LVA_SHIFT 16
161#define ID_AA64MMFR2_IESB_SHIFT 12
162#define ID_AA64MMFR2_LSM_SHIFT 8
163#define ID_AA64MMFR2_UAO_SHIFT 4
164#define ID_AA64MMFR2_CNP_SHIFT 0
165
166/* id_aa64dfr0 */
167#define ID_AA64DFR0_CTX_CMPS_SHIFT 28
168#define ID_AA64DFR0_WRPS_SHIFT 20
169#define ID_AA64DFR0_BRPS_SHIFT 12
170#define ID_AA64DFR0_PMUVER_SHIFT 8
171#define ID_AA64DFR0_TRACEVER_SHIFT 4
172#define ID_AA64DFR0_DEBUGVER_SHIFT 0
173
174#define ID_ISAR5_RDM_SHIFT 24
175#define ID_ISAR5_CRC32_SHIFT 16
176#define ID_ISAR5_SHA2_SHIFT 12
177#define ID_ISAR5_SHA1_SHIFT 8
178#define ID_ISAR5_AES_SHIFT 4
179#define ID_ISAR5_SEVL_SHIFT 0
180
181#define MVFR0_FPROUND_SHIFT 28
182#define MVFR0_FPSHVEC_SHIFT 24
183#define MVFR0_FPSQRT_SHIFT 20
184#define MVFR0_FPDIVIDE_SHIFT 16
185#define MVFR0_FPTRAP_SHIFT 12
186#define MVFR0_FPDP_SHIFT 8
187#define MVFR0_FPSP_SHIFT 4
188#define MVFR0_SIMD_SHIFT 0
189
190#define MVFR1_SIMDFMAC_SHIFT 28
191#define MVFR1_FPHP_SHIFT 24
192#define MVFR1_SIMDHP_SHIFT 20
193#define MVFR1_SIMDSP_SHIFT 16
194#define MVFR1_SIMDINT_SHIFT 12
195#define MVFR1_SIMDLS_SHIFT 8
196#define MVFR1_FPDNAN_SHIFT 4
197#define MVFR1_FPFTZ_SHIFT 0
198
199
200#define ID_AA64MMFR0_TGRAN4_SHIFT 28
201#define ID_AA64MMFR0_TGRAN64_SHIFT 24
202#define ID_AA64MMFR0_TGRAN16_SHIFT 20
203
204#define ID_AA64MMFR0_TGRAN4_NI 0xf
205#define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
206#define ID_AA64MMFR0_TGRAN64_NI 0xf
207#define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
208#define ID_AA64MMFR0_TGRAN16_NI 0x0
209#define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
210
211#if defined(CONFIG_ARM64_4K_PAGES)
212#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT
213#define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED
214#elif defined(CONFIG_ARM64_16K_PAGES)
215#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT
216#define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED
217#elif defined(CONFIG_ARM64_64K_PAGES)
218#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT
219#define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED
220#endif
221
222#ifdef __ASSEMBLY__
223
224 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
225 .equ .L__reg_num_x\num, \num
226 .endr
227 .equ .L__reg_num_xzr, 31
228
229 .macro mrs_s, rt, sreg
230 .inst 0xd5200000|(\sreg)|(.L__reg_num_\rt)
231 .endm
232
233 .macro msr_s, sreg, rt
234 .inst 0xd5000000|(\sreg)|(.L__reg_num_\rt)
235 .endm
236
237#else
238
239#include <linux/types.h>
240
241asm(
242" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
243" .equ .L__reg_num_x\\num, \\num\n"
244" .endr\n"
245" .equ .L__reg_num_xzr, 31\n"
246"\n"
247" .macro mrs_s, rt, sreg\n"
248" .inst 0xd5200000|(\\sreg)|(.L__reg_num_\\rt)\n"
249" .endm\n"
250"\n"
251" .macro msr_s, sreg, rt\n"
252" .inst 0xd5000000|(\\sreg)|(.L__reg_num_\\rt)\n"
253" .endm\n"
254);
255
256static inline void config_sctlr_el1(u32 clear, u32 set)
257{
258 u32 val;
259
260 asm volatile("mrs %0, sctlr_el1" : "=r" (val));
261 val &= ~clear;
262 val |= set;
263 asm volatile("msr sctlr_el1, %0" : : "r" (val));
264}
265
266/*
267 * Unlike read_cpuid, calls to read_sysreg are never expected to be
268 * optimized away or replaced with synthetic values.
269 */
270#define read_sysreg(r) ({ \
271 u64 __val; \
272 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
273 __val; \
274})
275
276#define write_sysreg(v, r) do { \
277 u64 __val = (u64)v; \
278 asm volatile("msr " __stringify(r) ", %0" \
279 : : "r" (__val)); \
280} while (0)
281
282#endif
283
284#endif /* __ASM_SYSREG_H */