tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*
2 * Device Tree file for Marvell Armada 385 Access Point Development board
3 * (DB-88F6820-AP)
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Nadav Haklai <nadavh@marvell.com>
8 *
9 * This file is dual-licensed: you can use it either under the terms
10 * of the GPL or the X11 license, at your option. Note that this dual
11 * licensing only applies to this file, and not this project as a
12 * whole.
13 *
14 * a) This file is licensed under the terms of the GNU General Public
15 * License version 2. This program is licensed "as is" without
16 * any warranty of any kind, whether express or implied.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42/dts-v1/;
43#include "armada-385.dtsi"
44
45#include <dt-bindings/gpio/gpio.h>
46
47/ {
48 model = "Marvell Armada 385 Access Point Development Board";
49 compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada380";
50
51 chosen {
52 stdout-path = "serial1:115200n8";
53 };
54
55 memory {
56 device_type = "memory";
57 reg = <0x00000000 0x80000000>; /* 2GB */
58 };
59
60 soc {
61 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
62 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
63 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
64 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
65 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
66
67 internal-regs {
68 spi1: spi@10680 {
69 pinctrl-names = "default";
70 pinctrl-0 = <&spi1_pins>;
71 status = "okay";
72
73 spi-flash@0 {
74 #address-cells = <1>;
75 #size-cells = <1>;
76 compatible = "st,m25p128", "jedec,spi-nor";
77 reg = <0>; /* Chip select 0 */
78 spi-max-frequency = <54000000>;
79 };
80 };
81
82 i2c0: i2c@11000 {
83 pinctrl-names = "default";
84 pinctrl-0 = <&i2c0_pins>;
85 status = "okay";
86
87 /*
88 * This bus is wired to two EEPROM
89 * sockets, one of which holding the
90 * board ID used by the bootloader.
91 * Erasing this EEPROM's content will
92 * brick the board.
93 * Use this bus with caution.
94 */
95 };
96
97 mdio@72004 {
98 pinctrl-names = "default";
99 pinctrl-0 = <&mdio_pins>;
100
101 phy0: ethernet-phy@1 {
102 reg = <1>;
103 };
104
105 phy1: ethernet-phy@4 {
106 reg = <4>;
107 };
108
109 phy2: ethernet-phy@6 {
110 reg = <6>;
111 };
112 };
113
114 /* UART0 is exposed through the JP8 connector */
115 uart0: serial@12000 {
116 pinctrl-names = "default";
117 pinctrl-0 = <&uart0_pins>;
118 status = "okay";
119 };
120
121 /*
122 * UART1 is exposed through a FTDI chip
123 * wired to the mini-USB connector
124 */
125 uart1: serial@12100 {
126 pinctrl-names = "default";
127 pinctrl-0 = <&uart1_pins>;
128 status = "okay";
129 };
130
131 pinctrl@18000 {
132 xhci0_vbus_pins: xhci0-vbus-pins {
133 marvell,pins = "mpp44";
134 marvell,function = "gpio";
135 };
136 };
137
138 /* CON3 */
139 ethernet@30000 {
140 status = "okay";
141 phy = <&phy2>;
142 phy-mode = "sgmii";
143 buffer-manager = <&bm>;
144 bm,pool-long = <1>;
145 bm,pool-short = <3>;
146 };
147
148 /* CON2 */
149 ethernet@34000 {
150 status = "okay";
151 phy = <&phy1>;
152 phy-mode = "sgmii";
153 buffer-manager = <&bm>;
154 bm,pool-long = <2>;
155 bm,pool-short = <3>;
156 };
157
158 /* CON4 */
159 ethernet@70000 {
160 pinctrl-names = "default";
161
162 /*
163 * The Reference Clock 0 is used to
164 * provide a clock to the PHY
165 */
166 pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
167 status = "okay";
168 phy = <&phy0>;
169 phy-mode = "rgmii-id";
170 buffer-manager = <&bm>;
171 bm,pool-long = <0>;
172 bm,pool-short = <3>;
173 };
174
175 bm@c8000 {
176 status = "okay";
177 };
178
179 nfc: flash@d0000 {
180 status = "okay";
181 #address-cells = <1>;
182 #size-cells = <1>;
183
184 num-cs = <1>;
185 nand-ecc-strength = <4>;
186 nand-ecc-step-size = <512>;
187 marvell,nand-keep-config;
188 marvell,nand-enable-arbiter;
189 nand-on-flash-bbt;
190 };
191
192 usb3@f0000 {
193 status = "okay";
194 usb-phy = <&usb3_phy>;
195 };
196 };
197
198 bm-bppi {
199 status = "okay";
200 };
201
202 pcie-controller {
203 status = "okay";
204
205 /*
206 * The three PCIe units are accessible through
207 * standard mini-PCIe slots on the board.
208 */
209 pcie@1,0 {
210 /* Port 0, Lane 0 */
211 status = "okay";
212 };
213
214 pcie@2,0 {
215 /* Port 1, Lane 0 */
216 status = "okay";
217 };
218
219 pcie@3,0 {
220 /* Port 2, Lane 0 */
221 status = "okay";
222 };
223 };
224 };
225
226 usb3_phy: usb3_phy {
227 compatible = "usb-nop-xceiv";
228 vcc-supply = <®_xhci0_vbus>;
229 };
230
231 reg_xhci0_vbus: xhci0-vbus {
232 compatible = "regulator-fixed";
233 pinctrl-names = "default";
234 pinctrl-0 = <&xhci0_vbus_pins>;
235 regulator-name = "xhci0-vbus";
236 regulator-min-microvolt = <5000000>;
237 regulator-max-microvolt = <5000000>;
238 enable-active-high;
239 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
240 };
241};