tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1* Mediatek MT65XX Pin Controller
2
3The Mediatek's Pin controller is used to control SoC pins.
4
5Required properties:
6- compatible: value should be one of the following.
7 "mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl.
8 "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
9 "mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl.
10 "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
11 "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
12 "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
13- pins-are-numbered: Specify the subnodes are using numbered pinmux to
14 specify pins.
15- gpio-controller : Marks the device node as a gpio controller.
16- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
17 binding is used, the amount of cells must be specified as 2. See the below
18 mentioned gpio binding representation for description of particular cells.
19
20 Eg: <&pio 6 0>
21 <[phandle of the gpio controller node]
22 [line number within the gpio controller]
23 [flags]>
24
25 Values for gpio specifier:
26 - Line number: is a value between 0 to 202.
27 - Flags: bit field of flags, as defined in <dt-bindings/gpio/gpio.h>.
28 Only the following flags are supported:
29 0 - GPIO_ACTIVE_HIGH
30 1 - GPIO_ACTIVE_LOW
31
32Optional properties:
33- mediatek,pctl-regmap: Should be a phandle of the syscfg node.
34- reg: physicall address base for EINT registers
35- interrupt-controller: Marks the device node as an interrupt controller
36- #interrupt-cells: Should be two.
37- interrupts : The interrupt outputs from the controller.
38
39Please refer to pinctrl-bindings.txt in this directory for details of the
40common pinctrl bindings used by client devices.
41
42Subnode format
43A pinctrl node should contain at least one subnodes representing the
44pinctrl groups available on the machine. Each subnode will list the
45pins it needs, and how they should be configured, with regard to muxer
46configuration, pullups, drive strength, input enable/disable and input schmitt.
47
48 node {
49 pinmux = <PIN_NUMBER_PINMUX>;
50 GENERIC_PINCONFIG;
51 };
52
53Required properties:
54- pinmux: integer array, represents gpio pin number and mux setting.
55 Supported pin number and mux varies for different SoCs, and are defined
56 as macros in boot/dts/<soc>-pinfunc.h directly.
57
58Optional properties:
59- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable,
60 bias-pull-down, bias-pull-up, input-enable, input-disable, output-low, output-high,
61 input-schmitt-enable, input-schmitt-disable and drive-strength are valid.
62
63 Some special pins have extra pull up strength, there are R0 and R1 pull-up
64 resistors available, but for user, it's only need to set R1R0 as 00, 01, 10 or 11.
65 So when config bias-pull-up, it support arguments for those special pins.
66 Some macros have been defined for this usage, such as MTK_PUPD_SET_R1R0_00.
67 See dt-bindings/pinctrl/mt65xx.h.
68
69 When config drive-strength, it can support some arguments, such as
70 MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h.
71
72Examples:
73
74#include "mt8135-pinfunc.h"
75
76...
77{
78 syscfg_pctl_a: syscfg_pctl_a@10005000 {
79 compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
80 reg = <0 0x10005000 0 0x1000>;
81 };
82
83 syscfg_pctl_b: syscfg_pctl_b@1020C020 {
84 compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
85 reg = <0 0x1020C020 0 0x1000>;
86 };
87
88 pinctrl@01c20800 {
89 compatible = "mediatek,mt8135-pinctrl";
90 reg = <0 0x1000B000 0 0x1000>;
91 mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
92 pins-are-numbered;
93 gpio-controller;
94 #gpio-cells = <2>;
95 interrupt-controller;
96 #interrupt-cells = <2>;
97 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
98 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
100
101 i2c0_pins_a: i2c0@0 {
102 pins1 {
103 pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
104 <MT8135_PIN_101_SCL0__FUNC_SCL0>;
105 bias-disable;
106 };
107 };
108
109 i2c1_pins_a: i2c1@0 {
110 pins {
111 pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
112 <MT8135_PIN_196_SCL1__FUNC_SCL1>;
113 bias-pull-up = <55>;
114 };
115 };
116
117 i2c2_pins_a: i2c2@0 {
118 pins1 {
119 pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
120 bias-pull-down;
121 };
122
123 pins2 {
124 pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
125 bias-pull-up;
126 };
127 };
128
129 i2c3_pins_a: i2c3@0 {
130 pins1 {
131 pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
132 <MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;
133 bias-pull-up = <55>;
134 };
135
136 pins2 {
137 pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>,
138 <MT8135_PIN_36_SDA3__FUNC_SDA3>;
139 output-low;
140 bias-pull-up = <55>;
141 };
142
143 pins3 {
144 pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,
145 <MT8135_PIN_60_JTDI__FUNC_JTDI>;
146 drive-strength = <32>;
147 };
148 };
149
150 ...
151 }
152};