tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/*
2 * TI Palmas
3 *
4 * Copyright 2011-2013 Texas Instruments Inc.
5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 * Author: Ian Lartey <ian@slimlogic.co.uk>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#ifndef __LINUX_MFD_PALMAS_H
17#define __LINUX_MFD_PALMAS_H
18
19#include <linux/usb/otg.h>
20#include <linux/leds.h>
21#include <linux/regmap.h>
22#include <linux/regulator/driver.h>
23#include <linux/extcon.h>
24#include <linux/of_gpio.h>
25#include <linux/usb/phy_companion.h>
26
27#define PALMAS_NUM_CLIENTS 3
28
29/* The ID_REVISION NUMBERS */
30#define PALMAS_CHIP_OLD_ID 0x0000
31#define PALMAS_CHIP_ID 0xC035
32#define PALMAS_CHIP_CHARGER_ID 0xC036
33
34#define TPS65917_RESERVED -1
35
36#define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \
37 ((a) == PALMAS_CHIP_ID))
38#define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID)
39
40/**
41 * Palmas PMIC feature types
42 *
43 * PALMAS_PMIC_FEATURE_SMPS10_BOOST - used when the PMIC provides SMPS10_BOOST
44 * regulator.
45 *
46 * PALMAS_PMIC_HAS(b, f) - macro to check if a bandgap device is capable of a
47 * specific feature (above) or not. Return non-zero, if yes.
48 */
49#define PALMAS_PMIC_FEATURE_SMPS10_BOOST BIT(0)
50#define PALMAS_PMIC_HAS(b, f) \
51 ((b)->features & PALMAS_PMIC_FEATURE_ ## f)
52
53struct palmas_pmic;
54struct palmas_gpadc;
55struct palmas_resource;
56struct palmas_usb;
57struct palmas_pmic_driver_data;
58struct palmas_pmic_platform_data;
59
60enum palmas_usb_state {
61 PALMAS_USB_STATE_DISCONNECT,
62 PALMAS_USB_STATE_VBUS,
63 PALMAS_USB_STATE_ID,
64};
65
66struct palmas {
67 struct device *dev;
68
69 struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS];
70 struct regmap *regmap[PALMAS_NUM_CLIENTS];
71
72 /* Stored chip id */
73 int id;
74
75 unsigned int features;
76 /* IRQ Data */
77 int irq;
78 u32 irq_mask;
79 struct mutex irq_lock;
80 struct regmap_irq_chip_data *irq_data;
81
82 struct palmas_pmic_driver_data *pmic_ddata;
83
84 /* Child Devices */
85 struct palmas_pmic *pmic;
86 struct palmas_gpadc *gpadc;
87 struct palmas_resource *resource;
88 struct palmas_usb *usb;
89
90 /* GPIO MUXing */
91 u8 gpio_muxed;
92 u8 led_muxed;
93 u8 pwm_muxed;
94};
95
96#define PALMAS_EXT_REQ (PALMAS_EXT_CONTROL_ENABLE1 | \
97 PALMAS_EXT_CONTROL_ENABLE2 | \
98 PALMAS_EXT_CONTROL_NSLEEP)
99
100struct palmas_sleep_requestor_info {
101 int id;
102 int reg_offset;
103 int bit_pos;
104};
105
106struct palmas_regs_info {
107 char *name;
108 char *sname;
109 u8 vsel_addr;
110 u8 ctrl_addr;
111 u8 tstep_addr;
112 int sleep_id;
113};
114
115struct palmas_pmic_driver_data {
116 int smps_start;
117 int smps_end;
118 int ldo_begin;
119 int ldo_end;
120 int max_reg;
121 bool has_regen3;
122 struct palmas_regs_info *palmas_regs_info;
123 struct of_regulator_match *palmas_matches;
124 struct palmas_sleep_requestor_info *sleep_req_info;
125 int (*smps_register)(struct palmas_pmic *pmic,
126 struct palmas_pmic_driver_data *ddata,
127 struct palmas_pmic_platform_data *pdata,
128 const char *pdev_name,
129 struct regulator_config config);
130 int (*ldo_register)(struct palmas_pmic *pmic,
131 struct palmas_pmic_driver_data *ddata,
132 struct palmas_pmic_platform_data *pdata,
133 const char *pdev_name,
134 struct regulator_config config);
135};
136
137struct palmas_adc_wakeup_property {
138 int adc_channel_number;
139 int adc_high_threshold;
140 int adc_low_threshold;
141};
142
143struct palmas_gpadc_platform_data {
144 /* Channel 3 current source is only enabled during conversion */
145 int ch3_current; /* 0: off; 1: 10uA; 2: 400uA; 3: 800 uA */
146
147 /* Channel 0 current source can be used for battery detection.
148 * If used for battery detection this will cause a permanent current
149 * consumption depending on current level set here.
150 */
151 int ch0_current; /* 0: off; 1: 5uA; 2: 15uA; 3: 20 uA */
152 bool extended_delay; /* use extended delay for conversion */
153
154 /* default BAT_REMOVAL_DAT setting on device probe */
155 int bat_removal;
156
157 /* Sets the START_POLARITY bit in the RT_CTRL register */
158 int start_polarity;
159
160 int auto_conversion_period_ms;
161 struct palmas_adc_wakeup_property *adc_wakeup1_data;
162 struct palmas_adc_wakeup_property *adc_wakeup2_data;
163};
164
165struct palmas_reg_init {
166 /* warm_rest controls the voltage levels after a warm reset
167 *
168 * 0: reload default values from OTP on warm reset
169 * 1: maintain voltage from VSEL on warm reset
170 */
171 int warm_reset;
172
173 /* roof_floor controls whether the regulator uses the i2c style
174 * of DVS or uses the method where a GPIO or other control method is
175 * attached to the NSLEEP/ENABLE1/ENABLE2 pins
176 *
177 * For SMPS
178 *
179 * 0: i2c selection of voltage
180 * 1: pin selection of voltage.
181 *
182 * For LDO unused
183 */
184 int roof_floor;
185
186 /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
187 * the data sheet.
188 *
189 * For SMPS
190 *
191 * 0: Off
192 * 1: AUTO
193 * 2: ECO
194 * 3: Forced PWM
195 *
196 * For LDO
197 *
198 * 0: Off
199 * 1: On
200 */
201 int mode_sleep;
202
203 /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
204 * register. Set this is the default voltage set in OTP needs
205 * to be overridden.
206 */
207 u8 vsel;
208
209};
210
211enum palmas_regulators {
212 /* SMPS regulators */
213 PALMAS_REG_SMPS12,
214 PALMAS_REG_SMPS123,
215 PALMAS_REG_SMPS3,
216 PALMAS_REG_SMPS45,
217 PALMAS_REG_SMPS457,
218 PALMAS_REG_SMPS6,
219 PALMAS_REG_SMPS7,
220 PALMAS_REG_SMPS8,
221 PALMAS_REG_SMPS9,
222 PALMAS_REG_SMPS10_OUT2,
223 PALMAS_REG_SMPS10_OUT1,
224 /* LDO regulators */
225 PALMAS_REG_LDO1,
226 PALMAS_REG_LDO2,
227 PALMAS_REG_LDO3,
228 PALMAS_REG_LDO4,
229 PALMAS_REG_LDO5,
230 PALMAS_REG_LDO6,
231 PALMAS_REG_LDO7,
232 PALMAS_REG_LDO8,
233 PALMAS_REG_LDO9,
234 PALMAS_REG_LDOLN,
235 PALMAS_REG_LDOUSB,
236 /* External regulators */
237 PALMAS_REG_REGEN1,
238 PALMAS_REG_REGEN2,
239 PALMAS_REG_REGEN3,
240 PALMAS_REG_SYSEN1,
241 PALMAS_REG_SYSEN2,
242 /* Total number of regulators */
243 PALMAS_NUM_REGS,
244};
245
246enum tps65917_regulators {
247 /* SMPS regulators */
248 TPS65917_REG_SMPS1,
249 TPS65917_REG_SMPS2,
250 TPS65917_REG_SMPS3,
251 TPS65917_REG_SMPS4,
252 TPS65917_REG_SMPS5,
253 /* LDO regulators */
254 TPS65917_REG_LDO1,
255 TPS65917_REG_LDO2,
256 TPS65917_REG_LDO3,
257 TPS65917_REG_LDO4,
258 TPS65917_REG_LDO5,
259 TPS65917_REG_REGEN1,
260 TPS65917_REG_REGEN2,
261 TPS65917_REG_REGEN3,
262
263 /* Total number of regulators */
264 TPS65917_NUM_REGS,
265};
266
267/* External controll signal name */
268enum {
269 PALMAS_EXT_CONTROL_ENABLE1 = 0x1,
270 PALMAS_EXT_CONTROL_ENABLE2 = 0x2,
271 PALMAS_EXT_CONTROL_NSLEEP = 0x4,
272};
273
274/*
275 * Palmas device resources can be controlled externally for
276 * enabling/disabling it rather than register write through i2c.
277 * Add the external controlled requestor ID for different resources.
278 */
279enum palmas_external_requestor_id {
280 PALMAS_EXTERNAL_REQSTR_ID_REGEN1,
281 PALMAS_EXTERNAL_REQSTR_ID_REGEN2,
282 PALMAS_EXTERNAL_REQSTR_ID_SYSEN1,
283 PALMAS_EXTERNAL_REQSTR_ID_SYSEN2,
284 PALMAS_EXTERNAL_REQSTR_ID_CLK32KG,
285 PALMAS_EXTERNAL_REQSTR_ID_CLK32KGAUDIO,
286 PALMAS_EXTERNAL_REQSTR_ID_REGEN3,
287 PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
288 PALMAS_EXTERNAL_REQSTR_ID_SMPS3,
289 PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
290 PALMAS_EXTERNAL_REQSTR_ID_SMPS6,
291 PALMAS_EXTERNAL_REQSTR_ID_SMPS7,
292 PALMAS_EXTERNAL_REQSTR_ID_SMPS8,
293 PALMAS_EXTERNAL_REQSTR_ID_SMPS9,
294 PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
295 PALMAS_EXTERNAL_REQSTR_ID_LDO1,
296 PALMAS_EXTERNAL_REQSTR_ID_LDO2,
297 PALMAS_EXTERNAL_REQSTR_ID_LDO3,
298 PALMAS_EXTERNAL_REQSTR_ID_LDO4,
299 PALMAS_EXTERNAL_REQSTR_ID_LDO5,
300 PALMAS_EXTERNAL_REQSTR_ID_LDO6,
301 PALMAS_EXTERNAL_REQSTR_ID_LDO7,
302 PALMAS_EXTERNAL_REQSTR_ID_LDO8,
303 PALMAS_EXTERNAL_REQSTR_ID_LDO9,
304 PALMAS_EXTERNAL_REQSTR_ID_LDOLN,
305 PALMAS_EXTERNAL_REQSTR_ID_LDOUSB,
306
307 /* Last entry */
308 PALMAS_EXTERNAL_REQSTR_ID_MAX,
309};
310
311enum tps65917_external_requestor_id {
312 TPS65917_EXTERNAL_REQSTR_ID_REGEN1,
313 TPS65917_EXTERNAL_REQSTR_ID_REGEN2,
314 TPS65917_EXTERNAL_REQSTR_ID_REGEN3,
315 TPS65917_EXTERNAL_REQSTR_ID_SMPS1,
316 TPS65917_EXTERNAL_REQSTR_ID_SMPS2,
317 TPS65917_EXTERNAL_REQSTR_ID_SMPS3,
318 TPS65917_EXTERNAL_REQSTR_ID_SMPS4,
319 TPS65917_EXTERNAL_REQSTR_ID_SMPS5,
320 TPS65917_EXTERNAL_REQSTR_ID_LDO1,
321 TPS65917_EXTERNAL_REQSTR_ID_LDO2,
322 TPS65917_EXTERNAL_REQSTR_ID_LDO3,
323 TPS65917_EXTERNAL_REQSTR_ID_LDO4,
324 TPS65917_EXTERNAL_REQSTR_ID_LDO5,
325 /* Last entry */
326 TPS65917_EXTERNAL_REQSTR_ID_MAX,
327};
328
329struct palmas_pmic_platform_data {
330 /* An array of pointers to regulator init data indexed by regulator
331 * ID
332 */
333 struct regulator_init_data *reg_data[PALMAS_NUM_REGS];
334
335 /* An array of pointers to structures containing sleep mode and DVS
336 * configuration for regulators indexed by ID
337 */
338 struct palmas_reg_init *reg_init[PALMAS_NUM_REGS];
339
340 /* use LDO6 for vibrator control */
341 int ldo6_vibrator;
342
343 /* Enable tracking mode of LDO8 */
344 bool enable_ldo8_tracking;
345};
346
347struct palmas_usb_platform_data {
348 /* Do we enable the wakeup comparator on probe */
349 int wakeup;
350};
351
352struct palmas_resource_platform_data {
353 int regen1_mode_sleep;
354 int regen2_mode_sleep;
355 int sysen1_mode_sleep;
356 int sysen2_mode_sleep;
357
358 /* bitfield to be loaded to NSLEEP_RES_ASSIGN */
359 u8 nsleep_res;
360 /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */
361 u8 nsleep_smps;
362 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */
363 u8 nsleep_ldo1;
364 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */
365 u8 nsleep_ldo2;
366
367 /* bitfield to be loaded to ENABLE1_RES_ASSIGN */
368 u8 enable1_res;
369 /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */
370 u8 enable1_smps;
371 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */
372 u8 enable1_ldo1;
373 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */
374 u8 enable1_ldo2;
375
376 /* bitfield to be loaded to ENABLE2_RES_ASSIGN */
377 u8 enable2_res;
378 /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */
379 u8 enable2_smps;
380 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */
381 u8 enable2_ldo1;
382 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */
383 u8 enable2_ldo2;
384};
385
386struct palmas_clk_platform_data {
387 int clk32kg_mode_sleep;
388 int clk32kgaudio_mode_sleep;
389};
390
391struct palmas_platform_data {
392 int irq_flags;
393 int gpio_base;
394
395 /* bit value to be loaded to the POWER_CTRL register */
396 u8 power_ctrl;
397
398 /*
399 * boolean to select if we want to configure muxing here
400 * then the two value to load into the registers if true
401 */
402 int mux_from_pdata;
403 u8 pad1, pad2;
404 bool pm_off;
405
406 struct palmas_pmic_platform_data *pmic_pdata;
407 struct palmas_gpadc_platform_data *gpadc_pdata;
408 struct palmas_usb_platform_data *usb_pdata;
409 struct palmas_resource_platform_data *resource_pdata;
410 struct palmas_clk_platform_data *clk_pdata;
411};
412
413struct palmas_gpadc_calibration {
414 s32 gain;
415 s32 gain_error;
416 s32 offset_error;
417};
418
419#define PALMAS_DATASHEET_NAME(_name) "palmas-gpadc-chan-"#_name
420
421struct palmas_gpadc_result {
422 s32 raw_code;
423 s32 corrected_code;
424 s32 result;
425};
426
427#define PALMAS_MAX_CHANNELS 16
428
429/* Define the tps65917 IRQ numbers */
430enum tps65917_irqs {
431 /* INT1 registers */
432 TPS65917_RESERVED1,
433 TPS65917_PWRON_IRQ,
434 TPS65917_LONG_PRESS_KEY_IRQ,
435 TPS65917_RESERVED2,
436 TPS65917_PWRDOWN_IRQ,
437 TPS65917_HOTDIE_IRQ,
438 TPS65917_VSYS_MON_IRQ,
439 TPS65917_RESERVED3,
440 /* INT2 registers */
441 TPS65917_RESERVED4,
442 TPS65917_OTP_ERROR_IRQ,
443 TPS65917_WDT_IRQ,
444 TPS65917_RESERVED5,
445 TPS65917_RESET_IN_IRQ,
446 TPS65917_FSD_IRQ,
447 TPS65917_SHORT_IRQ,
448 TPS65917_RESERVED6,
449 /* INT3 registers */
450 TPS65917_GPADC_AUTO_0_IRQ,
451 TPS65917_GPADC_AUTO_1_IRQ,
452 TPS65917_GPADC_EOC_SW_IRQ,
453 TPS65917_RESREVED6,
454 TPS65917_RESERVED7,
455 TPS65917_RESERVED8,
456 TPS65917_RESERVED9,
457 TPS65917_VBUS_IRQ,
458 /* INT4 registers */
459 TPS65917_GPIO_0_IRQ,
460 TPS65917_GPIO_1_IRQ,
461 TPS65917_GPIO_2_IRQ,
462 TPS65917_GPIO_3_IRQ,
463 TPS65917_GPIO_4_IRQ,
464 TPS65917_GPIO_5_IRQ,
465 TPS65917_GPIO_6_IRQ,
466 TPS65917_RESERVED10,
467 /* Total Number IRQs */
468 TPS65917_NUM_IRQ,
469};
470
471/* Define the palmas IRQ numbers */
472enum palmas_irqs {
473 /* INT1 registers */
474 PALMAS_CHARG_DET_N_VBUS_OVV_IRQ,
475 PALMAS_PWRON_IRQ,
476 PALMAS_LONG_PRESS_KEY_IRQ,
477 PALMAS_RPWRON_IRQ,
478 PALMAS_PWRDOWN_IRQ,
479 PALMAS_HOTDIE_IRQ,
480 PALMAS_VSYS_MON_IRQ,
481 PALMAS_VBAT_MON_IRQ,
482 /* INT2 registers */
483 PALMAS_RTC_ALARM_IRQ,
484 PALMAS_RTC_TIMER_IRQ,
485 PALMAS_WDT_IRQ,
486 PALMAS_BATREMOVAL_IRQ,
487 PALMAS_RESET_IN_IRQ,
488 PALMAS_FBI_BB_IRQ,
489 PALMAS_SHORT_IRQ,
490 PALMAS_VAC_ACOK_IRQ,
491 /* INT3 registers */
492 PALMAS_GPADC_AUTO_0_IRQ,
493 PALMAS_GPADC_AUTO_1_IRQ,
494 PALMAS_GPADC_EOC_SW_IRQ,
495 PALMAS_GPADC_EOC_RT_IRQ,
496 PALMAS_ID_OTG_IRQ,
497 PALMAS_ID_IRQ,
498 PALMAS_VBUS_OTG_IRQ,
499 PALMAS_VBUS_IRQ,
500 /* INT4 registers */
501 PALMAS_GPIO_0_IRQ,
502 PALMAS_GPIO_1_IRQ,
503 PALMAS_GPIO_2_IRQ,
504 PALMAS_GPIO_3_IRQ,
505 PALMAS_GPIO_4_IRQ,
506 PALMAS_GPIO_5_IRQ,
507 PALMAS_GPIO_6_IRQ,
508 PALMAS_GPIO_7_IRQ,
509 /* Total Number IRQs */
510 PALMAS_NUM_IRQ,
511};
512
513/* Palmas GPADC Channels */
514enum {
515 PALMAS_ADC_CH_IN0,
516 PALMAS_ADC_CH_IN1,
517 PALMAS_ADC_CH_IN2,
518 PALMAS_ADC_CH_IN3,
519 PALMAS_ADC_CH_IN4,
520 PALMAS_ADC_CH_IN5,
521 PALMAS_ADC_CH_IN6,
522 PALMAS_ADC_CH_IN7,
523 PALMAS_ADC_CH_IN8,
524 PALMAS_ADC_CH_IN9,
525 PALMAS_ADC_CH_IN10,
526 PALMAS_ADC_CH_IN11,
527 PALMAS_ADC_CH_IN12,
528 PALMAS_ADC_CH_IN13,
529 PALMAS_ADC_CH_IN14,
530 PALMAS_ADC_CH_IN15,
531 PALMAS_ADC_CH_MAX,
532};
533
534/* Palmas GPADC Channel0 Current Source */
535enum {
536 PALMAS_ADC_CH0_CURRENT_SRC_0,
537 PALMAS_ADC_CH0_CURRENT_SRC_5,
538 PALMAS_ADC_CH0_CURRENT_SRC_15,
539 PALMAS_ADC_CH0_CURRENT_SRC_20,
540};
541
542/* Palmas GPADC Channel3 Current Source */
543enum {
544 PALMAS_ADC_CH3_CURRENT_SRC_0,
545 PALMAS_ADC_CH3_CURRENT_SRC_10,
546 PALMAS_ADC_CH3_CURRENT_SRC_400,
547 PALMAS_ADC_CH3_CURRENT_SRC_800,
548};
549
550struct palmas_pmic {
551 struct palmas *palmas;
552 struct device *dev;
553 struct regulator_desc desc[PALMAS_NUM_REGS];
554 struct regulator_dev *rdev[PALMAS_NUM_REGS];
555 struct mutex mutex;
556
557 int smps123;
558 int smps457;
559 int smps12;
560
561 int range[PALMAS_REG_SMPS10_OUT1];
562 unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1];
563 unsigned int current_reg_mode[PALMAS_REG_SMPS10_OUT1];
564};
565
566struct palmas_resource {
567 struct palmas *palmas;
568 struct device *dev;
569};
570
571struct palmas_usb {
572 struct palmas *palmas;
573 struct device *dev;
574
575 struct extcon_dev *edev;
576
577 int id_otg_irq;
578 int id_irq;
579 int vbus_otg_irq;
580 int vbus_irq;
581
582 int gpio_id_irq;
583 int gpio_vbus_irq;
584 struct gpio_desc *id_gpiod;
585 struct gpio_desc *vbus_gpiod;
586 unsigned long sw_debounce_jiffies;
587 struct delayed_work wq_detectid;
588
589 enum palmas_usb_state linkstat;
590 int wakeup;
591 bool enable_vbus_detection;
592 bool enable_id_detection;
593 bool enable_gpio_id_detection;
594 bool enable_gpio_vbus_detection;
595};
596
597#define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator)
598
599enum usb_irq_events {
600 /* Wakeup events from INT3 */
601 PALMAS_USB_ID_WAKEPUP,
602 PALMAS_USB_VBUS_WAKEUP,
603
604 /* ID_OTG_EVENTS */
605 PALMAS_USB_ID_GND,
606 N_PALMAS_USB_ID_GND,
607 PALMAS_USB_ID_C,
608 N_PALMAS_USB_ID_C,
609 PALMAS_USB_ID_B,
610 N_PALMAS_USB_ID_B,
611 PALMAS_USB_ID_A,
612 N_PALMAS_USB_ID_A,
613 PALMAS_USB_ID_FLOAT,
614 N_PALMAS_USB_ID_FLOAT,
615
616 /* VBUS_OTG_EVENTS */
617 PALMAS_USB_VB_SESS_END,
618 N_PALMAS_USB_VB_SESS_END,
619 PALMAS_USB_VB_SESS_VLD,
620 N_PALMAS_USB_VB_SESS_VLD,
621 PALMAS_USB_VA_SESS_VLD,
622 N_PALMAS_USB_VA_SESS_VLD,
623 PALMAS_USB_VA_VBUS_VLD,
624 N_PALMAS_USB_VA_VBUS_VLD,
625 PALMAS_USB_VADP_SNS,
626 N_PALMAS_USB_VADP_SNS,
627 PALMAS_USB_VADP_PRB,
628 N_PALMAS_USB_VADP_PRB,
629 PALMAS_USB_VOTG_SESS_VLD,
630 N_PALMAS_USB_VOTG_SESS_VLD,
631};
632
633/* defines so we can store the mux settings */
634#define PALMAS_GPIO_0_MUXED (1 << 0)
635#define PALMAS_GPIO_1_MUXED (1 << 1)
636#define PALMAS_GPIO_2_MUXED (1 << 2)
637#define PALMAS_GPIO_3_MUXED (1 << 3)
638#define PALMAS_GPIO_4_MUXED (1 << 4)
639#define PALMAS_GPIO_5_MUXED (1 << 5)
640#define PALMAS_GPIO_6_MUXED (1 << 6)
641#define PALMAS_GPIO_7_MUXED (1 << 7)
642
643#define PALMAS_LED1_MUXED (1 << 0)
644#define PALMAS_LED2_MUXED (1 << 1)
645
646#define PALMAS_PWM1_MUXED (1 << 0)
647#define PALMAS_PWM2_MUXED (1 << 1)
648
649/* helper macro to get correct slave number */
650#define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1)
651#define PALMAS_BASE_TO_REG(x, y) ((x & 0xFF) + y)
652
653/* Base addresses of IP blocks in Palmas */
654#define PALMAS_SMPS_DVS_BASE 0x020
655#define PALMAS_RTC_BASE 0x100
656#define PALMAS_VALIDITY_BASE 0x118
657#define PALMAS_SMPS_BASE 0x120
658#define PALMAS_LDO_BASE 0x150
659#define PALMAS_DVFS_BASE 0x180
660#define PALMAS_PMU_CONTROL_BASE 0x1A0
661#define PALMAS_RESOURCE_BASE 0x1D4
662#define PALMAS_PU_PD_OD_BASE 0x1F0
663#define PALMAS_LED_BASE 0x200
664#define PALMAS_INTERRUPT_BASE 0x210
665#define PALMAS_USB_OTG_BASE 0x250
666#define PALMAS_VIBRATOR_BASE 0x270
667#define PALMAS_GPIO_BASE 0x280
668#define PALMAS_USB_BASE 0x290
669#define PALMAS_GPADC_BASE 0x2C0
670#define PALMAS_TRIM_GPADC_BASE 0x3CD
671
672/* Registers for function RTC */
673#define PALMAS_SECONDS_REG 0x00
674#define PALMAS_MINUTES_REG 0x01
675#define PALMAS_HOURS_REG 0x02
676#define PALMAS_DAYS_REG 0x03
677#define PALMAS_MONTHS_REG 0x04
678#define PALMAS_YEARS_REG 0x05
679#define PALMAS_WEEKS_REG 0x06
680#define PALMAS_ALARM_SECONDS_REG 0x08
681#define PALMAS_ALARM_MINUTES_REG 0x09
682#define PALMAS_ALARM_HOURS_REG 0x0A
683#define PALMAS_ALARM_DAYS_REG 0x0B
684#define PALMAS_ALARM_MONTHS_REG 0x0C
685#define PALMAS_ALARM_YEARS_REG 0x0D
686#define PALMAS_RTC_CTRL_REG 0x10
687#define PALMAS_RTC_STATUS_REG 0x11
688#define PALMAS_RTC_INTERRUPTS_REG 0x12
689#define PALMAS_RTC_COMP_LSB_REG 0x13
690#define PALMAS_RTC_COMP_MSB_REG 0x14
691#define PALMAS_RTC_RES_PROG_REG 0x15
692#define PALMAS_RTC_RESET_STATUS_REG 0x16
693
694/* Bit definitions for SECONDS_REG */
695#define PALMAS_SECONDS_REG_SEC1_MASK 0x70
696#define PALMAS_SECONDS_REG_SEC1_SHIFT 0x04
697#define PALMAS_SECONDS_REG_SEC0_MASK 0x0F
698#define PALMAS_SECONDS_REG_SEC0_SHIFT 0x00
699
700/* Bit definitions for MINUTES_REG */
701#define PALMAS_MINUTES_REG_MIN1_MASK 0x70
702#define PALMAS_MINUTES_REG_MIN1_SHIFT 0x04
703#define PALMAS_MINUTES_REG_MIN0_MASK 0x0F
704#define PALMAS_MINUTES_REG_MIN0_SHIFT 0x00
705
706/* Bit definitions for HOURS_REG */
707#define PALMAS_HOURS_REG_PM_NAM 0x80
708#define PALMAS_HOURS_REG_PM_NAM_SHIFT 0x07
709#define PALMAS_HOURS_REG_HOUR1_MASK 0x30
710#define PALMAS_HOURS_REG_HOUR1_SHIFT 0x04
711#define PALMAS_HOURS_REG_HOUR0_MASK 0x0F
712#define PALMAS_HOURS_REG_HOUR0_SHIFT 0x00
713
714/* Bit definitions for DAYS_REG */
715#define PALMAS_DAYS_REG_DAY1_MASK 0x30
716#define PALMAS_DAYS_REG_DAY1_SHIFT 0x04
717#define PALMAS_DAYS_REG_DAY0_MASK 0x0F
718#define PALMAS_DAYS_REG_DAY0_SHIFT 0x00
719
720/* Bit definitions for MONTHS_REG */
721#define PALMAS_MONTHS_REG_MONTH1 0x10
722#define PALMAS_MONTHS_REG_MONTH1_SHIFT 0x04
723#define PALMAS_MONTHS_REG_MONTH0_MASK 0x0F
724#define PALMAS_MONTHS_REG_MONTH0_SHIFT 0x00
725
726/* Bit definitions for YEARS_REG */
727#define PALMAS_YEARS_REG_YEAR1_MASK 0xf0
728#define PALMAS_YEARS_REG_YEAR1_SHIFT 0x04
729#define PALMAS_YEARS_REG_YEAR0_MASK 0x0F
730#define PALMAS_YEARS_REG_YEAR0_SHIFT 0x00
731
732/* Bit definitions for WEEKS_REG */
733#define PALMAS_WEEKS_REG_WEEK_MASK 0x07
734#define PALMAS_WEEKS_REG_WEEK_SHIFT 0x00
735
736/* Bit definitions for ALARM_SECONDS_REG */
737#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70
738#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 0x04
739#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0F
740#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0x00
741
742/* Bit definitions for ALARM_MINUTES_REG */
743#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70
744#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 0x04
745#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0F
746#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0x00
747
748/* Bit definitions for ALARM_HOURS_REG */
749#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80
750#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 0x07
751#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30
752#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 0x04
753#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0F
754#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0x00
755
756/* Bit definitions for ALARM_DAYS_REG */
757#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30
758#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 0x04
759#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0F
760#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0x00
761
762/* Bit definitions for ALARM_MONTHS_REG */
763#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10
764#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 0x04
765#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0F
766#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0x00
767
768/* Bit definitions for ALARM_YEARS_REG */
769#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0
770#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 0x04
771#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0F
772#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0x00
773
774/* Bit definitions for RTC_CTRL_REG */
775#define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80
776#define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 0x07
777#define PALMAS_RTC_CTRL_REG_GET_TIME 0x40
778#define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 0x06
779#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20
780#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 0x05
781#define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10
782#define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 0x04
783#define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08
784#define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 0x03
785#define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04
786#define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 0x02
787#define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02
788#define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 0x01
789#define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01
790#define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0x00
791
792/* Bit definitions for RTC_STATUS_REG */
793#define PALMAS_RTC_STATUS_REG_POWER_UP 0x80
794#define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 0x07
795#define PALMAS_RTC_STATUS_REG_ALARM 0x40
796#define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 0x06
797#define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20
798#define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 0x05
799#define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10
800#define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 0x04
801#define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08
802#define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 0x03
803#define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04
804#define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 0x02
805#define PALMAS_RTC_STATUS_REG_RUN 0x02
806#define PALMAS_RTC_STATUS_REG_RUN_SHIFT 0x01
807
808/* Bit definitions for RTC_INTERRUPTS_REG */
809#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10
810#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 0x04
811#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08
812#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 0x03
813#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04
814#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 0x02
815#define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03
816#define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0x00
817
818/* Bit definitions for RTC_COMP_LSB_REG */
819#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xFF
820#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0x00
821
822/* Bit definitions for RTC_COMP_MSB_REG */
823#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xFF
824#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0x00
825
826/* Bit definitions for RTC_RES_PROG_REG */
827#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3F
828#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0x00
829
830/* Bit definitions for RTC_RESET_STATUS_REG */
831#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01
832#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0x00
833
834/* Registers for function BACKUP */
835#define PALMAS_BACKUP0 0x00
836#define PALMAS_BACKUP1 0x01
837#define PALMAS_BACKUP2 0x02
838#define PALMAS_BACKUP3 0x03
839#define PALMAS_BACKUP4 0x04
840#define PALMAS_BACKUP5 0x05
841#define PALMAS_BACKUP6 0x06
842#define PALMAS_BACKUP7 0x07
843
844/* Bit definitions for BACKUP0 */
845#define PALMAS_BACKUP0_BACKUP_MASK 0xFF
846#define PALMAS_BACKUP0_BACKUP_SHIFT 0x00
847
848/* Bit definitions for BACKUP1 */
849#define PALMAS_BACKUP1_BACKUP_MASK 0xFF
850#define PALMAS_BACKUP1_BACKUP_SHIFT 0x00
851
852/* Bit definitions for BACKUP2 */
853#define PALMAS_BACKUP2_BACKUP_MASK 0xFF
854#define PALMAS_BACKUP2_BACKUP_SHIFT 0x00
855
856/* Bit definitions for BACKUP3 */
857#define PALMAS_BACKUP3_BACKUP_MASK 0xFF
858#define PALMAS_BACKUP3_BACKUP_SHIFT 0x00
859
860/* Bit definitions for BACKUP4 */
861#define PALMAS_BACKUP4_BACKUP_MASK 0xFF
862#define PALMAS_BACKUP4_BACKUP_SHIFT 0x00
863
864/* Bit definitions for BACKUP5 */
865#define PALMAS_BACKUP5_BACKUP_MASK 0xFF
866#define PALMAS_BACKUP5_BACKUP_SHIFT 0x00
867
868/* Bit definitions for BACKUP6 */
869#define PALMAS_BACKUP6_BACKUP_MASK 0xFF
870#define PALMAS_BACKUP6_BACKUP_SHIFT 0x00
871
872/* Bit definitions for BACKUP7 */
873#define PALMAS_BACKUP7_BACKUP_MASK 0xFF
874#define PALMAS_BACKUP7_BACKUP_SHIFT 0x00
875
876/* Registers for function SMPS */
877#define PALMAS_SMPS12_CTRL 0x00
878#define PALMAS_SMPS12_TSTEP 0x01
879#define PALMAS_SMPS12_FORCE 0x02
880#define PALMAS_SMPS12_VOLTAGE 0x03
881#define PALMAS_SMPS3_CTRL 0x04
882#define PALMAS_SMPS3_VOLTAGE 0x07
883#define PALMAS_SMPS45_CTRL 0x08
884#define PALMAS_SMPS45_TSTEP 0x09
885#define PALMAS_SMPS45_FORCE 0x0A
886#define PALMAS_SMPS45_VOLTAGE 0x0B
887#define PALMAS_SMPS6_CTRL 0x0C
888#define PALMAS_SMPS6_TSTEP 0x0D
889#define PALMAS_SMPS6_FORCE 0x0E
890#define PALMAS_SMPS6_VOLTAGE 0x0F
891#define PALMAS_SMPS7_CTRL 0x10
892#define PALMAS_SMPS7_VOLTAGE 0x13
893#define PALMAS_SMPS8_CTRL 0x14
894#define PALMAS_SMPS8_TSTEP 0x15
895#define PALMAS_SMPS8_FORCE 0x16
896#define PALMAS_SMPS8_VOLTAGE 0x17
897#define PALMAS_SMPS9_CTRL 0x18
898#define PALMAS_SMPS9_VOLTAGE 0x1B
899#define PALMAS_SMPS10_CTRL 0x1C
900#define PALMAS_SMPS10_STATUS 0x1F
901#define PALMAS_SMPS_CTRL 0x24
902#define PALMAS_SMPS_PD_CTRL 0x25
903#define PALMAS_SMPS_DITHER_EN 0x26
904#define PALMAS_SMPS_THERMAL_EN 0x27
905#define PALMAS_SMPS_THERMAL_STATUS 0x28
906#define PALMAS_SMPS_SHORT_STATUS 0x29
907#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A
908#define PALMAS_SMPS_POWERGOOD_MASK1 0x2B
909#define PALMAS_SMPS_POWERGOOD_MASK2 0x2C
910
911/* Bit definitions for SMPS12_CTRL */
912#define PALMAS_SMPS12_CTRL_WR_S 0x80
913#define PALMAS_SMPS12_CTRL_WR_S_SHIFT 0x07
914#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40
915#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
916#define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30
917#define PALMAS_SMPS12_CTRL_STATUS_SHIFT 0x04
918#define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c
919#define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 0x02
920#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03
921#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0x00
922
923/* Bit definitions for SMPS12_TSTEP */
924#define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03
925#define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0x00
926
927/* Bit definitions for SMPS12_FORCE */
928#define PALMAS_SMPS12_FORCE_CMD 0x80
929#define PALMAS_SMPS12_FORCE_CMD_SHIFT 0x07
930#define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7F
931#define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0x00
932
933/* Bit definitions for SMPS12_VOLTAGE */
934#define PALMAS_SMPS12_VOLTAGE_RANGE 0x80
935#define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 0x07
936#define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7F
937#define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0x00
938
939/* Bit definitions for SMPS3_CTRL */
940#define PALMAS_SMPS3_CTRL_WR_S 0x80
941#define PALMAS_SMPS3_CTRL_WR_S_SHIFT 0x07
942#define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30
943#define PALMAS_SMPS3_CTRL_STATUS_SHIFT 0x04
944#define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c
945#define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02
946#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
947#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00
948
949/* Bit definitions for SMPS3_VOLTAGE */
950#define PALMAS_SMPS3_VOLTAGE_RANGE 0x80
951#define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 0x07
952#define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7F
953#define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0x00
954
955/* Bit definitions for SMPS45_CTRL */
956#define PALMAS_SMPS45_CTRL_WR_S 0x80
957#define PALMAS_SMPS45_CTRL_WR_S_SHIFT 0x07
958#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40
959#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
960#define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30
961#define PALMAS_SMPS45_CTRL_STATUS_SHIFT 0x04
962#define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c
963#define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 0x02
964#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03
965#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0x00
966
967/* Bit definitions for SMPS45_TSTEP */
968#define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03
969#define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0x00
970
971/* Bit definitions for SMPS45_FORCE */
972#define PALMAS_SMPS45_FORCE_CMD 0x80
973#define PALMAS_SMPS45_FORCE_CMD_SHIFT 0x07
974#define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7F
975#define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0x00
976
977/* Bit definitions for SMPS45_VOLTAGE */
978#define PALMAS_SMPS45_VOLTAGE_RANGE 0x80
979#define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 0x07
980#define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7F
981#define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0x00
982
983/* Bit definitions for SMPS6_CTRL */
984#define PALMAS_SMPS6_CTRL_WR_S 0x80
985#define PALMAS_SMPS6_CTRL_WR_S_SHIFT 0x07
986#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40
987#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
988#define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30
989#define PALMAS_SMPS6_CTRL_STATUS_SHIFT 0x04
990#define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c
991#define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 0x02
992#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03
993#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0x00
994
995/* Bit definitions for SMPS6_TSTEP */
996#define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03
997#define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0x00
998
999/* Bit definitions for SMPS6_FORCE */
1000#define PALMAS_SMPS6_FORCE_CMD 0x80
1001#define PALMAS_SMPS6_FORCE_CMD_SHIFT 0x07
1002#define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7F
1003#define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0x00
1004
1005/* Bit definitions for SMPS6_VOLTAGE */
1006#define PALMAS_SMPS6_VOLTAGE_RANGE 0x80
1007#define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 0x07
1008#define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7F
1009#define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0x00
1010
1011/* Bit definitions for SMPS7_CTRL */
1012#define PALMAS_SMPS7_CTRL_WR_S 0x80
1013#define PALMAS_SMPS7_CTRL_WR_S_SHIFT 0x07
1014#define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30
1015#define PALMAS_SMPS7_CTRL_STATUS_SHIFT 0x04
1016#define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c
1017#define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 0x02
1018#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03
1019#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0x00
1020
1021/* Bit definitions for SMPS7_VOLTAGE */
1022#define PALMAS_SMPS7_VOLTAGE_RANGE 0x80
1023#define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 0x07
1024#define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7F
1025#define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0x00
1026
1027/* Bit definitions for SMPS8_CTRL */
1028#define PALMAS_SMPS8_CTRL_WR_S 0x80
1029#define PALMAS_SMPS8_CTRL_WR_S_SHIFT 0x07
1030#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40
1031#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
1032#define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30
1033#define PALMAS_SMPS8_CTRL_STATUS_SHIFT 0x04
1034#define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c
1035#define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 0x02
1036#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03
1037#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0x00
1038
1039/* Bit definitions for SMPS8_TSTEP */
1040#define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03
1041#define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0x00
1042
1043/* Bit definitions for SMPS8_FORCE */
1044#define PALMAS_SMPS8_FORCE_CMD 0x80
1045#define PALMAS_SMPS8_FORCE_CMD_SHIFT 0x07
1046#define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7F
1047#define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0x00
1048
1049/* Bit definitions for SMPS8_VOLTAGE */
1050#define PALMAS_SMPS8_VOLTAGE_RANGE 0x80
1051#define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 0x07
1052#define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7F
1053#define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0x00
1054
1055/* Bit definitions for SMPS9_CTRL */
1056#define PALMAS_SMPS9_CTRL_WR_S 0x80
1057#define PALMAS_SMPS9_CTRL_WR_S_SHIFT 0x07
1058#define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30
1059#define PALMAS_SMPS9_CTRL_STATUS_SHIFT 0x04
1060#define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c
1061#define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 0x02
1062#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03
1063#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0x00
1064
1065/* Bit definitions for SMPS9_VOLTAGE */
1066#define PALMAS_SMPS9_VOLTAGE_RANGE 0x80
1067#define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 0x07
1068#define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7F
1069#define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0x00
1070
1071/* Bit definitions for SMPS10_CTRL */
1072#define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0
1073#define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 0x04
1074#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0F
1075#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0x00
1076
1077/* Bit definitions for SMPS10_STATUS */
1078#define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0F
1079#define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0x00
1080
1081/* Bit definitions for SMPS_CTRL */
1082#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20
1083#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 0x05
1084#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10
1085#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 0x04
1086#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c
1087#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 0x02
1088#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03
1089#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0x00
1090
1091/* Bit definitions for SMPS_PD_CTRL */
1092#define PALMAS_SMPS_PD_CTRL_SMPS9 0x40
1093#define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 0x06
1094#define PALMAS_SMPS_PD_CTRL_SMPS8 0x20
1095#define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 0x05
1096#define PALMAS_SMPS_PD_CTRL_SMPS7 0x10
1097#define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 0x04
1098#define PALMAS_SMPS_PD_CTRL_SMPS6 0x08
1099#define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 0x03
1100#define PALMAS_SMPS_PD_CTRL_SMPS45 0x04
1101#define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 0x02
1102#define PALMAS_SMPS_PD_CTRL_SMPS3 0x02
1103#define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 0x01
1104#define PALMAS_SMPS_PD_CTRL_SMPS12 0x01
1105#define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0x00
1106
1107/* Bit definitions for SMPS_THERMAL_EN */
1108#define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40
1109#define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 0x06
1110#define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20
1111#define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 0x05
1112#define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08
1113#define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 0x03
1114#define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04
1115#define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 0x02
1116#define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01
1117#define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0x00
1118
1119/* Bit definitions for SMPS_THERMAL_STATUS */
1120#define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40
1121#define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 0x06
1122#define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20
1123#define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 0x05
1124#define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08
1125#define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 0x03
1126#define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04
1127#define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 0x02
1128#define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01
1129#define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0x00
1130
1131/* Bit definitions for SMPS_SHORT_STATUS */
1132#define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80
1133#define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 0x07
1134#define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40
1135#define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 0x06
1136#define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20
1137#define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 0x05
1138#define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10
1139#define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 0x04
1140#define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08
1141#define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 0x03
1142#define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04
1143#define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 0x02
1144#define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02
1145#define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x01
1146#define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01
1147#define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0x00
1148
1149/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
1150#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40
1151#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 0x06
1152#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20
1153#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 0x05
1154#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10
1155#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 0x04
1156#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08
1157#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 0x03
1158#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04
1159#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 0x02
1160#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02
1161#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x01
1162#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01
1163#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0x00
1164
1165/* Bit definitions for SMPS_POWERGOOD_MASK1 */
1166#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80
1167#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 0x07
1168#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40
1169#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 0x06
1170#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20
1171#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 0x05
1172#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10
1173#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 0x04
1174#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08
1175#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 0x03
1176#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04
1177#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 0x02
1178#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02
1179#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x01
1180#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01
1181#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0x00
1182
1183/* Bit definitions for SMPS_POWERGOOD_MASK2 */
1184#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
1185#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07
1186#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04
1187#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 0x02
1188#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02
1189#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 0x01
1190#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01
1191#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0x00
1192
1193/* Registers for function LDO */
1194#define PALMAS_LDO1_CTRL 0x00
1195#define PALMAS_LDO1_VOLTAGE 0x01
1196#define PALMAS_LDO2_CTRL 0x02
1197#define PALMAS_LDO2_VOLTAGE 0x03
1198#define PALMAS_LDO3_CTRL 0x04
1199#define PALMAS_LDO3_VOLTAGE 0x05
1200#define PALMAS_LDO4_CTRL 0x06
1201#define PALMAS_LDO4_VOLTAGE 0x07
1202#define PALMAS_LDO5_CTRL 0x08
1203#define PALMAS_LDO5_VOLTAGE 0x09
1204#define PALMAS_LDO6_CTRL 0x0A
1205#define PALMAS_LDO6_VOLTAGE 0x0B
1206#define PALMAS_LDO7_CTRL 0x0C
1207#define PALMAS_LDO7_VOLTAGE 0x0D
1208#define PALMAS_LDO8_CTRL 0x0E
1209#define PALMAS_LDO8_VOLTAGE 0x0F
1210#define PALMAS_LDO9_CTRL 0x10
1211#define PALMAS_LDO9_VOLTAGE 0x11
1212#define PALMAS_LDOLN_CTRL 0x12
1213#define PALMAS_LDOLN_VOLTAGE 0x13
1214#define PALMAS_LDOUSB_CTRL 0x14
1215#define PALMAS_LDOUSB_VOLTAGE 0x15
1216#define PALMAS_LDO_CTRL 0x1A
1217#define PALMAS_LDO_PD_CTRL1 0x1B
1218#define PALMAS_LDO_PD_CTRL2 0x1C
1219#define PALMAS_LDO_SHORT_STATUS1 0x1D
1220#define PALMAS_LDO_SHORT_STATUS2 0x1E
1221
1222/* Bit definitions for LDO1_CTRL */
1223#define PALMAS_LDO1_CTRL_WR_S 0x80
1224#define PALMAS_LDO1_CTRL_WR_S_SHIFT 0x07
1225#define PALMAS_LDO1_CTRL_STATUS 0x10
1226#define PALMAS_LDO1_CTRL_STATUS_SHIFT 0x04
1227#define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04
1228#define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02
1229#define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01
1230#define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00
1231
1232/* Bit definitions for LDO1_VOLTAGE */
1233#define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3F
1234#define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0x00
1235
1236/* Bit definitions for LDO2_CTRL */
1237#define PALMAS_LDO2_CTRL_WR_S 0x80
1238#define PALMAS_LDO2_CTRL_WR_S_SHIFT 0x07
1239#define PALMAS_LDO2_CTRL_STATUS 0x10
1240#define PALMAS_LDO2_CTRL_STATUS_SHIFT 0x04
1241#define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04
1242#define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02
1243#define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01
1244#define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00
1245
1246/* Bit definitions for LDO2_VOLTAGE */
1247#define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3F
1248#define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0x00
1249
1250/* Bit definitions for LDO3_CTRL */
1251#define PALMAS_LDO3_CTRL_WR_S 0x80
1252#define PALMAS_LDO3_CTRL_WR_S_SHIFT 0x07
1253#define PALMAS_LDO3_CTRL_STATUS 0x10
1254#define PALMAS_LDO3_CTRL_STATUS_SHIFT 0x04
1255#define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04
1256#define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02
1257#define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01
1258#define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00
1259
1260/* Bit definitions for LDO3_VOLTAGE */
1261#define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3F
1262#define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0x00
1263
1264/* Bit definitions for LDO4_CTRL */
1265#define PALMAS_LDO4_CTRL_WR_S 0x80
1266#define PALMAS_LDO4_CTRL_WR_S_SHIFT 0x07
1267#define PALMAS_LDO4_CTRL_STATUS 0x10
1268#define PALMAS_LDO4_CTRL_STATUS_SHIFT 0x04
1269#define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04
1270#define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02
1271#define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01
1272#define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00
1273
1274/* Bit definitions for LDO4_VOLTAGE */
1275#define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3F
1276#define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0x00
1277
1278/* Bit definitions for LDO5_CTRL */
1279#define PALMAS_LDO5_CTRL_WR_S 0x80
1280#define PALMAS_LDO5_CTRL_WR_S_SHIFT 0x07
1281#define PALMAS_LDO5_CTRL_STATUS 0x10
1282#define PALMAS_LDO5_CTRL_STATUS_SHIFT 0x04
1283#define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04
1284#define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02
1285#define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01
1286#define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00
1287
1288/* Bit definitions for LDO5_VOLTAGE */
1289#define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3F
1290#define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0x00
1291
1292/* Bit definitions for LDO6_CTRL */
1293#define PALMAS_LDO6_CTRL_WR_S 0x80
1294#define PALMAS_LDO6_CTRL_WR_S_SHIFT 0x07
1295#define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40
1296#define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 0x06
1297#define PALMAS_LDO6_CTRL_STATUS 0x10
1298#define PALMAS_LDO6_CTRL_STATUS_SHIFT 0x04
1299#define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04
1300#define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 0x02
1301#define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01
1302#define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0x00
1303
1304/* Bit definitions for LDO6_VOLTAGE */
1305#define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3F
1306#define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0x00
1307
1308/* Bit definitions for LDO7_CTRL */
1309#define PALMAS_LDO7_CTRL_WR_S 0x80
1310#define PALMAS_LDO7_CTRL_WR_S_SHIFT 0x07
1311#define PALMAS_LDO7_CTRL_STATUS 0x10
1312#define PALMAS_LDO7_CTRL_STATUS_SHIFT 0x04
1313#define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04
1314#define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 0x02
1315#define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01
1316#define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0x00
1317
1318/* Bit definitions for LDO7_VOLTAGE */
1319#define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3F
1320#define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0x00
1321
1322/* Bit definitions for LDO8_CTRL */
1323#define PALMAS_LDO8_CTRL_WR_S 0x80
1324#define PALMAS_LDO8_CTRL_WR_S_SHIFT 0x07
1325#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40
1326#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 0x06
1327#define PALMAS_LDO8_CTRL_STATUS 0x10
1328#define PALMAS_LDO8_CTRL_STATUS_SHIFT 0x04
1329#define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04
1330#define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 0x02
1331#define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01
1332#define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0x00
1333
1334/* Bit definitions for LDO8_VOLTAGE */
1335#define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3F
1336#define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0x00
1337
1338/* Bit definitions for LDO9_CTRL */
1339#define PALMAS_LDO9_CTRL_WR_S 0x80
1340#define PALMAS_LDO9_CTRL_WR_S_SHIFT 0x07
1341#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40
1342#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 0x06
1343#define PALMAS_LDO9_CTRL_STATUS 0x10
1344#define PALMAS_LDO9_CTRL_STATUS_SHIFT 0x04
1345#define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04
1346#define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 0x02
1347#define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01
1348#define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0x00
1349
1350/* Bit definitions for LDO9_VOLTAGE */
1351#define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3F
1352#define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0x00
1353
1354/* Bit definitions for LDOLN_CTRL */
1355#define PALMAS_LDOLN_CTRL_WR_S 0x80
1356#define PALMAS_LDOLN_CTRL_WR_S_SHIFT 0x07
1357#define PALMAS_LDOLN_CTRL_STATUS 0x10
1358#define PALMAS_LDOLN_CTRL_STATUS_SHIFT 0x04
1359#define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04
1360#define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 0x02
1361#define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01
1362#define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0x00
1363
1364/* Bit definitions for LDOLN_VOLTAGE */
1365#define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3F
1366#define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0x00
1367
1368/* Bit definitions for LDOUSB_CTRL */
1369#define PALMAS_LDOUSB_CTRL_WR_S 0x80
1370#define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 0x07
1371#define PALMAS_LDOUSB_CTRL_STATUS 0x10
1372#define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 0x04
1373#define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04
1374#define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 0x02
1375#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01
1376#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0x00
1377
1378/* Bit definitions for LDOUSB_VOLTAGE */
1379#define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3F
1380#define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0x00
1381
1382/* Bit definitions for LDO_CTRL */
1383#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01
1384#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0x00
1385
1386/* Bit definitions for LDO_PD_CTRL1 */
1387#define PALMAS_LDO_PD_CTRL1_LDO8 0x80
1388#define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 0x07
1389#define PALMAS_LDO_PD_CTRL1_LDO7 0x40
1390#define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 0x06
1391#define PALMAS_LDO_PD_CTRL1_LDO6 0x20
1392#define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 0x05
1393#define PALMAS_LDO_PD_CTRL1_LDO5 0x10
1394#define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 0x04
1395#define PALMAS_LDO_PD_CTRL1_LDO4 0x08
1396#define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 0x03
1397#define PALMAS_LDO_PD_CTRL1_LDO3 0x04
1398#define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 0x02
1399#define PALMAS_LDO_PD_CTRL1_LDO2 0x02
1400#define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 0x01
1401#define PALMAS_LDO_PD_CTRL1_LDO1 0x01
1402#define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0x00
1403
1404/* Bit definitions for LDO_PD_CTRL2 */
1405#define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04
1406#define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 0x02
1407#define PALMAS_LDO_PD_CTRL2_LDOLN 0x02
1408#define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 0x01
1409#define PALMAS_LDO_PD_CTRL2_LDO9 0x01
1410#define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0x00
1411
1412/* Bit definitions for LDO_SHORT_STATUS1 */
1413#define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80
1414#define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 0x07
1415#define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40
1416#define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 0x06
1417#define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20
1418#define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 0x05
1419#define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10
1420#define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 0x04
1421#define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08
1422#define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 0x03
1423#define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04
1424#define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 0x02
1425#define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02
1426#define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01
1427#define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01
1428#define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00
1429
1430/* Bit definitions for LDO_SHORT_STATUS2 */
1431#define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08
1432#define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x03
1433#define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04
1434#define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 0x02
1435#define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02
1436#define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 0x01
1437#define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01
1438#define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0x00
1439
1440/* Registers for function PMU_CONTROL */
1441#define PALMAS_DEV_CTRL 0x00
1442#define PALMAS_POWER_CTRL 0x01
1443#define PALMAS_VSYS_LO 0x02
1444#define PALMAS_VSYS_MON 0x03
1445#define PALMAS_VBAT_MON 0x04
1446#define PALMAS_WATCHDOG 0x05
1447#define PALMAS_BOOT_STATUS 0x06
1448#define PALMAS_BATTERY_BOUNCE 0x07
1449#define PALMAS_BACKUP_BATTERY_CTRL 0x08
1450#define PALMAS_LONG_PRESS_KEY 0x09
1451#define PALMAS_OSC_THERM_CTRL 0x0A
1452#define PALMAS_BATDEBOUNCING 0x0B
1453#define PALMAS_SWOFF_HWRST 0x0F
1454#define PALMAS_SWOFF_COLDRST 0x10
1455#define PALMAS_SWOFF_STATUS 0x11
1456#define PALMAS_PMU_CONFIG 0x12
1457#define PALMAS_SPARE 0x14
1458#define PALMAS_PMU_SECONDARY_INT 0x15
1459#define PALMAS_SW_REVISION 0x17
1460#define PALMAS_EXT_CHRG_CTRL 0x18
1461#define PALMAS_PMU_SECONDARY_INT2 0x19
1462
1463/* Bit definitions for DEV_CTRL */
1464#define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c
1465#define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 0x02
1466#define PALMAS_DEV_CTRL_SW_RST 0x02
1467#define PALMAS_DEV_CTRL_SW_RST_SHIFT 0x01
1468#define PALMAS_DEV_CTRL_DEV_ON 0x01
1469#define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0x00
1470
1471/* Bit definitions for POWER_CTRL */
1472#define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04
1473#define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 0x02
1474#define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02
1475#define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 0x01
1476#define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01
1477#define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0x00
1478
1479/* Bit definitions for VSYS_LO */
1480#define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1F
1481#define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0x00
1482
1483/* Bit definitions for VSYS_MON */
1484#define PALMAS_VSYS_MON_ENABLE 0x80
1485#define PALMAS_VSYS_MON_ENABLE_SHIFT 0x07
1486#define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3F
1487#define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0x00
1488
1489/* Bit definitions for VBAT_MON */
1490#define PALMAS_VBAT_MON_ENABLE 0x80
1491#define PALMAS_VBAT_MON_ENABLE_SHIFT 0x07
1492#define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3F
1493#define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0x00
1494
1495/* Bit definitions for WATCHDOG */
1496#define PALMAS_WATCHDOG_LOCK 0x20
1497#define PALMAS_WATCHDOG_LOCK_SHIFT 0x05
1498#define PALMAS_WATCHDOG_ENABLE 0x10
1499#define PALMAS_WATCHDOG_ENABLE_SHIFT 0x04
1500#define PALMAS_WATCHDOG_MODE 0x08
1501#define PALMAS_WATCHDOG_MODE_SHIFT 0x03
1502#define PALMAS_WATCHDOG_TIMER_MASK 0x07
1503#define PALMAS_WATCHDOG_TIMER_SHIFT 0x00
1504
1505/* Bit definitions for BOOT_STATUS */
1506#define PALMAS_BOOT_STATUS_BOOT1 0x02
1507#define PALMAS_BOOT_STATUS_BOOT1_SHIFT 0x01
1508#define PALMAS_BOOT_STATUS_BOOT0 0x01
1509#define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0x00
1510
1511/* Bit definitions for BATTERY_BOUNCE */
1512#define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3F
1513#define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0x00
1514
1515/* Bit definitions for BACKUP_BATTERY_CTRL */
1516#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80
1517#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 0x07
1518#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40
1519#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 0x06
1520#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20
1521#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 0x05
1522#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10
1523#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 0x04
1524#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08
1525#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 0x03
1526#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06
1527#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 0x01
1528#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01
1529#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0x00
1530
1531/* Bit definitions for LONG_PRESS_KEY */
1532#define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80
1533#define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 0x07
1534#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10
1535#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 0x04
1536#define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c
1537#define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 0x02
1538#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03
1539#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0x00
1540
1541/* Bit definitions for OSC_THERM_CTRL */
1542#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80
1543#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 0x07
1544#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40
1545#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 0x06
1546#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20
1547#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 0x05
1548#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10
1549#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 0x04
1550#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c
1551#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 0x02
1552#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02
1553#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 0x01
1554#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01
1555#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0x00
1556
1557/* Bit definitions for BATDEBOUNCING */
1558#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80
1559#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 0x07
1560#define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78
1561#define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 0x03
1562#define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07
1563#define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0x00
1564
1565/* Bit definitions for SWOFF_HWRST */
1566#define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80
1567#define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 0x07
1568#define PALMAS_SWOFF_HWRST_PWRDOWN 0x40
1569#define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 0x06
1570#define PALMAS_SWOFF_HWRST_WTD 0x20
1571#define PALMAS_SWOFF_HWRST_WTD_SHIFT 0x05
1572#define PALMAS_SWOFF_HWRST_TSHUT 0x10
1573#define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 0x04
1574#define PALMAS_SWOFF_HWRST_RESET_IN 0x08
1575#define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 0x03
1576#define PALMAS_SWOFF_HWRST_SW_RST 0x04
1577#define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 0x02
1578#define PALMAS_SWOFF_HWRST_VSYS_LO 0x02
1579#define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 0x01
1580#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01
1581#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0x00
1582
1583/* Bit definitions for SWOFF_COLDRST */
1584#define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80
1585#define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 0x07
1586#define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40
1587#define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 0x06
1588#define PALMAS_SWOFF_COLDRST_WTD 0x20
1589#define PALMAS_SWOFF_COLDRST_WTD_SHIFT 0x05
1590#define PALMAS_SWOFF_COLDRST_TSHUT 0x10
1591#define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 0x04
1592#define PALMAS_SWOFF_COLDRST_RESET_IN 0x08
1593#define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 0x03
1594#define PALMAS_SWOFF_COLDRST_SW_RST 0x04
1595#define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 0x02
1596#define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02
1597#define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 0x01
1598#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01
1599#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0x00
1600
1601/* Bit definitions for SWOFF_STATUS */
1602#define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80
1603#define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 0x07
1604#define PALMAS_SWOFF_STATUS_PWRDOWN 0x40
1605#define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 0x06
1606#define PALMAS_SWOFF_STATUS_WTD 0x20
1607#define PALMAS_SWOFF_STATUS_WTD_SHIFT 0x05
1608#define PALMAS_SWOFF_STATUS_TSHUT 0x10
1609#define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 0x04
1610#define PALMAS_SWOFF_STATUS_RESET_IN 0x08
1611#define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 0x03
1612#define PALMAS_SWOFF_STATUS_SW_RST 0x04
1613#define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 0x02
1614#define PALMAS_SWOFF_STATUS_VSYS_LO 0x02
1615#define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 0x01
1616#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01
1617#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0x00
1618
1619/* Bit definitions for PMU_CONFIG */
1620#define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40
1621#define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 0x06
1622#define PALMAS_PMU_CONFIG_SPARE_MASK 0x30
1623#define PALMAS_PMU_CONFIG_SPARE_SHIFT 0x04
1624#define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c
1625#define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 0x02
1626#define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02
1627#define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 0x01
1628#define PALMAS_PMU_CONFIG_AUTODEVON 0x01
1629#define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0x00
1630
1631/* Bit definitions for SPARE */
1632#define PALMAS_SPARE_SPARE_MASK 0xf8
1633#define PALMAS_SPARE_SPARE_SHIFT 0x03
1634#define PALMAS_SPARE_REGEN3_OD 0x04
1635#define PALMAS_SPARE_REGEN3_OD_SHIFT 0x02
1636#define PALMAS_SPARE_REGEN2_OD 0x02
1637#define PALMAS_SPARE_REGEN2_OD_SHIFT 0x01
1638#define PALMAS_SPARE_REGEN1_OD 0x01
1639#define PALMAS_SPARE_REGEN1_OD_SHIFT 0x00
1640
1641/* Bit definitions for PMU_SECONDARY_INT */
1642#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80
1643#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 0x07
1644#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40
1645#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 0x06
1646#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20
1647#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 0x05
1648#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10
1649#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 0x04
1650#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08
1651#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 0x03
1652#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04
1653#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 0x02
1654#define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02
1655#define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 0x01
1656#define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01
1657#define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0x00
1658
1659/* Bit definitions for SW_REVISION */
1660#define PALMAS_SW_REVISION_SW_REVISION_MASK 0xFF
1661#define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0x00
1662
1663/* Bit definitions for EXT_CHRG_CTRL */
1664#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80
1665#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 0x07
1666#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40
1667#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 0x06
1668#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08
1669#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 0x03
1670#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04
1671#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 0x02
1672#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02
1673#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 0x01
1674#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01
1675#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0x00
1676
1677/* Bit definitions for PMU_SECONDARY_INT2 */
1678#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20
1679#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 0x05
1680#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10
1681#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 0x04
1682#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02
1683#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 0x01
1684#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01
1685#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0x00
1686
1687/* Registers for function RESOURCE */
1688#define PALMAS_CLK32KG_CTRL 0x00
1689#define PALMAS_CLK32KGAUDIO_CTRL 0x01
1690#define PALMAS_REGEN1_CTRL 0x02
1691#define PALMAS_REGEN2_CTRL 0x03
1692#define PALMAS_SYSEN1_CTRL 0x04
1693#define PALMAS_SYSEN2_CTRL 0x05
1694#define PALMAS_NSLEEP_RES_ASSIGN 0x06
1695#define PALMAS_NSLEEP_SMPS_ASSIGN 0x07
1696#define PALMAS_NSLEEP_LDO_ASSIGN1 0x08
1697#define PALMAS_NSLEEP_LDO_ASSIGN2 0x09
1698#define PALMAS_ENABLE1_RES_ASSIGN 0x0A
1699#define PALMAS_ENABLE1_SMPS_ASSIGN 0x0B
1700#define PALMAS_ENABLE1_LDO_ASSIGN1 0x0C
1701#define PALMAS_ENABLE1_LDO_ASSIGN2 0x0D
1702#define PALMAS_ENABLE2_RES_ASSIGN 0x0E
1703#define PALMAS_ENABLE2_SMPS_ASSIGN 0x0F
1704#define PALMAS_ENABLE2_LDO_ASSIGN1 0x10
1705#define PALMAS_ENABLE2_LDO_ASSIGN2 0x11
1706#define PALMAS_REGEN3_CTRL 0x12
1707
1708/* Bit definitions for CLK32KG_CTRL */
1709#define PALMAS_CLK32KG_CTRL_STATUS 0x10
1710#define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 0x04
1711#define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04
1712#define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 0x02
1713#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01
1714#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0x00
1715
1716/* Bit definitions for CLK32KGAUDIO_CTRL */
1717#define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10
1718#define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 0x04
1719#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08
1720#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 0x03
1721#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04
1722#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 0x02
1723#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01
1724#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0x00
1725
1726/* Bit definitions for REGEN1_CTRL */
1727#define PALMAS_REGEN1_CTRL_STATUS 0x10
1728#define PALMAS_REGEN1_CTRL_STATUS_SHIFT 0x04
1729#define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04
1730#define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02
1731#define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01
1732#define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
1733
1734/* Bit definitions for REGEN2_CTRL */
1735#define PALMAS_REGEN2_CTRL_STATUS 0x10
1736#define PALMAS_REGEN2_CTRL_STATUS_SHIFT 0x04
1737#define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04
1738#define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02
1739#define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01
1740#define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
1741
1742/* Bit definitions for SYSEN1_CTRL */
1743#define PALMAS_SYSEN1_CTRL_STATUS 0x10
1744#define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 0x04
1745#define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04
1746#define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 0x02
1747#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01
1748#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
1749
1750/* Bit definitions for SYSEN2_CTRL */
1751#define PALMAS_SYSEN2_CTRL_STATUS 0x10
1752#define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 0x04
1753#define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04
1754#define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 0x02
1755#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01
1756#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
1757
1758/* Bit definitions for NSLEEP_RES_ASSIGN */
1759#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40
1760#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x06
1761#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20
1762#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
1763#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10
1764#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 0x04
1765#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08
1766#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 0x03
1767#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04
1768#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 0x02
1769#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02
1770#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01
1771#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01
1772#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00
1773
1774/* Bit definitions for NSLEEP_SMPS_ASSIGN */
1775#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80
1776#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 0x07
1777#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40
1778#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 0x06
1779#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20
1780#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 0x05
1781#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10
1782#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 0x04
1783#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08
1784#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 0x03
1785#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04
1786#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 0x02
1787#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02
1788#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x01
1789#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01
1790#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0x00
1791
1792/* Bit definitions for NSLEEP_LDO_ASSIGN1 */
1793#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80
1794#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 0x07
1795#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40
1796#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 0x06
1797#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20
1798#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 0x05
1799#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10
1800#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 0x04
1801#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08
1802#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x03
1803#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04
1804#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 0x02
1805#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02
1806#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01
1807#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01
1808#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00
1809
1810/* Bit definitions for NSLEEP_LDO_ASSIGN2 */
1811#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04
1812#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
1813#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02
1814#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 0x01
1815#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01
1816#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0x00
1817
1818/* Bit definitions for ENABLE1_RES_ASSIGN */
1819#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40
1820#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x06
1821#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20
1822#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
1823#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10
1824#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 0x04
1825#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08
1826#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 0x03
1827#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04
1828#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 0x02
1829#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02
1830#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01
1831#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01
1832#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00
1833
1834/* Bit definitions for ENABLE1_SMPS_ASSIGN */
1835#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80
1836#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 0x07
1837#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40
1838#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 0x06
1839#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20
1840#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 0x05
1841#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10
1842#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 0x04
1843#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08
1844#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 0x03
1845#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04
1846#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 0x02
1847#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02
1848#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x01
1849#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01
1850#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0x00
1851
1852/* Bit definitions for ENABLE1_LDO_ASSIGN1 */
1853#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80
1854#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 0x07
1855#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40
1856#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 0x06
1857#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20
1858#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 0x05
1859#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10
1860#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 0x04
1861#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08
1862#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x03
1863#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04
1864#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 0x02
1865#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02
1866#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01
1867#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01
1868#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00
1869
1870/* Bit definitions for ENABLE1_LDO_ASSIGN2 */
1871#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04
1872#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
1873#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02
1874#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 0x01
1875#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01
1876#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0x00
1877
1878/* Bit definitions for ENABLE2_RES_ASSIGN */
1879#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40
1880#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x06
1881#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20
1882#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
1883#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10
1884#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 0x04
1885#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08
1886#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 0x03
1887#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04
1888#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 0x02
1889#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02
1890#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01
1891#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01
1892#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00
1893
1894/* Bit definitions for ENABLE2_SMPS_ASSIGN */
1895#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80
1896#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 0x07
1897#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40
1898#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 0x06
1899#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20
1900#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 0x05
1901#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10
1902#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 0x04
1903#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08
1904#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 0x03
1905#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04
1906#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 0x02
1907#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02
1908#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x01
1909#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01
1910#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0x00
1911
1912/* Bit definitions for ENABLE2_LDO_ASSIGN1 */
1913#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80
1914#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 0x07
1915#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40
1916#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 0x06
1917#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20
1918#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 0x05
1919#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10
1920#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 0x04
1921#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08
1922#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x03
1923#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04
1924#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 0x02
1925#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02
1926#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01
1927#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01
1928#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00
1929
1930/* Bit definitions for ENABLE2_LDO_ASSIGN2 */
1931#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04
1932#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
1933#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02
1934#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 0x01
1935#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01
1936#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0x00
1937
1938/* Bit definitions for REGEN3_CTRL */
1939#define PALMAS_REGEN3_CTRL_STATUS 0x10
1940#define PALMAS_REGEN3_CTRL_STATUS_SHIFT 0x04
1941#define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04
1942#define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02
1943#define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01
1944#define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00
1945
1946/* Registers for function PAD_CONTROL */
1947#define PALMAS_OD_OUTPUT_CTRL2 0x02
1948#define PALMAS_POLARITY_CTRL2 0x03
1949#define PALMAS_PU_PD_INPUT_CTRL1 0x04
1950#define PALMAS_PU_PD_INPUT_CTRL2 0x05
1951#define PALMAS_PU_PD_INPUT_CTRL3 0x06
1952#define PALMAS_PU_PD_INPUT_CTRL5 0x07
1953#define PALMAS_OD_OUTPUT_CTRL 0x08
1954#define PALMAS_POLARITY_CTRL 0x09
1955#define PALMAS_PRIMARY_SECONDARY_PAD1 0x0A
1956#define PALMAS_PRIMARY_SECONDARY_PAD2 0x0B
1957#define PALMAS_I2C_SPI 0x0C
1958#define PALMAS_PU_PD_INPUT_CTRL4 0x0D
1959#define PALMAS_PRIMARY_SECONDARY_PAD3 0x0E
1960#define PALMAS_PRIMARY_SECONDARY_PAD4 0x0F
1961
1962/* Bit definitions for PU_PD_INPUT_CTRL1 */
1963#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40
1964#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 0x06
1965#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20
1966#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 0x05
1967#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10
1968#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 0x04
1969#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04
1970#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 0x02
1971#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02
1972#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 0x01
1973
1974/* Bit definitions for PU_PD_INPUT_CTRL2 */
1975#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20
1976#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 0x05
1977#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10
1978#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 0x04
1979#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08
1980#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 0x03
1981#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04
1982#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 0x02
1983#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02
1984#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 0x01
1985#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01
1986#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0x00
1987
1988/* Bit definitions for PU_PD_INPUT_CTRL3 */
1989#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40
1990#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 0x06
1991#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10
1992#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 0x04
1993#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04
1994#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 0x02
1995#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01
1996#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0x00
1997
1998/* Bit definitions for OD_OUTPUT_CTRL */
1999#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80
2000#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 0x07
2001#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40
2002#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 0x06
2003#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20
2004#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 0x05
2005#define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08
2006#define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 0x03
2007
2008/* Bit definitions for POLARITY_CTRL */
2009#define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80
2010#define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 0x07
2011#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40
2012#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 0x06
2013#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20
2014#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 0x05
2015#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10
2016#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 0x04
2017#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08
2018#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 0x03
2019#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04
2020#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 0x02
2021#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02
2022#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 0x01
2023#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01
2024#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0x00
2025
2026/* Bit definitions for PRIMARY_SECONDARY_PAD1 */
2027#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80
2028#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 0x07
2029#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60
2030#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 0x05
2031#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18
2032#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 0x03
2033#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04
2034#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 0x02
2035#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02
2036#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 0x01
2037#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01
2038#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0x00
2039
2040/* Bit definitions for PRIMARY_SECONDARY_PAD2 */
2041#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30
2042#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 0x04
2043#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08
2044#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 0x03
2045#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06
2046#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 0x01
2047#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01
2048#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0x00
2049
2050/* Bit definitions for I2C_SPI */
2051#define PALMAS_I2C_SPI_I2C2OTP_EN 0x80
2052#define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 0x07
2053#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40
2054#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 0x06
2055#define PALMAS_I2C_SPI_ID_I2C2 0x20
2056#define PALMAS_I2C_SPI_ID_I2C2_SHIFT 0x05
2057#define PALMAS_I2C_SPI_I2C_SPI 0x10
2058#define PALMAS_I2C_SPI_I2C_SPI_SHIFT 0x04
2059#define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0F
2060#define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0x00
2061
2062/* Bit definitions for PU_PD_INPUT_CTRL4 */
2063#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40
2064#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 0x06
2065#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10
2066#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 0x04
2067#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04
2068#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 0x02
2069#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01
2070#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0x00
2071
2072/* Bit definitions for PRIMARY_SECONDARY_PAD3 */
2073#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02
2074#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 0x01
2075#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01
2076#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0x00
2077
2078/* Registers for function LED_PWM */
2079#define PALMAS_LED_PERIOD_CTRL 0x00
2080#define PALMAS_LED_CTRL 0x01
2081#define PALMAS_PWM_CTRL1 0x02
2082#define PALMAS_PWM_CTRL2 0x03
2083
2084/* Bit definitions for LED_PERIOD_CTRL */
2085#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38
2086#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 0x03
2087#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07
2088#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0x00
2089
2090/* Bit definitions for LED_CTRL */
2091#define PALMAS_LED_CTRL_LED_2_SEQ 0x20
2092#define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 0x05
2093#define PALMAS_LED_CTRL_LED_1_SEQ 0x10
2094#define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 0x04
2095#define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c
2096#define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 0x02
2097#define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03
2098#define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0x00
2099
2100/* Bit definitions for PWM_CTRL1 */
2101#define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02
2102#define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 0x01
2103#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01
2104#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0x00
2105
2106/* Bit definitions for PWM_CTRL2 */
2107#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xFF
2108#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0x00
2109
2110/* Registers for function INTERRUPT */
2111#define PALMAS_INT1_STATUS 0x00
2112#define PALMAS_INT1_MASK 0x01
2113#define PALMAS_INT1_LINE_STATE 0x02
2114#define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x03
2115#define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x04
2116#define PALMAS_INT2_STATUS 0x05
2117#define PALMAS_INT2_MASK 0x06
2118#define PALMAS_INT2_LINE_STATE 0x07
2119#define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x08
2120#define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x09
2121#define PALMAS_INT3_STATUS 0x0A
2122#define PALMAS_INT3_MASK 0x0B
2123#define PALMAS_INT3_LINE_STATE 0x0C
2124#define PALMAS_INT3_EDGE_DETECT1_RESERVED 0x0D
2125#define PALMAS_INT3_EDGE_DETECT2_RESERVED 0x0E
2126#define PALMAS_INT4_STATUS 0x0F
2127#define PALMAS_INT4_MASK 0x10
2128#define PALMAS_INT4_LINE_STATE 0x11
2129#define PALMAS_INT4_EDGE_DETECT1 0x12
2130#define PALMAS_INT4_EDGE_DETECT2 0x13
2131#define PALMAS_INT_CTRL 0x14
2132
2133/* Bit definitions for INT1_STATUS */
2134#define PALMAS_INT1_STATUS_VBAT_MON 0x80
2135#define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 0x07
2136#define PALMAS_INT1_STATUS_VSYS_MON 0x40
2137#define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 0x06
2138#define PALMAS_INT1_STATUS_HOTDIE 0x20
2139#define PALMAS_INT1_STATUS_HOTDIE_SHIFT 0x05
2140#define PALMAS_INT1_STATUS_PWRDOWN 0x10
2141#define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 0x04
2142#define PALMAS_INT1_STATUS_RPWRON 0x08
2143#define PALMAS_INT1_STATUS_RPWRON_SHIFT 0x03
2144#define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04
2145#define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02
2146#define PALMAS_INT1_STATUS_PWRON 0x02
2147#define PALMAS_INT1_STATUS_PWRON_SHIFT 0x01
2148#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01
2149#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2150
2151/* Bit definitions for INT1_MASK */
2152#define PALMAS_INT1_MASK_VBAT_MON 0x80
2153#define PALMAS_INT1_MASK_VBAT_MON_SHIFT 0x07
2154#define PALMAS_INT1_MASK_VSYS_MON 0x40
2155#define PALMAS_INT1_MASK_VSYS_MON_SHIFT 0x06
2156#define PALMAS_INT1_MASK_HOTDIE 0x20
2157#define PALMAS_INT1_MASK_HOTDIE_SHIFT 0x05
2158#define PALMAS_INT1_MASK_PWRDOWN 0x10
2159#define PALMAS_INT1_MASK_PWRDOWN_SHIFT 0x04
2160#define PALMAS_INT1_MASK_RPWRON 0x08
2161#define PALMAS_INT1_MASK_RPWRON_SHIFT 0x03
2162#define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04
2163#define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02
2164#define PALMAS_INT1_MASK_PWRON 0x02
2165#define PALMAS_INT1_MASK_PWRON_SHIFT 0x01
2166#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01
2167#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2168
2169/* Bit definitions for INT1_LINE_STATE */
2170#define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80
2171#define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 0x07
2172#define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40
2173#define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06
2174#define PALMAS_INT1_LINE_STATE_HOTDIE 0x20
2175#define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 0x05
2176#define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10
2177#define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04
2178#define PALMAS_INT1_LINE_STATE_RPWRON 0x08
2179#define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 0x03
2180#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
2181#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02
2182#define PALMAS_INT1_LINE_STATE_PWRON 0x02
2183#define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 0x01
2184#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01
2185#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2186
2187/* Bit definitions for INT2_STATUS */
2188#define PALMAS_INT2_STATUS_VAC_ACOK 0x80
2189#define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 0x07
2190#define PALMAS_INT2_STATUS_SHORT 0x40
2191#define PALMAS_INT2_STATUS_SHORT_SHIFT 0x06
2192#define PALMAS_INT2_STATUS_FBI_BB 0x20
2193#define PALMAS_INT2_STATUS_FBI_BB_SHIFT 0x05
2194#define PALMAS_INT2_STATUS_RESET_IN 0x10
2195#define PALMAS_INT2_STATUS_RESET_IN_SHIFT 0x04
2196#define PALMAS_INT2_STATUS_BATREMOVAL 0x08
2197#define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 0x03
2198#define PALMAS_INT2_STATUS_WDT 0x04
2199#define PALMAS_INT2_STATUS_WDT_SHIFT 0x02
2200#define PALMAS_INT2_STATUS_RTC_TIMER 0x02
2201#define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 0x01
2202#define PALMAS_INT2_STATUS_RTC_ALARM 0x01
2203#define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0x00
2204
2205/* Bit definitions for INT2_MASK */
2206#define PALMAS_INT2_MASK_VAC_ACOK 0x80
2207#define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 0x07
2208#define PALMAS_INT2_MASK_SHORT 0x40
2209#define PALMAS_INT2_MASK_SHORT_SHIFT 0x06
2210#define PALMAS_INT2_MASK_FBI_BB 0x20
2211#define PALMAS_INT2_MASK_FBI_BB_SHIFT 0x05
2212#define PALMAS_INT2_MASK_RESET_IN 0x10
2213#define PALMAS_INT2_MASK_RESET_IN_SHIFT 0x04
2214#define PALMAS_INT2_MASK_BATREMOVAL 0x08
2215#define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 0x03
2216#define PALMAS_INT2_MASK_WDT 0x04
2217#define PALMAS_INT2_MASK_WDT_SHIFT 0x02
2218#define PALMAS_INT2_MASK_RTC_TIMER 0x02
2219#define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 0x01
2220#define PALMAS_INT2_MASK_RTC_ALARM 0x01
2221#define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0x00
2222
2223/* Bit definitions for INT2_LINE_STATE */
2224#define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80
2225#define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 0x07
2226#define PALMAS_INT2_LINE_STATE_SHORT 0x40
2227#define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 0x06
2228#define PALMAS_INT2_LINE_STATE_FBI_BB 0x20
2229#define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 0x05
2230#define PALMAS_INT2_LINE_STATE_RESET_IN 0x10
2231#define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 0x04
2232#define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08
2233#define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 0x03
2234#define PALMAS_INT2_LINE_STATE_WDT 0x04
2235#define PALMAS_INT2_LINE_STATE_WDT_SHIFT 0x02
2236#define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02
2237#define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 0x01
2238#define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01
2239#define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0x00
2240
2241/* Bit definitions for INT3_STATUS */
2242#define PALMAS_INT3_STATUS_VBUS 0x80
2243#define PALMAS_INT3_STATUS_VBUS_SHIFT 0x07
2244#define PALMAS_INT3_STATUS_VBUS_OTG 0x40
2245#define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 0x06
2246#define PALMAS_INT3_STATUS_ID 0x20
2247#define PALMAS_INT3_STATUS_ID_SHIFT 0x05
2248#define PALMAS_INT3_STATUS_ID_OTG 0x10
2249#define PALMAS_INT3_STATUS_ID_OTG_SHIFT 0x04
2250#define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08
2251#define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 0x03
2252#define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04
2253#define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02
2254#define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02
2255#define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01
2256#define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01
2257#define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00
2258
2259/* Bit definitions for INT3_MASK */
2260#define PALMAS_INT3_MASK_VBUS 0x80
2261#define PALMAS_INT3_MASK_VBUS_SHIFT 0x07
2262#define PALMAS_INT3_MASK_VBUS_OTG 0x40
2263#define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 0x06
2264#define PALMAS_INT3_MASK_ID 0x20
2265#define PALMAS_INT3_MASK_ID_SHIFT 0x05
2266#define PALMAS_INT3_MASK_ID_OTG 0x10
2267#define PALMAS_INT3_MASK_ID_OTG_SHIFT 0x04
2268#define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08
2269#define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 0x03
2270#define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04
2271#define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02
2272#define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02
2273#define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01
2274#define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01
2275#define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00
2276
2277/* Bit definitions for INT3_LINE_STATE */
2278#define PALMAS_INT3_LINE_STATE_VBUS 0x80
2279#define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 0x07
2280#define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40
2281#define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 0x06
2282#define PALMAS_INT3_LINE_STATE_ID 0x20
2283#define PALMAS_INT3_LINE_STATE_ID_SHIFT 0x05
2284#define PALMAS_INT3_LINE_STATE_ID_OTG 0x10
2285#define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 0x04
2286#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08
2287#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 0x03
2288#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04
2289#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02
2290#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02
2291#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01
2292#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01
2293#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00
2294
2295/* Bit definitions for INT4_STATUS */
2296#define PALMAS_INT4_STATUS_GPIO_7 0x80
2297#define PALMAS_INT4_STATUS_GPIO_7_SHIFT 0x07
2298#define PALMAS_INT4_STATUS_GPIO_6 0x40
2299#define PALMAS_INT4_STATUS_GPIO_6_SHIFT 0x06
2300#define PALMAS_INT4_STATUS_GPIO_5 0x20
2301#define PALMAS_INT4_STATUS_GPIO_5_SHIFT 0x05
2302#define PALMAS_INT4_STATUS_GPIO_4 0x10
2303#define PALMAS_INT4_STATUS_GPIO_4_SHIFT 0x04
2304#define PALMAS_INT4_STATUS_GPIO_3 0x08
2305#define PALMAS_INT4_STATUS_GPIO_3_SHIFT 0x03
2306#define PALMAS_INT4_STATUS_GPIO_2 0x04
2307#define PALMAS_INT4_STATUS_GPIO_2_SHIFT 0x02
2308#define PALMAS_INT4_STATUS_GPIO_1 0x02
2309#define PALMAS_INT4_STATUS_GPIO_1_SHIFT 0x01
2310#define PALMAS_INT4_STATUS_GPIO_0 0x01
2311#define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0x00
2312
2313/* Bit definitions for INT4_MASK */
2314#define PALMAS_INT4_MASK_GPIO_7 0x80
2315#define PALMAS_INT4_MASK_GPIO_7_SHIFT 0x07
2316#define PALMAS_INT4_MASK_GPIO_6 0x40
2317#define PALMAS_INT4_MASK_GPIO_6_SHIFT 0x06
2318#define PALMAS_INT4_MASK_GPIO_5 0x20
2319#define PALMAS_INT4_MASK_GPIO_5_SHIFT 0x05
2320#define PALMAS_INT4_MASK_GPIO_4 0x10
2321#define PALMAS_INT4_MASK_GPIO_4_SHIFT 0x04
2322#define PALMAS_INT4_MASK_GPIO_3 0x08
2323#define PALMAS_INT4_MASK_GPIO_3_SHIFT 0x03
2324#define PALMAS_INT4_MASK_GPIO_2 0x04
2325#define PALMAS_INT4_MASK_GPIO_2_SHIFT 0x02
2326#define PALMAS_INT4_MASK_GPIO_1 0x02
2327#define PALMAS_INT4_MASK_GPIO_1_SHIFT 0x01
2328#define PALMAS_INT4_MASK_GPIO_0 0x01
2329#define PALMAS_INT4_MASK_GPIO_0_SHIFT 0x00
2330
2331/* Bit definitions for INT4_LINE_STATE */
2332#define PALMAS_INT4_LINE_STATE_GPIO_7 0x80
2333#define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 0x07
2334#define PALMAS_INT4_LINE_STATE_GPIO_6 0x40
2335#define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 0x06
2336#define PALMAS_INT4_LINE_STATE_GPIO_5 0x20
2337#define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 0x05
2338#define PALMAS_INT4_LINE_STATE_GPIO_4 0x10
2339#define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 0x04
2340#define PALMAS_INT4_LINE_STATE_GPIO_3 0x08
2341#define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 0x03
2342#define PALMAS_INT4_LINE_STATE_GPIO_2 0x04
2343#define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 0x02
2344#define PALMAS_INT4_LINE_STATE_GPIO_1 0x02
2345#define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 0x01
2346#define PALMAS_INT4_LINE_STATE_GPIO_0 0x01
2347#define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0x00
2348
2349/* Bit definitions for INT4_EDGE_DETECT1 */
2350#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
2351#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07
2352#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
2353#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06
2354#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
2355#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05
2356#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
2357#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04
2358#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
2359#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03
2360#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
2361#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02
2362#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
2363#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01
2364#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
2365#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00
2366
2367/* Bit definitions for INT4_EDGE_DETECT2 */
2368#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80
2369#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 0x07
2370#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40
2371#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 0x06
2372#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
2373#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05
2374#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
2375#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04
2376#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
2377#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03
2378#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
2379#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02
2380#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
2381#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01
2382#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
2383#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00
2384
2385/* Bit definitions for INT_CTRL */
2386#define PALMAS_INT_CTRL_INT_PENDING 0x04
2387#define PALMAS_INT_CTRL_INT_PENDING_SHIFT 0x02
2388#define PALMAS_INT_CTRL_INT_CLEAR 0x01
2389#define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0x00
2390
2391/* Registers for function USB_OTG */
2392#define PALMAS_USB_WAKEUP 0x03
2393#define PALMAS_USB_VBUS_CTRL_SET 0x04
2394#define PALMAS_USB_VBUS_CTRL_CLR 0x05
2395#define PALMAS_USB_ID_CTRL_SET 0x06
2396#define PALMAS_USB_ID_CTRL_CLEAR 0x07
2397#define PALMAS_USB_VBUS_INT_SRC 0x08
2398#define PALMAS_USB_VBUS_INT_LATCH_SET 0x09
2399#define PALMAS_USB_VBUS_INT_LATCH_CLR 0x0A
2400#define PALMAS_USB_VBUS_INT_EN_LO_SET 0x0B
2401#define PALMAS_USB_VBUS_INT_EN_LO_CLR 0x0C
2402#define PALMAS_USB_VBUS_INT_EN_HI_SET 0x0D
2403#define PALMAS_USB_VBUS_INT_EN_HI_CLR 0x0E
2404#define PALMAS_USB_ID_INT_SRC 0x0F
2405#define PALMAS_USB_ID_INT_LATCH_SET 0x10
2406#define PALMAS_USB_ID_INT_LATCH_CLR 0x11
2407#define PALMAS_USB_ID_INT_EN_LO_SET 0x12
2408#define PALMAS_USB_ID_INT_EN_LO_CLR 0x13
2409#define PALMAS_USB_ID_INT_EN_HI_SET 0x14
2410#define PALMAS_USB_ID_INT_EN_HI_CLR 0x15
2411#define PALMAS_USB_OTG_ADP_CTRL 0x16
2412#define PALMAS_USB_OTG_ADP_HIGH 0x17
2413#define PALMAS_USB_OTG_ADP_LOW 0x18
2414#define PALMAS_USB_OTG_ADP_RISE 0x19
2415#define PALMAS_USB_OTG_REVISION 0x1A
2416
2417/* Bit definitions for USB_WAKEUP */
2418#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01
2419#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0x00
2420
2421/* Bit definitions for USB_VBUS_CTRL_SET */
2422#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80
2423#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 0x07
2424#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20
2425#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 0x05
2426#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10
2427#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 0x04
2428#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08
2429#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 0x03
2430#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04
2431#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 0x02
2432
2433/* Bit definitions for USB_VBUS_CTRL_CLR */
2434#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80
2435#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 0x07
2436#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20
2437#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 0x05
2438#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10
2439#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 0x04
2440#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08
2441#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 0x03
2442#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04
2443#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 0x02
2444
2445/* Bit definitions for USB_ID_CTRL_SET */
2446#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80
2447#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 0x07
2448#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40
2449#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 0x06
2450#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20
2451#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 0x05
2452#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10
2453#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 0x04
2454#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08
2455#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 0x03
2456#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04
2457#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 0x02
2458
2459/* Bit definitions for USB_ID_CTRL_CLEAR */
2460#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80
2461#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 0x07
2462#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40
2463#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 0x06
2464#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20
2465#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 0x05
2466#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10
2467#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 0x04
2468#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08
2469#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 0x03
2470#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04
2471#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 0x02
2472
2473/* Bit definitions for USB_VBUS_INT_SRC */
2474#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80
2475#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 0x07
2476#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40
2477#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 0x06
2478#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20
2479#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 0x05
2480#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08
2481#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 0x03
2482#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04
2483#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 0x02
2484#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02
2485#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 0x01
2486#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01
2487#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0x00
2488
2489/* Bit definitions for USB_VBUS_INT_LATCH_SET */
2490#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80
2491#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 0x07
2492#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40
2493#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 0x06
2494#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20
2495#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 0x05
2496#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10
2497#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 0x04
2498#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08
2499#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 0x03
2500#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04
2501#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 0x02
2502#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02
2503#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 0x01
2504#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01
2505#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0x00
2506
2507/* Bit definitions for USB_VBUS_INT_LATCH_CLR */
2508#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80
2509#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 0x07
2510#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40
2511#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 0x06
2512#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20
2513#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 0x05
2514#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10
2515#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 0x04
2516#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08
2517#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 0x03
2518#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04
2519#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 0x02
2520#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02
2521#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 0x01
2522#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01
2523#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0x00
2524
2525/* Bit definitions for USB_VBUS_INT_EN_LO_SET */
2526#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80
2527#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 0x07
2528#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40
2529#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 0x06
2530#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20
2531#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 0x05
2532#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08
2533#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 0x03
2534#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04
2535#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 0x02
2536#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02
2537#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 0x01
2538#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01
2539#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0x00
2540
2541/* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
2542#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80
2543#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 0x07
2544#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40
2545#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 0x06
2546#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20
2547#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 0x05
2548#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08
2549#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 0x03
2550#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04
2551#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 0x02
2552#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02
2553#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 0x01
2554#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01
2555#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0x00
2556
2557/* Bit definitions for USB_VBUS_INT_EN_HI_SET */
2558#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80
2559#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 0x07
2560#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40
2561#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 0x06
2562#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20
2563#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 0x05
2564#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10
2565#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 0x04
2566#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08
2567#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 0x03
2568#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04
2569#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 0x02
2570#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02
2571#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 0x01
2572#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01
2573#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0x00
2574
2575/* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
2576#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80
2577#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 0x07
2578#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40
2579#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 0x06
2580#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20
2581#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 0x05
2582#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10
2583#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 0x04
2584#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08
2585#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 0x03
2586#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04
2587#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 0x02
2588#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02
2589#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 0x01
2590#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01
2591#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0x00
2592
2593/* Bit definitions for USB_ID_INT_SRC */
2594#define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10
2595#define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 0x04
2596#define PALMAS_USB_ID_INT_SRC_ID_A 0x08
2597#define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 0x03
2598#define PALMAS_USB_ID_INT_SRC_ID_B 0x04
2599#define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 0x02
2600#define PALMAS_USB_ID_INT_SRC_ID_C 0x02
2601#define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 0x01
2602#define PALMAS_USB_ID_INT_SRC_ID_GND 0x01
2603#define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0x00
2604
2605/* Bit definitions for USB_ID_INT_LATCH_SET */
2606#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10
2607#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 0x04
2608#define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08
2609#define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 0x03
2610#define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04
2611#define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 0x02
2612#define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02
2613#define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 0x01
2614#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01
2615#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0x00
2616
2617/* Bit definitions for USB_ID_INT_LATCH_CLR */
2618#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10
2619#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 0x04
2620#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08
2621#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 0x03
2622#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04
2623#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 0x02
2624#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02
2625#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 0x01
2626#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01
2627#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0x00
2628
2629/* Bit definitions for USB_ID_INT_EN_LO_SET */
2630#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10
2631#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 0x04
2632#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08
2633#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 0x03
2634#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04
2635#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 0x02
2636#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02
2637#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 0x01
2638#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01
2639#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0x00
2640
2641/* Bit definitions for USB_ID_INT_EN_LO_CLR */
2642#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10
2643#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 0x04
2644#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08
2645#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 0x03
2646#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04
2647#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 0x02
2648#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02
2649#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 0x01
2650#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01
2651#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0x00
2652
2653/* Bit definitions for USB_ID_INT_EN_HI_SET */
2654#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10
2655#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 0x04
2656#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08
2657#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 0x03
2658#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04
2659#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 0x02
2660#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02
2661#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 0x01
2662#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01
2663#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0x00
2664
2665/* Bit definitions for USB_ID_INT_EN_HI_CLR */
2666#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10
2667#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 0x04
2668#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08
2669#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 0x03
2670#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04
2671#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 0x02
2672#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02
2673#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 0x01
2674#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01
2675#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0x00
2676
2677/* Bit definitions for USB_OTG_ADP_CTRL */
2678#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04
2679#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 0x02
2680#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03
2681#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0x00
2682
2683/* Bit definitions for USB_OTG_ADP_HIGH */
2684#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xFF
2685#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0x00
2686
2687/* Bit definitions for USB_OTG_ADP_LOW */
2688#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xFF
2689#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0x00
2690
2691/* Bit definitions for USB_OTG_ADP_RISE */
2692#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xFF
2693#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0x00
2694
2695/* Bit definitions for USB_OTG_REVISION */
2696#define PALMAS_USB_OTG_REVISION_OTG_REV 0x01
2697#define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0x00
2698
2699/* Registers for function VIBRATOR */
2700#define PALMAS_VIBRA_CTRL 0x00
2701
2702/* Bit definitions for VIBRA_CTRL */
2703#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06
2704#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 0x01
2705#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01
2706#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0x00
2707
2708/* Registers for function GPIO */
2709#define PALMAS_GPIO_DATA_IN 0x00
2710#define PALMAS_GPIO_DATA_DIR 0x01
2711#define PALMAS_GPIO_DATA_OUT 0x02
2712#define PALMAS_GPIO_DEBOUNCE_EN 0x03
2713#define PALMAS_GPIO_CLEAR_DATA_OUT 0x04
2714#define PALMAS_GPIO_SET_DATA_OUT 0x05
2715#define PALMAS_PU_PD_GPIO_CTRL1 0x06
2716#define PALMAS_PU_PD_GPIO_CTRL2 0x07
2717#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x08
2718#define PALMAS_GPIO_DATA_IN2 0x09
2719#define PALMAS_GPIO_DATA_DIR2 0x0A
2720#define PALMAS_GPIO_DATA_OUT2 0x0B
2721#define PALMAS_GPIO_DEBOUNCE_EN2 0x0C
2722#define PALMAS_GPIO_CLEAR_DATA_OUT2 0x0D
2723#define PALMAS_GPIO_SET_DATA_OUT2 0x0E
2724#define PALMAS_PU_PD_GPIO_CTRL3 0x0F
2725#define PALMAS_PU_PD_GPIO_CTRL4 0x10
2726#define PALMAS_OD_OUTPUT_GPIO_CTRL2 0x11
2727
2728/* Bit definitions for GPIO_DATA_IN */
2729#define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80
2730#define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 0x07
2731#define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40
2732#define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 0x06
2733#define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20
2734#define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 0x05
2735#define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10
2736#define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 0x04
2737#define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08
2738#define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 0x03
2739#define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04
2740#define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 0x02
2741#define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02
2742#define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 0x01
2743#define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01
2744#define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0x00
2745
2746/* Bit definitions for GPIO_DATA_DIR */
2747#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80
2748#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 0x07
2749#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40
2750#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 0x06
2751#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20
2752#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 0x05
2753#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10
2754#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 0x04
2755#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08
2756#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 0x03
2757#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04
2758#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 0x02
2759#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02
2760#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 0x01
2761#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01
2762#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0x00
2763
2764/* Bit definitions for GPIO_DATA_OUT */
2765#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80
2766#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 0x07
2767#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40
2768#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 0x06
2769#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20
2770#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 0x05
2771#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10
2772#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 0x04
2773#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08
2774#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 0x03
2775#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04
2776#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 0x02
2777#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02
2778#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 0x01
2779#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01
2780#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0x00
2781
2782/* Bit definitions for GPIO_DEBOUNCE_EN */
2783#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80
2784#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 0x07
2785#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40
2786#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 0x06
2787#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20
2788#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 0x05
2789#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10
2790#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 0x04
2791#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08
2792#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 0x03
2793#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04
2794#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 0x02
2795#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02
2796#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 0x01
2797#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01
2798#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0x00
2799
2800/* Bit definitions for GPIO_CLEAR_DATA_OUT */
2801#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80
2802#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 0x07
2803#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40
2804#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 0x06
2805#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20
2806#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 0x05
2807#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10
2808#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 0x04
2809#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08
2810#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 0x03
2811#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04
2812#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 0x02
2813#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02
2814#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 0x01
2815#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01
2816#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0x00
2817
2818/* Bit definitions for GPIO_SET_DATA_OUT */
2819#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80
2820#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 0x07
2821#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40
2822#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 0x06
2823#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20
2824#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 0x05
2825#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10
2826#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 0x04
2827#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08
2828#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 0x03
2829#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04
2830#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 0x02
2831#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02
2832#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 0x01
2833#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01
2834#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0x00
2835
2836/* Bit definitions for PU_PD_GPIO_CTRL1 */
2837#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40
2838#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 0x06
2839#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20
2840#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 0x05
2841#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10
2842#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 0x04
2843#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08
2844#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 0x03
2845#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04
2846#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 0x02
2847#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01
2848#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0x00
2849
2850/* Bit definitions for PU_PD_GPIO_CTRL2 */
2851#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40
2852#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 0x06
2853#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20
2854#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 0x05
2855#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10
2856#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 0x04
2857#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08
2858#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 0x03
2859#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04
2860#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 0x02
2861#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02
2862#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 0x01
2863#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01
2864#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0x00
2865
2866/* Bit definitions for OD_OUTPUT_GPIO_CTRL */
2867#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20
2868#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 0x05
2869#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04
2870#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 0x02
2871#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02
2872#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 0x01
2873
2874/* Registers for function GPADC */
2875#define PALMAS_GPADC_CTRL1 0x00
2876#define PALMAS_GPADC_CTRL2 0x01
2877#define PALMAS_GPADC_RT_CTRL 0x02
2878#define PALMAS_GPADC_AUTO_CTRL 0x03
2879#define PALMAS_GPADC_STATUS 0x04
2880#define PALMAS_GPADC_RT_SELECT 0x05
2881#define PALMAS_GPADC_RT_CONV0_LSB 0x06
2882#define PALMAS_GPADC_RT_CONV0_MSB 0x07
2883#define PALMAS_GPADC_AUTO_SELECT 0x08
2884#define PALMAS_GPADC_AUTO_CONV0_LSB 0x09
2885#define PALMAS_GPADC_AUTO_CONV0_MSB 0x0A
2886#define PALMAS_GPADC_AUTO_CONV1_LSB 0x0B
2887#define PALMAS_GPADC_AUTO_CONV1_MSB 0x0C
2888#define PALMAS_GPADC_SW_SELECT 0x0D
2889#define PALMAS_GPADC_SW_CONV0_LSB 0x0E
2890#define PALMAS_GPADC_SW_CONV0_MSB 0x0F
2891#define PALMAS_GPADC_THRES_CONV0_LSB 0x10
2892#define PALMAS_GPADC_THRES_CONV0_MSB 0x11
2893#define PALMAS_GPADC_THRES_CONV1_LSB 0x12
2894#define PALMAS_GPADC_THRES_CONV1_MSB 0x13
2895#define PALMAS_GPADC_SMPS_ILMONITOR_EN 0x14
2896#define PALMAS_GPADC_SMPS_VSEL_MONITORING 0x15
2897
2898/* Bit definitions for GPADC_CTRL1 */
2899#define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0
2900#define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 0x06
2901#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30
2902#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 0x04
2903#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c
2904#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 0x02
2905#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02
2906#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 0x01
2907#define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01
2908#define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0x00
2909
2910/* Bit definitions for GPADC_CTRL2 */
2911#define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06
2912#define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 0x01
2913
2914/* Bit definitions for GPADC_RT_CTRL */
2915#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02
2916#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 0x01
2917#define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01
2918#define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0x00
2919
2920/* Bit definitions for GPADC_AUTO_CTRL */
2921#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80
2922#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 0x07
2923#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40
2924#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 0x06
2925#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20
2926#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 0x05
2927#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10
2928#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 0x04
2929#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0F
2930#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0x00
2931
2932/* Bit definitions for GPADC_STATUS */
2933#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10
2934#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 0x04
2935
2936/* Bit definitions for GPADC_RT_SELECT */
2937#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80
2938#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 0x07
2939#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0F
2940#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0x00
2941
2942/* Bit definitions for GPADC_RT_CONV0_LSB */
2943#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xFF
2944#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0x00
2945
2946/* Bit definitions for GPADC_RT_CONV0_MSB */
2947#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0F
2948#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0x00
2949
2950/* Bit definitions for GPADC_AUTO_SELECT */
2951#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xF0
2952#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 0x04
2953#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0F
2954#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0x00
2955
2956/* Bit definitions for GPADC_AUTO_CONV0_LSB */
2957#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xFF
2958#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0x00
2959
2960/* Bit definitions for GPADC_AUTO_CONV0_MSB */
2961#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0F
2962#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0x00
2963
2964/* Bit definitions for GPADC_AUTO_CONV1_LSB */
2965#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xFF
2966#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0x00
2967
2968/* Bit definitions for GPADC_AUTO_CONV1_MSB */
2969#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0F
2970#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0x00
2971
2972/* Bit definitions for GPADC_SW_SELECT */
2973#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80
2974#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 0x07
2975#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10
2976#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 0x04
2977#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0F
2978#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0x00
2979
2980/* Bit definitions for GPADC_SW_CONV0_LSB */
2981#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xFF
2982#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0x00
2983
2984/* Bit definitions for GPADC_SW_CONV0_MSB */
2985#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0F
2986#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0x00
2987
2988/* Bit definitions for GPADC_THRES_CONV0_LSB */
2989#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xFF
2990#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0x00
2991
2992/* Bit definitions for GPADC_THRES_CONV0_MSB */
2993#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80
2994#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 0x07
2995#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0F
2996#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0x00
2997
2998/* Bit definitions for GPADC_THRES_CONV1_LSB */
2999#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xFF
3000#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0x00
3001
3002/* Bit definitions for GPADC_THRES_CONV1_MSB */
3003#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80
3004#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 0x07
3005#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0F
3006#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0x00
3007
3008/* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
3009#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20
3010#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 0x05
3011#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10
3012#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 0x04
3013#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0F
3014#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0x00
3015
3016/* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
3017#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80
3018#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 0x07
3019#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7F
3020#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0x00
3021
3022/* Registers for function GPADC */
3023#define PALMAS_GPADC_TRIM1 0x00
3024#define PALMAS_GPADC_TRIM2 0x01
3025#define PALMAS_GPADC_TRIM3 0x02
3026#define PALMAS_GPADC_TRIM4 0x03
3027#define PALMAS_GPADC_TRIM5 0x04
3028#define PALMAS_GPADC_TRIM6 0x05
3029#define PALMAS_GPADC_TRIM7 0x06
3030#define PALMAS_GPADC_TRIM8 0x07
3031#define PALMAS_GPADC_TRIM9 0x08
3032#define PALMAS_GPADC_TRIM10 0x09
3033#define PALMAS_GPADC_TRIM11 0x0A
3034#define PALMAS_GPADC_TRIM12 0x0B
3035#define PALMAS_GPADC_TRIM13 0x0C
3036#define PALMAS_GPADC_TRIM14 0x0D
3037#define PALMAS_GPADC_TRIM15 0x0E
3038#define PALMAS_GPADC_TRIM16 0x0F
3039
3040/* TPS659038 regen2_ctrl offset iss different from palmas */
3041#define TPS659038_REGEN2_CTRL 0x12
3042
3043/* TPS65917 Interrupt registers */
3044
3045/* Registers for function INTERRUPT */
3046#define TPS65917_INT1_STATUS 0x00
3047#define TPS65917_INT1_MASK 0x01
3048#define TPS65917_INT1_LINE_STATE 0x02
3049#define TPS65917_INT2_STATUS 0x05
3050#define TPS65917_INT2_MASK 0x06
3051#define TPS65917_INT2_LINE_STATE 0x07
3052#define TPS65917_INT3_STATUS 0x0A
3053#define TPS65917_INT3_MASK 0x0B
3054#define TPS65917_INT3_LINE_STATE 0x0C
3055#define TPS65917_INT4_STATUS 0x0F
3056#define TPS65917_INT4_MASK 0x10
3057#define TPS65917_INT4_LINE_STATE 0x11
3058#define TPS65917_INT4_EDGE_DETECT1 0x12
3059#define TPS65917_INT4_EDGE_DETECT2 0x13
3060#define TPS65917_INT_CTRL 0x14
3061
3062/* Bit definitions for INT1_STATUS */
3063#define TPS65917_INT1_STATUS_VSYS_MON 0x40
3064#define TPS65917_INT1_STATUS_VSYS_MON_SHIFT 0x06
3065#define TPS65917_INT1_STATUS_HOTDIE 0x20
3066#define TPS65917_INT1_STATUS_HOTDIE_SHIFT 0x05
3067#define TPS65917_INT1_STATUS_PWRDOWN 0x10
3068#define TPS65917_INT1_STATUS_PWRDOWN_SHIFT 0x04
3069#define TPS65917_INT1_STATUS_LONG_PRESS_KEY 0x04
3070#define TPS65917_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02
3071#define TPS65917_INT1_STATUS_PWRON 0x02
3072#define TPS65917_INT1_STATUS_PWRON_SHIFT 0x01
3073
3074/* Bit definitions for INT1_MASK */
3075#define TPS65917_INT1_MASK_VSYS_MON 0x40
3076#define TPS65917_INT1_MASK_VSYS_MON_SHIFT 0x06
3077#define TPS65917_INT1_MASK_HOTDIE 0x20
3078#define TPS65917_INT1_MASK_HOTDIE_SHIFT 0x05
3079#define TPS65917_INT1_MASK_PWRDOWN 0x10
3080#define TPS65917_INT1_MASK_PWRDOWN_SHIFT 0x04
3081#define TPS65917_INT1_MASK_LONG_PRESS_KEY 0x04
3082#define TPS65917_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02
3083#define TPS65917_INT1_MASK_PWRON 0x02
3084#define TPS65917_INT1_MASK_PWRON_SHIFT 0x01
3085
3086/* Bit definitions for INT1_LINE_STATE */
3087#define TPS65917_INT1_LINE_STATE_VSYS_MON 0x40
3088#define TPS65917_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06
3089#define TPS65917_INT1_LINE_STATE_HOTDIE 0x20
3090#define TPS65917_INT1_LINE_STATE_HOTDIE_SHIFT 0x05
3091#define TPS65917_INT1_LINE_STATE_PWRDOWN 0x10
3092#define TPS65917_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04
3093#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
3094#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02
3095#define TPS65917_INT1_LINE_STATE_PWRON 0x02
3096#define TPS65917_INT1_LINE_STATE_PWRON_SHIFT 0x01
3097
3098/* Bit definitions for INT2_STATUS */
3099#define TPS65917_INT2_STATUS_SHORT 0x40
3100#define TPS65917_INT2_STATUS_SHORT_SHIFT 0x06
3101#define TPS65917_INT2_STATUS_FSD 0x20
3102#define TPS65917_INT2_STATUS_FSD_SHIFT 0x05
3103#define TPS65917_INT2_STATUS_RESET_IN 0x10
3104#define TPS65917_INT2_STATUS_RESET_IN_SHIFT 0x04
3105#define TPS65917_INT2_STATUS_WDT 0x04
3106#define TPS65917_INT2_STATUS_WDT_SHIFT 0x02
3107#define TPS65917_INT2_STATUS_OTP_ERROR 0x02
3108#define TPS65917_INT2_STATUS_OTP_ERROR_SHIFT 0x01
3109
3110/* Bit definitions for INT2_MASK */
3111#define TPS65917_INT2_MASK_SHORT 0x40
3112#define TPS65917_INT2_MASK_SHORT_SHIFT 0x06
3113#define TPS65917_INT2_MASK_FSD 0x20
3114#define TPS65917_INT2_MASK_FSD_SHIFT 0x05
3115#define TPS65917_INT2_MASK_RESET_IN 0x10
3116#define TPS65917_INT2_MASK_RESET_IN_SHIFT 0x04
3117#define TPS65917_INT2_MASK_WDT 0x04
3118#define TPS65917_INT2_MASK_WDT_SHIFT 0x02
3119#define TPS65917_INT2_MASK_OTP_ERROR_TIMER 0x02
3120#define TPS65917_INT2_MASK_OTP_ERROR_SHIFT 0x01
3121
3122/* Bit definitions for INT2_LINE_STATE */
3123#define TPS65917_INT2_LINE_STATE_SHORT 0x40
3124#define TPS65917_INT2_LINE_STATE_SHORT_SHIFT 0x06
3125#define TPS65917_INT2_LINE_STATE_FSD 0x20
3126#define TPS65917_INT2_LINE_STATE_FSD_SHIFT 0x05
3127#define TPS65917_INT2_LINE_STATE_RESET_IN 0x10
3128#define TPS65917_INT2_LINE_STATE_RESET_IN_SHIFT 0x04
3129#define TPS65917_INT2_LINE_STATE_WDT 0x04
3130#define TPS65917_INT2_LINE_STATE_WDT_SHIFT 0x02
3131#define TPS65917_INT2_LINE_STATE_OTP_ERROR 0x02
3132#define TPS65917_INT2_LINE_STATE_OTP_ERROR_SHIFT 0x01
3133
3134/* Bit definitions for INT3_STATUS */
3135#define TPS65917_INT3_STATUS_VBUS 0x80
3136#define TPS65917_INT3_STATUS_VBUS_SHIFT 0x07
3137#define TPS65917_INT3_STATUS_GPADC_EOC_SW 0x04
3138#define TPS65917_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02
3139#define TPS65917_INT3_STATUS_GPADC_AUTO_1 0x02
3140#define TPS65917_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01
3141#define TPS65917_INT3_STATUS_GPADC_AUTO_0 0x01
3142#define TPS65917_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00
3143
3144/* Bit definitions for INT3_MASK */
3145#define TPS65917_INT3_MASK_VBUS 0x80
3146#define TPS65917_INT3_MASK_VBUS_SHIFT 0x07
3147#define TPS65917_INT3_MASK_GPADC_EOC_SW 0x04
3148#define TPS65917_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02
3149#define TPS65917_INT3_MASK_GPADC_AUTO_1 0x02
3150#define TPS65917_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01
3151#define TPS65917_INT3_MASK_GPADC_AUTO_0 0x01
3152#define TPS65917_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00
3153
3154/* Bit definitions for INT3_LINE_STATE */
3155#define TPS65917_INT3_LINE_STATE_VBUS 0x80
3156#define TPS65917_INT3_LINE_STATE_VBUS_SHIFT 0x07
3157#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW 0x04
3158#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02
3159#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1 0x02
3160#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01
3161#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0 0x01
3162#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00
3163
3164/* Bit definitions for INT4_STATUS */
3165#define TPS65917_INT4_STATUS_GPIO_6 0x40
3166#define TPS65917_INT4_STATUS_GPIO_6_SHIFT 0x06
3167#define TPS65917_INT4_STATUS_GPIO_5 0x20
3168#define TPS65917_INT4_STATUS_GPIO_5_SHIFT 0x05
3169#define TPS65917_INT4_STATUS_GPIO_4 0x10
3170#define TPS65917_INT4_STATUS_GPIO_4_SHIFT 0x04
3171#define TPS65917_INT4_STATUS_GPIO_3 0x08
3172#define TPS65917_INT4_STATUS_GPIO_3_SHIFT 0x03
3173#define TPS65917_INT4_STATUS_GPIO_2 0x04
3174#define TPS65917_INT4_STATUS_GPIO_2_SHIFT 0x02
3175#define TPS65917_INT4_STATUS_GPIO_1 0x02
3176#define TPS65917_INT4_STATUS_GPIO_1_SHIFT 0x01
3177#define TPS65917_INT4_STATUS_GPIO_0 0x01
3178#define TPS65917_INT4_STATUS_GPIO_0_SHIFT 0x00
3179
3180/* Bit definitions for INT4_MASK */
3181#define TPS65917_INT4_MASK_GPIO_6 0x40
3182#define TPS65917_INT4_MASK_GPIO_6_SHIFT 0x06
3183#define TPS65917_INT4_MASK_GPIO_5 0x20
3184#define TPS65917_INT4_MASK_GPIO_5_SHIFT 0x05
3185#define TPS65917_INT4_MASK_GPIO_4 0x10
3186#define TPS65917_INT4_MASK_GPIO_4_SHIFT 0x04
3187#define TPS65917_INT4_MASK_GPIO_3 0x08
3188#define TPS65917_INT4_MASK_GPIO_3_SHIFT 0x03
3189#define TPS65917_INT4_MASK_GPIO_2 0x04
3190#define TPS65917_INT4_MASK_GPIO_2_SHIFT 0x02
3191#define TPS65917_INT4_MASK_GPIO_1 0x02
3192#define TPS65917_INT4_MASK_GPIO_1_SHIFT 0x01
3193#define TPS65917_INT4_MASK_GPIO_0 0x01
3194#define TPS65917_INT4_MASK_GPIO_0_SHIFT 0x00
3195
3196/* Bit definitions for INT4_LINE_STATE */
3197#define TPS65917_INT4_LINE_STATE_GPIO_6 0x40
3198#define TPS65917_INT4_LINE_STATE_GPIO_6_SHIFT 0x06
3199#define TPS65917_INT4_LINE_STATE_GPIO_5 0x20
3200#define TPS65917_INT4_LINE_STATE_GPIO_5_SHIFT 0x05
3201#define TPS65917_INT4_LINE_STATE_GPIO_4 0x10
3202#define TPS65917_INT4_LINE_STATE_GPIO_4_SHIFT 0x04
3203#define TPS65917_INT4_LINE_STATE_GPIO_3 0x08
3204#define TPS65917_INT4_LINE_STATE_GPIO_3_SHIFT 0x03
3205#define TPS65917_INT4_LINE_STATE_GPIO_2 0x04
3206#define TPS65917_INT4_LINE_STATE_GPIO_2_SHIFT 0x02
3207#define TPS65917_INT4_LINE_STATE_GPIO_1 0x02
3208#define TPS65917_INT4_LINE_STATE_GPIO_1_SHIFT 0x01
3209#define TPS65917_INT4_LINE_STATE_GPIO_0 0x01
3210#define TPS65917_INT4_LINE_STATE_GPIO_0_SHIFT 0x00
3211
3212/* Bit definitions for INT4_EDGE_DETECT1 */
3213#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
3214#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07
3215#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
3216#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06
3217#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
3218#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05
3219#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
3220#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04
3221#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
3222#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03
3223#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
3224#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02
3225#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
3226#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01
3227#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
3228#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00
3229
3230/* Bit definitions for INT4_EDGE_DETECT2 */
3231#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
3232#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05
3233#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
3234#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04
3235#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
3236#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03
3237#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
3238#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02
3239#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
3240#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01
3241#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
3242#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00
3243
3244/* Bit definitions for INT_CTRL */
3245#define TPS65917_INT_CTRL_INT_PENDING 0x04
3246#define TPS65917_INT_CTRL_INT_PENDING_SHIFT 0x02
3247#define TPS65917_INT_CTRL_INT_CLEAR 0x01
3248#define TPS65917_INT_CTRL_INT_CLEAR_SHIFT 0x00
3249
3250/* TPS65917 SMPS Registers */
3251
3252/* Registers for function SMPS */
3253#define TPS65917_SMPS1_CTRL 0x00
3254#define TPS65917_SMPS1_FORCE 0x02
3255#define TPS65917_SMPS1_VOLTAGE 0x03
3256#define TPS65917_SMPS2_CTRL 0x04
3257#define TPS65917_SMPS2_FORCE 0x06
3258#define TPS65917_SMPS2_VOLTAGE 0x07
3259#define TPS65917_SMPS3_CTRL 0x0C
3260#define TPS65917_SMPS3_FORCE 0x0E
3261#define TPS65917_SMPS3_VOLTAGE 0x0F
3262#define TPS65917_SMPS4_CTRL 0x10
3263#define TPS65917_SMPS4_VOLTAGE 0x13
3264#define TPS65917_SMPS5_CTRL 0x18
3265#define TPS65917_SMPS5_VOLTAGE 0x1B
3266#define TPS65917_SMPS_CTRL 0x24
3267#define TPS65917_SMPS_PD_CTRL 0x25
3268#define TPS65917_SMPS_THERMAL_EN 0x27
3269#define TPS65917_SMPS_THERMAL_STATUS 0x28
3270#define TPS65917_SMPS_SHORT_STATUS 0x29
3271#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A
3272#define TPS65917_SMPS_POWERGOOD_MASK1 0x2B
3273#define TPS65917_SMPS_POWERGOOD_MASK2 0x2C
3274
3275/* Bit definitions for SMPS1_CTRL */
3276#define TPS65917_SMPS1_CTRL_WR_S 0x80
3277#define TPS65917_SMPS1_CTRL_WR_S_SHIFT 0x07
3278#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN 0x40
3279#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3280#define TPS65917_SMPS1_CTRL_STATUS_MASK 0x30
3281#define TPS65917_SMPS1_CTRL_STATUS_SHIFT 0x04
3282#define TPS65917_SMPS1_CTRL_MODE_SLEEP_MASK 0x0C
3283#define TPS65917_SMPS1_CTRL_MODE_SLEEP_SHIFT 0x02
3284#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_MASK 0x03
3285#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_SHIFT 0x00
3286
3287/* Bit definitions for SMPS1_FORCE */
3288#define TPS65917_SMPS1_FORCE_CMD 0x80
3289#define TPS65917_SMPS1_FORCE_CMD_SHIFT 0x07
3290#define TPS65917_SMPS1_FORCE_VSEL_MASK 0x7F
3291#define TPS65917_SMPS1_FORCE_VSEL_SHIFT 0x00
3292
3293/* Bit definitions for SMPS1_VOLTAGE */
3294#define TPS65917_SMPS1_VOLTAGE_RANGE 0x80
3295#define TPS65917_SMPS1_VOLTAGE_RANGE_SHIFT 0x07
3296#define TPS65917_SMPS1_VOLTAGE_VSEL_MASK 0x7F
3297#define TPS65917_SMPS1_VOLTAGE_VSEL_SHIFT 0x00
3298
3299/* Bit definitions for SMPS2_CTRL */
3300#define TPS65917_SMPS2_CTRL_WR_S 0x80
3301#define TPS65917_SMPS2_CTRL_WR_S_SHIFT 0x07
3302#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN 0x40
3303#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3304#define TPS65917_SMPS2_CTRL_STATUS_MASK 0x30
3305#define TPS65917_SMPS2_CTRL_STATUS_SHIFT 0x04
3306#define TPS65917_SMPS2_CTRL_MODE_SLEEP_MASK 0x0C
3307#define TPS65917_SMPS2_CTRL_MODE_SLEEP_SHIFT 0x02
3308#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_MASK 0x03
3309#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_SHIFT 0x00
3310
3311/* Bit definitions for SMPS2_FORCE */
3312#define TPS65917_SMPS2_FORCE_CMD 0x80
3313#define TPS65917_SMPS2_FORCE_CMD_SHIFT 0x07
3314#define TPS65917_SMPS2_FORCE_VSEL_MASK 0x7F
3315#define TPS65917_SMPS2_FORCE_VSEL_SHIFT 0x00
3316
3317/* Bit definitions for SMPS2_VOLTAGE */
3318#define TPS65917_SMPS2_VOLTAGE_RANGE 0x80
3319#define TPS65917_SMPS2_VOLTAGE_RANGE_SHIFT 0x07
3320#define TPS65917_SMPS2_VOLTAGE_VSEL_MASK 0x7F
3321#define TPS65917_SMPS2_VOLTAGE_VSEL_SHIFT 0x00
3322
3323/* Bit definitions for SMPS3_CTRL */
3324#define TPS65917_SMPS3_CTRL_WR_S 0x80
3325#define TPS65917_SMPS3_CTRL_WR_S_SHIFT 0x07
3326#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN 0x40
3327#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3328#define TPS65917_SMPS3_CTRL_STATUS_MASK 0x30
3329#define TPS65917_SMPS3_CTRL_STATUS_SHIFT 0x04
3330#define TPS65917_SMPS3_CTRL_MODE_SLEEP_MASK 0x0C
3331#define TPS65917_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02
3332#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
3333#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00
3334
3335/* Bit definitions for SMPS3_FORCE */
3336#define TPS65917_SMPS3_FORCE_CMD 0x80
3337#define TPS65917_SMPS3_FORCE_CMD_SHIFT 0x07
3338#define TPS65917_SMPS3_FORCE_VSEL_MASK 0x7F
3339#define TPS65917_SMPS3_FORCE_VSEL_SHIFT 0x00
3340
3341/* Bit definitions for SMPS3_VOLTAGE */
3342#define TPS65917_SMPS3_VOLTAGE_RANGE 0x80
3343#define TPS65917_SMPS3_VOLTAGE_RANGE_SHIFT 0x07
3344#define TPS65917_SMPS3_VOLTAGE_VSEL_MASK 0x7F
3345#define TPS65917_SMPS3_VOLTAGE_VSEL_SHIFT 0x00
3346
3347/* Bit definitions for SMPS4_CTRL */
3348#define TPS65917_SMPS4_CTRL_WR_S 0x80
3349#define TPS65917_SMPS4_CTRL_WR_S_SHIFT 0x07
3350#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN 0x40
3351#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3352#define TPS65917_SMPS4_CTRL_STATUS_MASK 0x30
3353#define TPS65917_SMPS4_CTRL_STATUS_SHIFT 0x04
3354#define TPS65917_SMPS4_CTRL_MODE_SLEEP_MASK 0x0C
3355#define TPS65917_SMPS4_CTRL_MODE_SLEEP_SHIFT 0x02
3356#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_MASK 0x03
3357#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_SHIFT 0x00
3358
3359/* Bit definitions for SMPS4_VOLTAGE */
3360#define TPS65917_SMPS4_VOLTAGE_RANGE 0x80
3361#define TPS65917_SMPS4_VOLTAGE_RANGE_SHIFT 0x07
3362#define TPS65917_SMPS4_VOLTAGE_VSEL_MASK 0x7F
3363#define TPS65917_SMPS4_VOLTAGE_VSEL_SHIFT 0x00
3364
3365/* Bit definitions for SMPS5_CTRL */
3366#define TPS65917_SMPS5_CTRL_WR_S 0x80
3367#define TPS65917_SMPS5_CTRL_WR_S_SHIFT 0x07
3368#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN 0x40
3369#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3370#define TPS65917_SMPS5_CTRL_STATUS_MASK 0x30
3371#define TPS65917_SMPS5_CTRL_STATUS_SHIFT 0x04
3372#define TPS65917_SMPS5_CTRL_MODE_SLEEP_MASK 0x0C
3373#define TPS65917_SMPS5_CTRL_MODE_SLEEP_SHIFT 0x02
3374#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_MASK 0x03
3375#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_SHIFT 0x00
3376
3377/* Bit definitions for SMPS5_VOLTAGE */
3378#define TPS65917_SMPS5_VOLTAGE_RANGE 0x80
3379#define TPS65917_SMPS5_VOLTAGE_RANGE_SHIFT 0x07
3380#define TPS65917_SMPS5_VOLTAGE_VSEL_MASK 0x7F
3381#define TPS65917_SMPS5_VOLTAGE_VSEL_SHIFT 0x00
3382
3383/* Bit definitions for SMPS_CTRL */
3384#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN 0x10
3385#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN_SHIFT 0x04
3386#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL 0x03
3387#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL_SHIFT 0x00
3388
3389/* Bit definitions for SMPS_PD_CTRL */
3390#define TPS65917_SMPS_PD_CTRL_SMPS5 0x40
3391#define TPS65917_SMPS_PD_CTRL_SMPS5_SHIFT 0x06
3392#define TPS65917_SMPS_PD_CTRL_SMPS4 0x10
3393#define TPS65917_SMPS_PD_CTRL_SMPS4_SHIFT 0x04
3394#define TPS65917_SMPS_PD_CTRL_SMPS3 0x08
3395#define TPS65917_SMPS_PD_CTRL_SMPS3_SHIFT 0x03
3396#define TPS65917_SMPS_PD_CTRL_SMPS2 0x02
3397#define TPS65917_SMPS_PD_CTRL_SMPS2_SHIFT 0x01
3398#define TPS65917_SMPS_PD_CTRL_SMPS1 0x01
3399#define TPS65917_SMPS_PD_CTRL_SMPS1_SHIFT 0x00
3400
3401/* Bit definitions for SMPS_THERMAL_EN */
3402#define TPS65917_SMPS_THERMAL_EN_SMPS5 0x40
3403#define TPS65917_SMPS_THERMAL_EN_SMPS5_SHIFT 0x06
3404#define TPS65917_SMPS_THERMAL_EN_SMPS3 0x08
3405#define TPS65917_SMPS_THERMAL_EN_SMPS3_SHIFT 0x03
3406#define TPS65917_SMPS_THERMAL_EN_SMPS12 0x01
3407#define TPS65917_SMPS_THERMAL_EN_SMPS12_SHIFT 0x00
3408
3409/* Bit definitions for SMPS_THERMAL_STATUS */
3410#define TPS65917_SMPS_THERMAL_STATUS_SMPS5 0x40
3411#define TPS65917_SMPS_THERMAL_STATUS_SMPS5_SHIFT 0x06
3412#define TPS65917_SMPS_THERMAL_STATUS_SMPS3 0x08
3413#define TPS65917_SMPS_THERMAL_STATUS_SMPS3_SHIFT 0x03
3414#define TPS65917_SMPS_THERMAL_STATUS_SMPS12 0x01
3415#define TPS65917_SMPS_THERMAL_STATUS_SMPS12_SHIFT 0x00
3416
3417/* Bit definitions for SMPS_SHORT_STATUS */
3418#define TPS65917_SMPS_SHORT_STATUS_SMPS5 0x40
3419#define TPS65917_SMPS_SHORT_STATUS_SMPS5_SHIFT 0x06
3420#define TPS65917_SMPS_SHORT_STATUS_SMPS4 0x10
3421#define TPS65917_SMPS_SHORT_STATUS_SMPS4_SHIFT 0x04
3422#define TPS65917_SMPS_SHORT_STATUS_SMPS3 0x08
3423#define TPS65917_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x03
3424#define TPS65917_SMPS_SHORT_STATUS_SMPS2 0x02
3425#define TPS65917_SMPS_SHORT_STATUS_SMPS2_SHIFT 0x01
3426#define TPS65917_SMPS_SHORT_STATUS_SMPS1 0x01
3427#define TPS65917_SMPS_SHORT_STATUS_SMPS1_SHIFT 0x00
3428
3429/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
3430#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5 0x40
3431#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5_SHIFT 0x06
3432#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4 0x10
3433#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4_SHIFT 0x04
3434#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x08
3435#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x03
3436#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2 0x02
3437#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2_SHIFT 0x01
3438#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1 0x01
3439#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1_SHIFT 0x00
3440
3441/* Bit definitions for SMPS_POWERGOOD_MASK1 */
3442#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5 0x40
3443#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5_SHIFT 0x06
3444#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4 0x10
3445#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4_SHIFT 0x04
3446#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3 0x08
3447#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x03
3448#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2 0x02
3449#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2_SHIFT 0x01
3450#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1 0x01
3451#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1_SHIFT 0x00
3452
3453/* Bit definitions for SMPS_POWERGOOD_MASK2 */
3454#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
3455#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07
3456#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM_SHIFT 0x10
3457#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM 0x04
3458
3459/* Bit definitions for SMPS_PLL_CTRL */
3460
3461#define TPS65917_SMPS_PLL_CTRL_PLL_EN_PLL_BYPASS_SHIFT 0x08
3462#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_EN_BYPASS 0x03
3463#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK_SHIFT 0x04
3464#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK 0x02
3465
3466/* Registers for function LDO */
3467#define TPS65917_LDO1_CTRL 0x00
3468#define TPS65917_LDO1_VOLTAGE 0x01
3469#define TPS65917_LDO2_CTRL 0x02
3470#define TPS65917_LDO2_VOLTAGE 0x03
3471#define TPS65917_LDO3_CTRL 0x04
3472#define TPS65917_LDO3_VOLTAGE 0x05
3473#define TPS65917_LDO4_CTRL 0x0E
3474#define TPS65917_LDO4_VOLTAGE 0x0F
3475#define TPS65917_LDO5_CTRL 0x12
3476#define TPS65917_LDO5_VOLTAGE 0x13
3477#define TPS65917_LDO_PD_CTRL1 0x1B
3478#define TPS65917_LDO_PD_CTRL2 0x1C
3479#define TPS65917_LDO_SHORT_STATUS1 0x1D
3480#define TPS65917_LDO_SHORT_STATUS2 0x1E
3481#define TPS65917_LDO_PD_CTRL3 0x2D
3482#define TPS65917_LDO_SHORT_STATUS3 0x2E
3483
3484/* Bit definitions for LDO1_CTRL */
3485#define TPS65917_LDO1_CTRL_WR_S 0x80
3486#define TPS65917_LDO1_CTRL_WR_S_SHIFT 0x07
3487#define TPS65917_LDO1_CTRL_BYPASS_EN 0x40
3488#define TPS65917_LDO1_CTRL_BYPASS_EN_SHIFT 0x06
3489#define TPS65917_LDO1_CTRL_STATUS 0x10
3490#define TPS65917_LDO1_CTRL_STATUS_SHIFT 0x04
3491#define TPS65917_LDO1_CTRL_MODE_SLEEP 0x04
3492#define TPS65917_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02
3493#define TPS65917_LDO1_CTRL_MODE_ACTIVE 0x01
3494#define TPS65917_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00
3495
3496/* Bit definitions for LDO1_VOLTAGE */
3497#define TPS65917_LDO1_VOLTAGE_VSEL_MASK 0x2F
3498#define TPS65917_LDO1_VOLTAGE_VSEL_SHIFT 0x00
3499
3500/* Bit definitions for LDO2_CTRL */
3501#define TPS65917_LDO2_CTRL_WR_S 0x80
3502#define TPS65917_LDO2_CTRL_WR_S_SHIFT 0x07
3503#define TPS65917_LDO2_CTRL_BYPASS_EN 0x40
3504#define TPS65917_LDO2_CTRL_BYPASS_EN_SHIFT 0x06
3505#define TPS65917_LDO2_CTRL_STATUS 0x10
3506#define TPS65917_LDO2_CTRL_STATUS_SHIFT 0x04
3507#define TPS65917_LDO2_CTRL_MODE_SLEEP 0x04
3508#define TPS65917_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02
3509#define TPS65917_LDO2_CTRL_MODE_ACTIVE 0x01
3510#define TPS65917_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00
3511
3512/* Bit definitions for LDO2_VOLTAGE */
3513#define TPS65917_LDO2_VOLTAGE_VSEL_MASK 0x2F
3514#define TPS65917_LDO2_VOLTAGE_VSEL_SHIFT 0x00
3515
3516/* Bit definitions for LDO3_CTRL */
3517#define TPS65917_LDO3_CTRL_WR_S 0x80
3518#define TPS65917_LDO3_CTRL_WR_S_SHIFT 0x07
3519#define TPS65917_LDO3_CTRL_STATUS 0x10
3520#define TPS65917_LDO3_CTRL_STATUS_SHIFT 0x04
3521#define TPS65917_LDO3_CTRL_MODE_SLEEP 0x04
3522#define TPS65917_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02
3523#define TPS65917_LDO3_CTRL_MODE_ACTIVE 0x01
3524#define TPS65917_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00
3525
3526/* Bit definitions for LDO3_VOLTAGE */
3527#define TPS65917_LDO3_VOLTAGE_VSEL_MASK 0x2F
3528#define TPS65917_LDO3_VOLTAGE_VSEL_SHIFT 0x00
3529
3530/* Bit definitions for LDO4_CTRL */
3531#define TPS65917_LDO4_CTRL_WR_S 0x80
3532#define TPS65917_LDO4_CTRL_WR_S_SHIFT 0x07
3533#define TPS65917_LDO4_CTRL_STATUS 0x10
3534#define TPS65917_LDO4_CTRL_STATUS_SHIFT 0x04
3535#define TPS65917_LDO4_CTRL_MODE_SLEEP 0x04
3536#define TPS65917_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02
3537#define TPS65917_LDO4_CTRL_MODE_ACTIVE 0x01
3538#define TPS65917_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00
3539
3540/* Bit definitions for LDO4_VOLTAGE */
3541#define TPS65917_LDO4_VOLTAGE_VSEL_MASK 0x2F
3542#define TPS65917_LDO4_VOLTAGE_VSEL_SHIFT 0x00
3543
3544/* Bit definitions for LDO5_CTRL */
3545#define TPS65917_LDO5_CTRL_WR_S 0x80
3546#define TPS65917_LDO5_CTRL_WR_S_SHIFT 0x07
3547#define TPS65917_LDO5_CTRL_STATUS 0x10
3548#define TPS65917_LDO5_CTRL_STATUS_SHIFT 0x04
3549#define TPS65917_LDO5_CTRL_MODE_SLEEP 0x04
3550#define TPS65917_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02
3551#define TPS65917_LDO5_CTRL_MODE_ACTIVE 0x01
3552#define TPS65917_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00
3553
3554/* Bit definitions for LDO5_VOLTAGE */
3555#define TPS65917_LDO5_VOLTAGE_VSEL_MASK 0x2F
3556#define TPS65917_LDO5_VOLTAGE_VSEL_SHIFT 0x00
3557
3558/* Bit definitions for LDO_PD_CTRL1 */
3559#define TPS65917_LDO_PD_CTRL1_LDO4 0x80
3560#define TPS65917_LDO_PD_CTRL1_LDO4_SHIFT 0x07
3561#define TPS65917_LDO_PD_CTRL1_LDO2 0x02
3562#define TPS65917_LDO_PD_CTRL1_LDO2_SHIFT 0x01
3563#define TPS65917_LDO_PD_CTRL1_LDO1 0x01
3564#define TPS65917_LDO_PD_CTRL1_LDO1_SHIFT 0x00
3565
3566/* Bit definitions for LDO_PD_CTRL2 */
3567#define TPS65917_LDO_PD_CTRL2_LDO3 0x04
3568#define TPS65917_LDO_PD_CTRL2_LDO3_SHIFT 0x02
3569#define TPS65917_LDO_PD_CTRL2_LDO5 0x02
3570#define TPS65917_LDO_PD_CTRL2_LDO5_SHIFT 0x01
3571
3572/* Bit definitions for LDO_PD_CTRL3 */
3573#define TPS65917_LDO_PD_CTRL2_LDOVANA 0x80
3574#define TPS65917_LDO_PD_CTRL2_LDOVANA_SHIFT 0x07
3575
3576/* Bit definitions for LDO_SHORT_STATUS1 */
3577#define TPS65917_LDO_SHORT_STATUS1_LDO4 0x80
3578#define TPS65917_LDO_SHORT_STATUS1_LDO4_SHIFT 0x07
3579#define TPS65917_LDO_SHORT_STATUS1_LDO2 0x02
3580#define TPS65917_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01
3581#define TPS65917_LDO_SHORT_STATUS1_LDO1 0x01
3582#define TPS65917_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00
3583
3584/* Bit definitions for LDO_SHORT_STATUS2 */
3585#define TPS65917_LDO_SHORT_STATUS2_LDO3 0x04
3586#define TPS65917_LDO_SHORT_STATUS2_LDO3_SHIFT 0x02
3587#define TPS65917_LDO_SHORT_STATUS2_LDO5 0x02
3588#define TPS65917_LDO_SHORT_STATUS2_LDO5_SHIFT 0x01
3589
3590/* Bit definitions for LDO_SHORT_STATUS2 */
3591#define TPS65917_LDO_SHORT_STATUS2_LDOVANA 0x80
3592#define TPS65917_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x07
3593
3594/* Bit definitions for REGEN1_CTRL */
3595#define TPS65917_REGEN1_CTRL_STATUS 0x10
3596#define TPS65917_REGEN1_CTRL_STATUS_SHIFT 0x04
3597#define TPS65917_REGEN1_CTRL_MODE_SLEEP 0x04
3598#define TPS65917_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02
3599#define TPS65917_REGEN1_CTRL_MODE_ACTIVE 0x01
3600#define TPS65917_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
3601
3602/* Bit definitions for PLLEN_CTRL */
3603#define TPS65917_PLLEN_CTRL_STATUS 0x10
3604#define TPS65917_PLLEN_CTRL_STATUS_SHIFT 0x04
3605#define TPS65917_PLLEN_CTRL_MODE_SLEEP 0x04
3606#define TPS65917_PLLEN_CTRL_MODE_SLEEP_SHIFT 0x02
3607#define TPS65917_PLLEN_CTRL_MODE_ACTIVE 0x01
3608#define TPS65917_PLLEN_CTRL_MODE_ACTIVE_SHIFT 0x00
3609
3610/* Bit definitions for REGEN2_CTRL */
3611#define TPS65917_REGEN2_CTRL_STATUS 0x10
3612#define TPS65917_REGEN2_CTRL_STATUS_SHIFT 0x04
3613#define TPS65917_REGEN2_CTRL_MODE_SLEEP 0x04
3614#define TPS65917_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02
3615#define TPS65917_REGEN2_CTRL_MODE_ACTIVE 0x01
3616#define TPS65917_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
3617
3618/* Bit definitions for NSLEEP_RES_ASSIGN */
3619#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN 0x08
3620#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN_SHIFT 0x03
3621#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3 0x04
3622#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x02
3623#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2 0x02
3624#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01
3625#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1 0x01
3626#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00
3627
3628/* Bit definitions for NSLEEP_SMPS_ASSIGN */
3629#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5 0x40
3630#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5_SHIFT 0x06
3631#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4 0x10
3632#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4_SHIFT 0x04
3633#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3 0x08
3634#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x03
3635#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2 0x02
3636#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2_SHIFT 0x01
3637#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1 0x01
3638#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1_SHIFT 0x00
3639
3640/* Bit definitions for NSLEEP_LDO_ASSIGN1 */
3641#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4 0x80
3642#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x07
3643#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2 0x02
3644#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01
3645#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1 0x01
3646#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00
3647
3648/* Bit definitions for NSLEEP_LDO_ASSIGN2 */
3649#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3 0x04
3650#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3_SHIFT 0x02
3651#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5 0x02
3652#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5_SHIFT 0x01
3653
3654/* Bit definitions for ENABLE1_RES_ASSIGN */
3655#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN 0x08
3656#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN_SHIFT 0x03
3657#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3 0x04
3658#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x02
3659#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2 0x02
3660#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01
3661#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1 0x01
3662#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00
3663
3664/* Bit definitions for ENABLE1_SMPS_ASSIGN */
3665#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5 0x40
3666#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5_SHIFT 0x06
3667#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4 0x10
3668#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4_SHIFT 0x04
3669#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3 0x08
3670#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x03
3671#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2 0x02
3672#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2_SHIFT 0x01
3673#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1 0x01
3674#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1_SHIFT 0x00
3675
3676/* Bit definitions for ENABLE1_LDO_ASSIGN1 */
3677#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4 0x80
3678#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x07
3679#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2 0x02
3680#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01
3681#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1 0x01
3682#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00
3683
3684/* Bit definitions for ENABLE1_LDO_ASSIGN2 */
3685#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3 0x04
3686#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3_SHIFT 0x02
3687#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5 0x02
3688#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5_SHIFT 0x01
3689
3690/* Bit definitions for ENABLE2_RES_ASSIGN */
3691#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN 0x08
3692#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN_SHIFT 0x03
3693#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3 0x04
3694#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x02
3695#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2 0x02
3696#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01
3697#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1 0x01
3698#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00
3699
3700/* Bit definitions for ENABLE2_SMPS_ASSIGN */
3701#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5 0x40
3702#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5_SHIFT 0x06
3703#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4 0x10
3704#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4_SHIFT 0x04
3705#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3 0x08
3706#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x03
3707#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2 0x02
3708#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2_SHIFT 0x01
3709#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1 0x01
3710#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1_SHIFT 0x00
3711
3712/* Bit definitions for ENABLE2_LDO_ASSIGN1 */
3713#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4 0x80
3714#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x07
3715#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2 0x02
3716#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01
3717#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1 0x01
3718#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00
3719
3720/* Bit definitions for ENABLE2_LDO_ASSIGN2 */
3721#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3 0x04
3722#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3_SHIFT 0x02
3723#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5 0x02
3724#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5_SHIFT 0x01
3725
3726/* Bit definitions for REGEN3_CTRL */
3727#define TPS65917_REGEN3_CTRL_STATUS 0x10
3728#define TPS65917_REGEN3_CTRL_STATUS_SHIFT 0x04
3729#define TPS65917_REGEN3_CTRL_MODE_SLEEP 0x04
3730#define TPS65917_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02
3731#define TPS65917_REGEN3_CTRL_MODE_ACTIVE 0x01
3732#define TPS65917_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00
3733
3734/* Registers for function RESOURCE */
3735#define TPS65917_REGEN1_CTRL 0x2
3736#define TPS65917_PLLEN_CTRL 0x3
3737#define TPS65917_NSLEEP_RES_ASSIGN 0x6
3738#define TPS65917_NSLEEP_SMPS_ASSIGN 0x7
3739#define TPS65917_NSLEEP_LDO_ASSIGN1 0x8
3740#define TPS65917_NSLEEP_LDO_ASSIGN2 0x9
3741#define TPS65917_ENABLE1_RES_ASSIGN 0xA
3742#define TPS65917_ENABLE1_SMPS_ASSIGN 0xB
3743#define TPS65917_ENABLE1_LDO_ASSIGN1 0xC
3744#define TPS65917_ENABLE1_LDO_ASSIGN2 0xD
3745#define TPS65917_ENABLE2_RES_ASSIGN 0xE
3746#define TPS65917_ENABLE2_SMPS_ASSIGN 0xF
3747#define TPS65917_ENABLE2_LDO_ASSIGN1 0x10
3748#define TPS65917_ENABLE2_LDO_ASSIGN2 0x11
3749#define TPS65917_REGEN2_CTRL 0x12
3750#define TPS65917_REGEN3_CTRL 0x13
3751
3752static inline int palmas_read(struct palmas *palmas, unsigned int base,
3753 unsigned int reg, unsigned int *val)
3754{
3755 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3756 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3757
3758 return regmap_read(palmas->regmap[slave_id], addr, val);
3759}
3760
3761static inline int palmas_write(struct palmas *palmas, unsigned int base,
3762 unsigned int reg, unsigned int value)
3763{
3764 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3765 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3766
3767 return regmap_write(palmas->regmap[slave_id], addr, value);
3768}
3769
3770static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base,
3771 unsigned int reg, const void *val, size_t val_count)
3772{
3773 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3774 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3775
3776 return regmap_bulk_write(palmas->regmap[slave_id], addr,
3777 val, val_count);
3778}
3779
3780static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base,
3781 unsigned int reg, void *val, size_t val_count)
3782{
3783 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3784 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3785
3786 return regmap_bulk_read(palmas->regmap[slave_id], addr,
3787 val, val_count);
3788}
3789
3790static inline int palmas_update_bits(struct palmas *palmas, unsigned int base,
3791 unsigned int reg, unsigned int mask, unsigned int val)
3792{
3793 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3794 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3795
3796 return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val);
3797}
3798
3799static inline int palmas_irq_get_virq(struct palmas *palmas, int irq)
3800{
3801 return regmap_irq_get_virq(palmas->irq_data, irq);
3802}
3803
3804
3805int palmas_ext_control_req_config(struct palmas *palmas,
3806 enum palmas_external_requestor_id ext_control_req_id,
3807 int ext_ctrl, bool enable);
3808
3809#endif /* __LINUX_MFD_PALMAS_H */