Linux kernel mirror (for testing)
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linux
1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_CORE_CQ_H
34#define MLX5_CORE_CQ_H
35
36#include <rdma/ib_verbs.h>
37#include <linux/mlx5/driver.h>
38
39
40struct mlx5_core_cq {
41 u32 cqn;
42 int cqe_sz;
43 __be32 *set_ci_db;
44 __be32 *arm_db;
45 atomic_t refcount;
46 struct completion free;
47 unsigned vector;
48 unsigned int irqn;
49 void (*comp) (struct mlx5_core_cq *);
50 void (*event) (struct mlx5_core_cq *, enum mlx5_event);
51 struct mlx5_uar *uar;
52 u32 cons_index;
53 unsigned arm_sn;
54 struct mlx5_rsc_debug *dbg;
55 int pid;
56 struct {
57 struct list_head list;
58 void (*comp)(struct mlx5_core_cq *);
59 void *priv;
60 } tasklet_ctx;
61};
62
63
64enum {
65 MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR = 0x01,
66 MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR = 0x02,
67 MLX5_CQE_SYNDROME_LOCAL_PROT_ERR = 0x04,
68 MLX5_CQE_SYNDROME_WR_FLUSH_ERR = 0x05,
69 MLX5_CQE_SYNDROME_MW_BIND_ERR = 0x06,
70 MLX5_CQE_SYNDROME_BAD_RESP_ERR = 0x10,
71 MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR = 0x11,
72 MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12,
73 MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR = 0x13,
74 MLX5_CQE_SYNDROME_REMOTE_OP_ERR = 0x14,
75 MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR = 0x15,
76 MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR = 0x16,
77 MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR = 0x22,
78};
79
80enum {
81 MLX5_CQE_OWNER_MASK = 1,
82 MLX5_CQE_REQ = 0,
83 MLX5_CQE_RESP_WR_IMM = 1,
84 MLX5_CQE_RESP_SEND = 2,
85 MLX5_CQE_RESP_SEND_IMM = 3,
86 MLX5_CQE_RESP_SEND_INV = 4,
87 MLX5_CQE_RESIZE_CQ = 5,
88 MLX5_CQE_SIG_ERR = 12,
89 MLX5_CQE_REQ_ERR = 13,
90 MLX5_CQE_RESP_ERR = 14,
91 MLX5_CQE_INVALID = 15,
92};
93
94enum {
95 MLX5_CQ_MODIFY_PERIOD = 1 << 0,
96 MLX5_CQ_MODIFY_COUNT = 1 << 1,
97 MLX5_CQ_MODIFY_OVERRUN = 1 << 2,
98};
99
100enum {
101 MLX5_CQ_OPMOD_RESIZE = 1,
102 MLX5_MODIFY_CQ_MASK_LOG_SIZE = 1 << 0,
103 MLX5_MODIFY_CQ_MASK_PG_OFFSET = 1 << 1,
104 MLX5_MODIFY_CQ_MASK_PG_SIZE = 1 << 2,
105};
106
107struct mlx5_cq_modify_params {
108 int type;
109 union {
110 struct {
111 u32 page_offset;
112 u8 log_cq_size;
113 } resize;
114
115 struct {
116 } moder;
117
118 struct {
119 } mapping;
120 } params;
121};
122
123enum {
124 CQE_SIZE_64 = 0,
125 CQE_SIZE_128 = 1,
126};
127
128static inline int cqe_sz_to_mlx_sz(u8 size)
129{
130 return size == 64 ? CQE_SIZE_64 : CQE_SIZE_128;
131}
132
133static inline void mlx5_cq_set_ci(struct mlx5_core_cq *cq)
134{
135 *cq->set_ci_db = cpu_to_be32(cq->cons_index & 0xffffff);
136}
137
138enum {
139 MLX5_CQ_DB_REQ_NOT_SOL = 1 << 24,
140 MLX5_CQ_DB_REQ_NOT = 0 << 24
141};
142
143static inline void mlx5_cq_arm(struct mlx5_core_cq *cq, u32 cmd,
144 void __iomem *uar_page,
145 spinlock_t *doorbell_lock,
146 u32 cons_index)
147{
148 __be32 doorbell[2];
149 u32 sn;
150 u32 ci;
151
152 sn = cq->arm_sn & 3;
153 ci = cons_index & 0xffffff;
154
155 *cq->arm_db = cpu_to_be32(sn << 28 | cmd | ci);
156
157 /* Make sure that the doorbell record in host memory is
158 * written before ringing the doorbell via PCI MMIO.
159 */
160 wmb();
161
162 doorbell[0] = cpu_to_be32(sn << 28 | cmd | ci);
163 doorbell[1] = cpu_to_be32(cq->cqn);
164
165 mlx5_write64(doorbell, uar_page + MLX5_CQ_DOORBELL, doorbell_lock);
166}
167
168int mlx5_init_cq_table(struct mlx5_core_dev *dev);
169void mlx5_cleanup_cq_table(struct mlx5_core_dev *dev);
170int mlx5_core_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
171 struct mlx5_create_cq_mbox_in *in, int inlen);
172int mlx5_core_destroy_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq);
173int mlx5_core_query_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
174 struct mlx5_query_cq_mbox_out *out);
175int mlx5_core_modify_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
176 struct mlx5_modify_cq_mbox_in *in, int in_sz);
177int mlx5_core_modify_cq_moderation(struct mlx5_core_dev *dev,
178 struct mlx5_core_cq *cq, u16 cq_period,
179 u16 cq_max_count);
180int mlx5_debug_cq_add(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq);
181void mlx5_debug_cq_remove(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq);
182
183#endif /* MLX5_CORE_CQ_H */