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1Renesas R-Car CAN controller Device Tree Bindings
2-------------------------------------------------
3
4Required properties:
5- compatible: "renesas,can-r8a7778" if CAN controller is a part of R8A7778 SoC.
6 "renesas,can-r8a7779" if CAN controller is a part of R8A7779 SoC.
7 "renesas,can-r8a7790" if CAN controller is a part of R8A7790 SoC.
8 "renesas,can-r8a7791" if CAN controller is a part of R8A7791 SoC.
9 "renesas,can-r8a7792" if CAN controller is a part of R8A7792 SoC.
10 "renesas,can-r8a7793" if CAN controller is a part of R8A7793 SoC.
11 "renesas,can-r8a7794" if CAN controller is a part of R8A7794 SoC.
12 "renesas,can-r8a7795" if CAN controller is a part of R8A7795 SoC.
13 "renesas,rcar-gen1-can" for a generic R-Car Gen1 compatible device.
14 "renesas,rcar-gen2-can" for a generic R-Car Gen2 compatible device.
15 "renesas,rcar-gen3-can" for a generic R-Car Gen3 compatible device.
16 When compatible with the generic version, nodes must list the
17 SoC-specific version corresponding to the platform first
18 followed by the generic version.
19
20- reg: physical base address and size of the R-Car CAN register map.
21- interrupts: interrupt specifier for the sole interrupt.
22- clocks: phandles and clock specifiers for 3 CAN clock inputs.
23- clock-names: 3 clock input name strings: "clkp1", "clkp2", "can_clk".
24- pinctrl-0: pin control group to be used for this controller.
25- pinctrl-names: must be "default".
26
27Required properties for "renesas,can-r8a7795" compatible:
28In R8A7795 SoC, "clkp2" can be CANFD clock. This is a div6 clock and can be
29used by both CAN and CAN FD controller at the same time. It needs to be scaled
30to maximum frequency if any of these controllers use it. This is done using
31the below properties.
32
33- assigned-clocks: phandle of clkp2(CANFD) clock.
34- assigned-clock-rates: maximum frequency of this clock.
35
36Optional properties:
37- renesas,can-clock-select: R-Car CAN Clock Source Select. Valid values are:
38 <0x0> (default) : Peripheral clock (clkp1)
39 <0x1> : Peripheral clock (clkp2)
40 <0x3> : Externally input clock
41
42Example
43-------
44
45SoC common .dtsi file:
46
47 can0: can@e6e80000 {
48 compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
49 reg = <0 0xe6e80000 0 0x1000>;
50 interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
51 clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
52 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
53 clock-names = "clkp1", "clkp2", "can_clk";
54 status = "disabled";
55 };
56
57Board specific .dts file:
58
59&can0 {
60 pinctrl-0 = <&can0_pins>;
61 pinctrl-names = "default";
62 status = "okay";
63};