Linux kernel mirror (for testing)
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1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __AMD_SHARED_H__
24#define __AMD_SHARED_H__
25
26#define AMD_MAX_USEC_TIMEOUT 100000 /* 100 ms */
27
28/*
29* Supported GPU families (aligned with amdgpu_drm.h)
30*/
31#define AMD_FAMILY_UNKNOWN 0
32#define AMD_FAMILY_CI 120 /* Bonaire, Hawaii */
33#define AMD_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */
34#define AMD_FAMILY_VI 130 /* Iceland, Tonga */
35#define AMD_FAMILY_CZ 135 /* Carrizo */
36
37/*
38 * Supported ASIC types
39 */
40enum amd_asic_type {
41 CHIP_BONAIRE = 0,
42 CHIP_KAVERI,
43 CHIP_KABINI,
44 CHIP_HAWAII,
45 CHIP_MULLINS,
46 CHIP_TOPAZ,
47 CHIP_TONGA,
48 CHIP_FIJI,
49 CHIP_CARRIZO,
50 CHIP_STONEY,
51 CHIP_POLARIS10,
52 CHIP_POLARIS11,
53 CHIP_LAST,
54};
55
56/*
57 * Chip flags
58 */
59enum amd_chip_flags {
60 AMD_ASIC_MASK = 0x0000ffffUL,
61 AMD_FLAGS_MASK = 0xffff0000UL,
62 AMD_IS_MOBILITY = 0x00010000UL,
63 AMD_IS_APU = 0x00020000UL,
64 AMD_IS_PX = 0x00040000UL,
65 AMD_EXP_HW_SUPPORT = 0x00080000UL,
66};
67
68enum amd_ip_block_type {
69 AMD_IP_BLOCK_TYPE_COMMON,
70 AMD_IP_BLOCK_TYPE_GMC,
71 AMD_IP_BLOCK_TYPE_IH,
72 AMD_IP_BLOCK_TYPE_SMC,
73 AMD_IP_BLOCK_TYPE_DCE,
74 AMD_IP_BLOCK_TYPE_GFX,
75 AMD_IP_BLOCK_TYPE_SDMA,
76 AMD_IP_BLOCK_TYPE_UVD,
77 AMD_IP_BLOCK_TYPE_VCE,
78 AMD_IP_BLOCK_TYPE_ACP,
79};
80
81enum amd_clockgating_state {
82 AMD_CG_STATE_GATE = 0,
83 AMD_CG_STATE_UNGATE,
84};
85
86enum amd_powergating_state {
87 AMD_PG_STATE_GATE = 0,
88 AMD_PG_STATE_UNGATE,
89};
90
91/* CG flags */
92#define AMD_CG_SUPPORT_GFX_MGCG (1 << 0)
93#define AMD_CG_SUPPORT_GFX_MGLS (1 << 1)
94#define AMD_CG_SUPPORT_GFX_CGCG (1 << 2)
95#define AMD_CG_SUPPORT_GFX_CGLS (1 << 3)
96#define AMD_CG_SUPPORT_GFX_CGTS (1 << 4)
97#define AMD_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
98#define AMD_CG_SUPPORT_GFX_CP_LS (1 << 6)
99#define AMD_CG_SUPPORT_GFX_RLC_LS (1 << 7)
100#define AMD_CG_SUPPORT_MC_LS (1 << 8)
101#define AMD_CG_SUPPORT_MC_MGCG (1 << 9)
102#define AMD_CG_SUPPORT_SDMA_LS (1 << 10)
103#define AMD_CG_SUPPORT_SDMA_MGCG (1 << 11)
104#define AMD_CG_SUPPORT_BIF_LS (1 << 12)
105#define AMD_CG_SUPPORT_UVD_MGCG (1 << 13)
106#define AMD_CG_SUPPORT_VCE_MGCG (1 << 14)
107#define AMD_CG_SUPPORT_HDP_LS (1 << 15)
108#define AMD_CG_SUPPORT_HDP_MGCG (1 << 16)
109#define AMD_CG_SUPPORT_ROM_MGCG (1 << 17)
110
111/* PG flags */
112#define AMD_PG_SUPPORT_GFX_PG (1 << 0)
113#define AMD_PG_SUPPORT_GFX_SMG (1 << 1)
114#define AMD_PG_SUPPORT_GFX_DMG (1 << 2)
115#define AMD_PG_SUPPORT_UVD (1 << 3)
116#define AMD_PG_SUPPORT_VCE (1 << 4)
117#define AMD_PG_SUPPORT_CP (1 << 5)
118#define AMD_PG_SUPPORT_GDS (1 << 6)
119#define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7)
120#define AMD_PG_SUPPORT_SDMA (1 << 8)
121#define AMD_PG_SUPPORT_ACP (1 << 9)
122#define AMD_PG_SUPPORT_SAMU (1 << 10)
123
124enum amd_pm_state_type {
125 /* not used for dpm */
126 POWER_STATE_TYPE_DEFAULT,
127 POWER_STATE_TYPE_POWERSAVE,
128 /* user selectable states */
129 POWER_STATE_TYPE_BATTERY,
130 POWER_STATE_TYPE_BALANCED,
131 POWER_STATE_TYPE_PERFORMANCE,
132 /* internal states */
133 POWER_STATE_TYPE_INTERNAL_UVD,
134 POWER_STATE_TYPE_INTERNAL_UVD_SD,
135 POWER_STATE_TYPE_INTERNAL_UVD_HD,
136 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
137 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
138 POWER_STATE_TYPE_INTERNAL_BOOT,
139 POWER_STATE_TYPE_INTERNAL_THERMAL,
140 POWER_STATE_TYPE_INTERNAL_ACPI,
141 POWER_STATE_TYPE_INTERNAL_ULV,
142 POWER_STATE_TYPE_INTERNAL_3DPERF,
143};
144
145struct amd_ip_funcs {
146 /* Name of IP block */
147 char *name;
148 /* sets up early driver state (pre sw_init), does not configure hw - Optional */
149 int (*early_init)(void *handle);
150 /* sets up late driver/hw state (post hw_init) - Optional */
151 int (*late_init)(void *handle);
152 /* sets up driver state, does not configure hw */
153 int (*sw_init)(void *handle);
154 /* tears down driver state, does not configure hw */
155 int (*sw_fini)(void *handle);
156 /* sets up the hw state */
157 int (*hw_init)(void *handle);
158 /* tears down the hw state */
159 int (*hw_fini)(void *handle);
160 void (*late_fini)(void *handle);
161 /* handles IP specific hw/sw changes for suspend */
162 int (*suspend)(void *handle);
163 /* handles IP specific hw/sw changes for resume */
164 int (*resume)(void *handle);
165 /* returns current IP block idle status */
166 bool (*is_idle)(void *handle);
167 /* poll for idle */
168 int (*wait_for_idle)(void *handle);
169 /* soft reset the IP block */
170 int (*soft_reset)(void *handle);
171 /* enable/disable cg for the IP block */
172 int (*set_clockgating_state)(void *handle,
173 enum amd_clockgating_state state);
174 /* enable/disable pg for the IP block */
175 int (*set_powergating_state)(void *handle,
176 enum amd_powergating_state state);
177};
178
179#endif /* __AMD_SHARED_H__ */