tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1#ifndef __MACH_IMX_CLK_H
2#define __MACH_IMX_CLK_H
3
4#include <linux/spinlock.h>
5#include <linux/clk-provider.h>
6
7extern spinlock_t imx_ccm_lock;
8
9void imx_check_clocks(struct clk *clks[], unsigned int count);
10void imx_register_uart_clocks(struct clk ** const clks[]);
11
12extern void imx_cscmr1_fixup(u32 *val);
13
14enum imx_pllv1_type {
15 IMX_PLLV1_IMX1,
16 IMX_PLLV1_IMX21,
17 IMX_PLLV1_IMX25,
18 IMX_PLLV1_IMX27,
19 IMX_PLLV1_IMX31,
20 IMX_PLLV1_IMX35,
21};
22
23struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name,
24 const char *parent, void __iomem *base);
25
26struct clk *imx_clk_pllv2(const char *name, const char *parent,
27 void __iomem *base);
28
29enum imx_pllv3_type {
30 IMX_PLLV3_GENERIC,
31 IMX_PLLV3_SYS,
32 IMX_PLLV3_USB,
33 IMX_PLLV3_USB_VF610,
34 IMX_PLLV3_AV,
35 IMX_PLLV3_ENET,
36 IMX_PLLV3_ENET_IMX7,
37};
38
39struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
40 const char *parent_name, void __iomem *base, u32 div_mask);
41
42struct clk *clk_register_gate2(struct device *dev, const char *name,
43 const char *parent_name, unsigned long flags,
44 void __iomem *reg, u8 bit_idx, u8 cgr_val,
45 u8 clk_gate_flags, spinlock_t *lock,
46 unsigned int *share_count);
47
48struct clk * imx_obtain_fixed_clock(
49 const char *name, unsigned long rate);
50
51struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
52 void __iomem *reg, u8 shift, u32 exclusive_mask);
53
54static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
55 void __iomem *reg, u8 shift)
56{
57 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
58 shift, 0x3, 0, &imx_ccm_lock, NULL);
59}
60
61static inline struct clk *imx_clk_gate2_shared(const char *name,
62 const char *parent, void __iomem *reg, u8 shift,
63 unsigned int *share_count)
64{
65 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
66 shift, 0x3, 0, &imx_ccm_lock, share_count);
67}
68
69static inline struct clk *imx_clk_gate2_cgr(const char *name, const char *parent,
70 void __iomem *reg, u8 shift, u8 cgr_val)
71{
72 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
73 shift, cgr_val, 0, &imx_ccm_lock, NULL);
74}
75
76struct clk *imx_clk_pfd(const char *name, const char *parent_name,
77 void __iomem *reg, u8 idx);
78
79struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
80 void __iomem *reg, u8 shift, u8 width,
81 void __iomem *busy_reg, u8 busy_shift);
82
83struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
84 u8 width, void __iomem *busy_reg, u8 busy_shift,
85 const char **parent_names, int num_parents);
86
87struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
88 void __iomem *reg, u8 shift, u8 width,
89 void (*fixup)(u32 *val));
90
91struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
92 u8 shift, u8 width, const char **parents,
93 int num_parents, void (*fixup)(u32 *val));
94
95static inline struct clk *imx_clk_fixed(const char *name, int rate)
96{
97 return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
98}
99
100static inline struct clk *imx_clk_divider(const char *name, const char *parent,
101 void __iomem *reg, u8 shift, u8 width)
102{
103 return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
104 reg, shift, width, 0, &imx_ccm_lock);
105}
106
107static inline struct clk *imx_clk_divider_flags(const char *name,
108 const char *parent, void __iomem *reg, u8 shift, u8 width,
109 unsigned long flags)
110{
111 return clk_register_divider(NULL, name, parent, flags,
112 reg, shift, width, 0, &imx_ccm_lock);
113}
114
115static inline struct clk *imx_clk_gate(const char *name, const char *parent,
116 void __iomem *reg, u8 shift)
117{
118 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
119 shift, 0, &imx_ccm_lock);
120}
121
122static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,
123 void __iomem *reg, u8 shift)
124{
125 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
126 shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);
127}
128
129static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
130 u8 shift, u8 width, const char **parents, int num_parents)
131{
132 return clk_register_mux(NULL, name, parents, num_parents,
133 CLK_SET_RATE_NO_REPARENT, reg, shift,
134 width, 0, &imx_ccm_lock);
135}
136
137static inline struct clk *imx_clk_mux_flags(const char *name,
138 void __iomem *reg, u8 shift, u8 width, const char **parents,
139 int num_parents, unsigned long flags)
140{
141 return clk_register_mux(NULL, name, parents, num_parents,
142 flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
143 &imx_ccm_lock);
144}
145
146static inline struct clk *imx_clk_fixed_factor(const char *name,
147 const char *parent, unsigned int mult, unsigned int div)
148{
149 return clk_register_fixed_factor(NULL, name, parent,
150 CLK_SET_RATE_PARENT, mult, div);
151}
152
153struct clk *imx_clk_cpu(const char *name, const char *parent_name,
154 struct clk *div, struct clk *mux, struct clk *pll,
155 struct clk *step);
156
157#endif