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1/*
2 * Cache operations for the cache instruction.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
9 * (C) Copyright 1999 Silicon Graphics, Inc.
10 */
11#ifndef __ASM_CACHEOPS_H
12#define __ASM_CACHEOPS_H
13
14/*
15 * Most cache ops are split into a 2 bit field identifying the cache, and a 3
16 * bit field identifying the cache operation.
17 */
18#define CacheOp_Cache 0x03
19#define CacheOp_Op 0x1c
20
21#define Cache_I 0x00
22#define Cache_D 0x01
23#define Cache_T 0x02
24#define Cache_S 0x03
25
26#define Index_Writeback_Inv 0x00
27#define Index_Load_Tag 0x04
28#define Index_Store_Tag 0x08
29#define Hit_Invalidate 0x10
30#define Hit_Writeback_Inv 0x14 /* not with Cache_I though */
31#define Hit_Writeback 0x18
32
33/*
34 * Cache Operations available on all MIPS processors with R4000-style caches
35 */
36#define Index_Invalidate_I (Cache_I | Index_Writeback_Inv)
37#define Index_Writeback_Inv_D (Cache_D | Index_Writeback_Inv)
38#define Index_Load_Tag_I (Cache_I | Index_Load_Tag)
39#define Index_Load_Tag_D (Cache_D | Index_Load_Tag)
40#define Index_Store_Tag_I (Cache_I | Index_Store_Tag)
41#define Index_Store_Tag_D (Cache_D | Index_Store_Tag)
42#define Hit_Invalidate_I (Cache_I | Hit_Invalidate)
43#define Hit_Invalidate_D (Cache_D | Hit_Invalidate)
44#define Hit_Writeback_Inv_D (Cache_D | Hit_Writeback_Inv)
45
46/*
47 * R4000-specific cacheops
48 */
49#define Create_Dirty_Excl_D (Cache_D | 0x0c)
50#define Fill (Cache_I | 0x14)
51#define Hit_Writeback_I (Cache_I | Hit_Writeback)
52#define Hit_Writeback_D (Cache_D | Hit_Writeback)
53
54/*
55 * R4000SC and R4400SC-specific cacheops
56 */
57#define Cache_SI 0x02
58#define Cache_SD 0x03
59
60#define Index_Invalidate_SI (Cache_SI | Index_Writeback_Inv)
61#define Index_Writeback_Inv_SD (Cache_SD | Index_Writeback_Inv)
62#define Index_Load_Tag_SI (Cache_SI | Index_Load_Tag)
63#define Index_Load_Tag_SD (Cache_SD | Index_Load_Tag)
64#define Index_Store_Tag_SI (Cache_SI | Index_Store_Tag)
65#define Index_Store_Tag_SD (Cache_SD | Index_Store_Tag)
66#define Create_Dirty_Excl_SD (Cache_SD | 0x0c)
67#define Hit_Invalidate_SI (Cache_SI | Hit_Invalidate)
68#define Hit_Invalidate_SD (Cache_SD | Hit_Invalidate)
69#define Hit_Writeback_Inv_SD (Cache_SD | Hit_Writeback_Inv)
70#define Hit_Writeback_SD (Cache_SD | Hit_Writeback)
71#define Hit_Set_Virtual_SI (Cache_SI | 0x1c)
72#define Hit_Set_Virtual_SD (Cache_SD | 0x1c)
73
74/*
75 * R5000-specific cacheops
76 */
77#define R5K_Page_Invalidate_S (Cache_S | 0x14)
78
79/*
80 * RM7000-specific cacheops
81 */
82#define Page_Invalidate_T (Cache_T | 0x14)
83#define Index_Store_Tag_T (Cache_T | Index_Store_Tag)
84#define Index_Load_Tag_T (Cache_T | Index_Load_Tag)
85
86/*
87 * R10000-specific cacheops
88 *
89 * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
90 * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
91 */
92#define Index_Writeback_Inv_S (Cache_S | Index_Writeback_Inv)
93#define Index_Load_Tag_S (Cache_S | Index_Load_Tag)
94#define Index_Store_Tag_S (Cache_S | Index_Store_Tag)
95#define Hit_Invalidate_S (Cache_S | Hit_Invalidate)
96#define Cache_Barrier 0x14
97#define Hit_Writeback_Inv_S (Cache_S | Hit_Writeback_Inv)
98#define Index_Load_Data_I (Cache_I | 0x18)
99#define Index_Load_Data_D (Cache_D | 0x18)
100#define Index_Load_Data_S (Cache_S | 0x18)
101#define Index_Store_Data_I (Cache_I | 0x1c)
102#define Index_Store_Data_D (Cache_D | 0x1c)
103#define Index_Store_Data_S (Cache_S | 0x1c)
104
105/*
106 * Loongson2-specific cacheops
107 */
108#define Hit_Invalidate_I_Loongson2 (Cache_I | 0x00)
109
110#endif /* __ASM_CACHEOPS_H */