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1* Renesas R-Car generation 2 USB PHY
2
3This file provides information on what the device node for the R-Car generation
42 USB PHY contains.
5
6Required properties:
7- compatible: "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC.
8 "renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC.
9 "renesas,usb-phy-r8a7794" if the device is a part of R8A7794 SoC.
10- reg: offset and length of the register block.
11- #address-cells: number of address cells for the USB channel subnodes, must
12 be <1>.
13- #size-cells: number of size cells for the USB channel subnodes, must be <0>.
14- clocks: clock phandle and specifier pair.
15- clock-names: string, clock input name, must be "usbhs".
16
17The USB PHY device tree node should have the subnodes corresponding to the USB
18channels. These subnodes must contain the following properties:
19- reg: the USB controller selector; see the table below for the values.
20- #phy-cells: see phy-bindings.txt in the same directory, must be <1>.
21
22The phandle's argument in the PHY specifier is the USB controller selector for
23the USB channel; see the selector meanings below:
24
25+-----------+---------------+---------------+
26|\ Selector | | |
27+ --------- + 0 | 1 |
28| Channel \| | |
29+-----------+---------------+---------------+
30| 0 | PCI EHCI/OHCI | HS-USB |
31| 2 | PCI EHCI/OHCI | xHCI |
32+-----------+---------------+---------------+
33
34Example (Lager board):
35
36 usb-phy@e6590100 {
37 compatible = "renesas,usb-phy-r8a7790";
38 reg = <0 0xe6590100 0 0x100>;
39 #address-cells = <1>;
40 #size-cells = <0>;
41 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
42 clock-names = "usbhs";
43
44 usb-channel@0 {
45 reg = <0>;
46 #phy-cells = <1>;
47 };
48 usb-channel@2 {
49 reg = <2>;
50 #phy-cells = <1>;
51 };
52 };