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1* ARM Generic Interrupt Controller
2
3ARM SMP cores are often associated with a GIC, providing per processor
4interrupts (PPI), shared processor interrupts (SPI) and software
5generated interrupts (SGI).
6
7Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
8Secondary GICs are cascaded into the upward interrupt controller and do not
9have PPIs or SGIs.
10
11Main node required properties:
12
13- compatible : should be one of:
14 "arm,arm1176jzf-devchip-gic"
15 "arm,arm11mp-gic"
16 "arm,cortex-a15-gic"
17 "arm,cortex-a7-gic"
18 "arm,cortex-a9-gic"
19 "arm,eb11mp-gic"
20 "arm,gic-400"
21 "arm,pl390"
22 "arm,tc11mp-gic"
23 "brcm,brahma-b15-gic"
24 "qcom,msm-8660-qgic"
25 "qcom,msm-qgic2"
26- interrupt-controller : Identifies the node as an interrupt controller
27- #interrupt-cells : Specifies the number of cells needed to encode an
28 interrupt source. The type shall be a <u32> and the value shall be 3.
29
30 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
31 interrupts.
32
33 The 2nd cell contains the interrupt number for the interrupt type.
34 SPI interrupts are in the range [0-987]. PPI interrupts are in the
35 range [0-15].
36
37 The 3rd cell is the flags, encoded as follows:
38 bits[3:0] trigger type and level flags.
39 1 = low-to-high edge triggered
40 2 = high-to-low edge triggered (invalid for SPIs)
41 4 = active high level-sensitive
42 8 = active low level-sensitive (invalid for SPIs).
43 bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of
44 the 8 possible cpus attached to the GIC. A bit set to '1' indicated
45 the interrupt is wired to that CPU. Only valid for PPI interrupts.
46 Also note that the configurability of PPI interrupts is IMPLEMENTATION
47 DEFINED and as such not guaranteed to be present (most SoC available
48 in 2014 seem to ignore the setting of this flag and use the hardware
49 default value).
50
51- reg : Specifies base physical address(s) and size of the GIC registers. The
52 first region is the GIC distributor register base and size. The 2nd region is
53 the GIC cpu interface register base and size.
54
55Optional
56- interrupts : Interrupt source of the parent interrupt controller on
57 secondary GICs, or VGIC maintenance interrupt on primary GIC (see
58 below).
59
60- cpu-offset : per-cpu offset within the distributor and cpu interface
61 regions, used when the GIC doesn't have banked registers. The offset is
62 cpu-offset * cpu-nr.
63
64- clocks : List of phandle and clock-specific pairs, one for each entry
65 in clock-names.
66- clock-names : List of names for the GIC clock input(s). Valid clock names
67 depend on the GIC variant:
68 "ic_clk" (for "arm,arm11mp-gic")
69 "PERIPHCLKEN" (for "arm,cortex-a15-gic")
70 "PERIPHCLK", "PERIPHCLKEN" (for "arm,cortex-a9-gic")
71 "clk" (for "arm,gic-400")
72 "gclk" (for "arm,pl390")
73
74- power-domains : A phandle and PM domain specifier as defined by bindings of
75 the power controller specified by phandle, used when the GIC
76 is part of a Power or Clock Domain.
77
78
79Example:
80
81 intc: interrupt-controller@fff11000 {
82 compatible = "arm,cortex-a9-gic";
83 #interrupt-cells = <3>;
84 #address-cells = <1>;
85 interrupt-controller;
86 reg = <0xfff11000 0x1000>,
87 <0xfff10100 0x100>;
88 };
89
90
91* GIC virtualization extensions (VGIC)
92
93For ARM cores that support the virtualization extensions, additional
94properties must be described (they only exist if the GIC is the
95primary interrupt controller).
96
97Required properties:
98
99- reg : Additional regions specifying the base physical address and
100 size of the VGIC registers. The first additional region is the GIC
101 virtual interface control register base and size. The 2nd additional
102 region is the GIC virtual cpu interface register base and size.
103
104- interrupts : VGIC maintenance interrupt.
105
106Example:
107
108 interrupt-controller@2c001000 {
109 compatible = "arm,cortex-a15-gic";
110 #interrupt-cells = <3>;
111 interrupt-controller;
112 reg = <0x2c001000 0x1000>,
113 <0x2c002000 0x1000>,
114 <0x2c004000 0x2000>,
115 <0x2c006000 0x2000>;
116 interrupts = <1 9 0xf04>;
117 };
118
119
120* GICv2m extension for MSI/MSI-x support (Optional)
121
122Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
123This is enabled by specifying v2m sub-node(s).
124
125Required properties:
126
127- compatible : The value here should contain "arm,gic-v2m-frame".
128
129- msi-controller : Identifies the node as an MSI controller.
130
131- reg : GICv2m MSI interface register base and size
132
133Optional properties:
134
135- arm,msi-base-spi : When the MSI_TYPER register contains an incorrect
136 value, this property should contain the SPI base of
137 the MSI frame, overriding the HW value.
138
139- arm,msi-num-spis : When the MSI_TYPER register contains an incorrect
140 value, this property should contain the number of
141 SPIs assigned to the frame, overriding the HW value.
142
143Example:
144
145 interrupt-controller@e1101000 {
146 compatible = "arm,gic-400";
147 #interrupt-cells = <3>;
148 #address-cells = <2>;
149 #size-cells = <2>;
150 interrupt-controller;
151 interrupts = <1 8 0xf04>;
152 ranges = <0 0 0 0xe1100000 0 0x100000>;
153 reg = <0x0 0xe1110000 0 0x01000>,
154 <0x0 0xe112f000 0 0x02000>,
155 <0x0 0xe1140000 0 0x10000>,
156 <0x0 0xe1160000 0 0x10000>;
157 v2m0: v2m@0x8000 {
158 compatible = "arm,gic-v2m-frame";
159 msi-controller;
160 reg = <0x0 0x80000 0 0x1000>;
161 };
162
163 ....
164
165 v2mN: v2m@0x9000 {
166 compatible = "arm,gic-v2m-frame";
167 msi-controller;
168 reg = <0x0 0x90000 0 0x1000>;
169 };
170 };