tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef RADEON_MODE_H
31#define RADEON_MODE_H
32
33#include <drm/drm_crtc.h>
34#include <drm/drm_edid.h>
35#include <drm/drm_dp_helper.h>
36#include <drm/drm_dp_mst_helper.h>
37#include <drm/drm_fixed.h>
38#include <drm/drm_crtc_helper.h>
39#include <linux/i2c.h>
40#include <linux/i2c-algo-bit.h>
41
42struct radeon_bo;
43struct radeon_device;
44
45#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
46#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
47#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
48#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
49
50#define RADEON_MAX_HPD_PINS 7
51#define RADEON_MAX_CRTCS 6
52#define RADEON_MAX_AFMT_BLOCKS 7
53
54enum radeon_rmx_type {
55 RMX_OFF,
56 RMX_FULL,
57 RMX_CENTER,
58 RMX_ASPECT
59};
60
61enum radeon_tv_std {
62 TV_STD_NTSC,
63 TV_STD_PAL,
64 TV_STD_PAL_M,
65 TV_STD_PAL_60,
66 TV_STD_NTSC_J,
67 TV_STD_SCART_PAL,
68 TV_STD_SECAM,
69 TV_STD_PAL_CN,
70 TV_STD_PAL_N,
71};
72
73enum radeon_underscan_type {
74 UNDERSCAN_OFF,
75 UNDERSCAN_ON,
76 UNDERSCAN_AUTO,
77};
78
79enum radeon_hpd_id {
80 RADEON_HPD_1 = 0,
81 RADEON_HPD_2,
82 RADEON_HPD_3,
83 RADEON_HPD_4,
84 RADEON_HPD_5,
85 RADEON_HPD_6,
86 RADEON_HPD_NONE = 0xff,
87};
88
89enum radeon_output_csc {
90 RADEON_OUTPUT_CSC_BYPASS = 0,
91 RADEON_OUTPUT_CSC_TVRGB = 1,
92 RADEON_OUTPUT_CSC_YCBCR601 = 2,
93 RADEON_OUTPUT_CSC_YCBCR709 = 3,
94};
95
96#define RADEON_MAX_I2C_BUS 16
97
98/* radeon gpio-based i2c
99 * 1. "mask" reg and bits
100 * grabs the gpio pins for software use
101 * 0=not held 1=held
102 * 2. "a" reg and bits
103 * output pin value
104 * 0=low 1=high
105 * 3. "en" reg and bits
106 * sets the pin direction
107 * 0=input 1=output
108 * 4. "y" reg and bits
109 * input pin value
110 * 0=low 1=high
111 */
112struct radeon_i2c_bus_rec {
113 bool valid;
114 /* id used by atom */
115 uint8_t i2c_id;
116 /* id used by atom */
117 enum radeon_hpd_id hpd;
118 /* can be used with hw i2c engine */
119 bool hw_capable;
120 /* uses multi-media i2c engine */
121 bool mm_i2c;
122 /* regs and bits */
123 uint32_t mask_clk_reg;
124 uint32_t mask_data_reg;
125 uint32_t a_clk_reg;
126 uint32_t a_data_reg;
127 uint32_t en_clk_reg;
128 uint32_t en_data_reg;
129 uint32_t y_clk_reg;
130 uint32_t y_data_reg;
131 uint32_t mask_clk_mask;
132 uint32_t mask_data_mask;
133 uint32_t a_clk_mask;
134 uint32_t a_data_mask;
135 uint32_t en_clk_mask;
136 uint32_t en_data_mask;
137 uint32_t y_clk_mask;
138 uint32_t y_data_mask;
139};
140
141struct radeon_tmds_pll {
142 uint32_t freq;
143 uint32_t value;
144};
145
146#define RADEON_MAX_BIOS_CONNECTOR 16
147
148/* pll flags */
149#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
150#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
151#define RADEON_PLL_USE_REF_DIV (1 << 2)
152#define RADEON_PLL_LEGACY (1 << 3)
153#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
154#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
155#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
156#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
157#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
158#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
159#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
160#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
161#define RADEON_PLL_USE_POST_DIV (1 << 12)
162#define RADEON_PLL_IS_LCD (1 << 13)
163#define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
164
165struct radeon_pll {
166 /* reference frequency */
167 uint32_t reference_freq;
168
169 /* fixed dividers */
170 uint32_t reference_div;
171 uint32_t post_div;
172
173 /* pll in/out limits */
174 uint32_t pll_in_min;
175 uint32_t pll_in_max;
176 uint32_t pll_out_min;
177 uint32_t pll_out_max;
178 uint32_t lcd_pll_out_min;
179 uint32_t lcd_pll_out_max;
180 uint32_t best_vco;
181
182 /* divider limits */
183 uint32_t min_ref_div;
184 uint32_t max_ref_div;
185 uint32_t min_post_div;
186 uint32_t max_post_div;
187 uint32_t min_feedback_div;
188 uint32_t max_feedback_div;
189 uint32_t min_frac_feedback_div;
190 uint32_t max_frac_feedback_div;
191
192 /* flags for the current clock */
193 uint32_t flags;
194
195 /* pll id */
196 uint32_t id;
197};
198
199struct radeon_i2c_chan {
200 struct i2c_adapter adapter;
201 struct drm_device *dev;
202 struct i2c_algo_bit_data bit;
203 struct radeon_i2c_bus_rec rec;
204 struct drm_dp_aux aux;
205 bool has_aux;
206 struct mutex mutex;
207};
208
209/* mostly for macs, but really any system without connector tables */
210enum radeon_connector_table {
211 CT_NONE = 0,
212 CT_GENERIC,
213 CT_IBOOK,
214 CT_POWERBOOK_EXTERNAL,
215 CT_POWERBOOK_INTERNAL,
216 CT_POWERBOOK_VGA,
217 CT_MINI_EXTERNAL,
218 CT_MINI_INTERNAL,
219 CT_IMAC_G5_ISIGHT,
220 CT_EMAC,
221 CT_RN50_POWER,
222 CT_MAC_X800,
223 CT_MAC_G5_9600,
224 CT_SAM440EP,
225 CT_MAC_G4_SILVER
226};
227
228enum radeon_dvo_chip {
229 DVO_SIL164,
230 DVO_SIL1178,
231};
232
233struct radeon_fbdev;
234
235struct radeon_afmt {
236 bool enabled;
237 int offset;
238 bool last_buffer_filled_status;
239 int id;
240};
241
242struct radeon_mode_info {
243 struct atom_context *atom_context;
244 struct card_info *atom_card_info;
245 enum radeon_connector_table connector_table;
246 bool mode_config_initialized;
247 struct radeon_crtc *crtcs[RADEON_MAX_CRTCS];
248 struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS];
249 /* DVI-I properties */
250 struct drm_property *coherent_mode_property;
251 /* DAC enable load detect */
252 struct drm_property *load_detect_property;
253 /* TV standard */
254 struct drm_property *tv_std_property;
255 /* legacy TMDS PLL detect */
256 struct drm_property *tmds_pll_property;
257 /* underscan */
258 struct drm_property *underscan_property;
259 struct drm_property *underscan_hborder_property;
260 struct drm_property *underscan_vborder_property;
261 /* audio */
262 struct drm_property *audio_property;
263 /* FMT dithering */
264 struct drm_property *dither_property;
265 /* Output CSC */
266 struct drm_property *output_csc_property;
267 /* hardcoded DFP edid from BIOS */
268 struct edid *bios_hardcoded_edid;
269 int bios_hardcoded_edid_size;
270
271 /* pointer to fbdev info structure */
272 struct radeon_fbdev *rfbdev;
273 /* firmware flags */
274 u16 firmware_flags;
275 /* pointer to backlight encoder */
276 struct radeon_encoder *bl_encoder;
277
278 /* bitmask for active encoder frontends */
279 uint32_t active_encoders;
280};
281
282#define RADEON_MAX_BL_LEVEL 0xFF
283
284#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
285
286struct radeon_backlight_privdata {
287 struct radeon_encoder *encoder;
288 uint8_t negative;
289};
290
291#endif
292
293#define MAX_H_CODE_TIMING_LEN 32
294#define MAX_V_CODE_TIMING_LEN 32
295
296/* need to store these as reading
297 back code tables is excessive */
298struct radeon_tv_regs {
299 uint32_t tv_uv_adr;
300 uint32_t timing_cntl;
301 uint32_t hrestart;
302 uint32_t vrestart;
303 uint32_t frestart;
304 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
305 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
306};
307
308struct radeon_atom_ss {
309 uint16_t percentage;
310 uint16_t percentage_divider;
311 uint8_t type;
312 uint16_t step;
313 uint8_t delay;
314 uint8_t range;
315 uint8_t refdiv;
316 /* asic_ss */
317 uint16_t rate;
318 uint16_t amount;
319};
320
321enum radeon_flip_status {
322 RADEON_FLIP_NONE,
323 RADEON_FLIP_PENDING,
324 RADEON_FLIP_SUBMITTED
325};
326
327struct radeon_crtc {
328 struct drm_crtc base;
329 int crtc_id;
330 u16 lut_r[256], lut_g[256], lut_b[256];
331 bool enabled;
332 bool can_tile;
333 uint32_t crtc_offset;
334 struct drm_gem_object *cursor_bo;
335 uint64_t cursor_addr;
336 int cursor_x;
337 int cursor_y;
338 int cursor_hot_x;
339 int cursor_hot_y;
340 int cursor_width;
341 int cursor_height;
342 int max_cursor_width;
343 int max_cursor_height;
344 uint32_t legacy_display_base_addr;
345 enum radeon_rmx_type rmx_type;
346 u8 h_border;
347 u8 v_border;
348 fixed20_12 vsc;
349 fixed20_12 hsc;
350 struct drm_display_mode native_mode;
351 int pll_id;
352 /* page flipping */
353 struct workqueue_struct *flip_queue;
354 struct radeon_flip_work *flip_work;
355 enum radeon_flip_status flip_status;
356 /* pll sharing */
357 struct radeon_atom_ss ss;
358 bool ss_enabled;
359 u32 adjusted_clock;
360 int bpc;
361 u32 pll_reference_div;
362 u32 pll_post_div;
363 u32 pll_flags;
364 struct drm_encoder *encoder;
365 struct drm_connector *connector;
366 /* for dpm */
367 u32 line_time;
368 u32 wm_low;
369 u32 wm_high;
370 u32 lb_vblank_lead_lines;
371 struct drm_display_mode hw_mode;
372 enum radeon_output_csc output_csc;
373};
374
375struct radeon_encoder_primary_dac {
376 /* legacy primary dac */
377 uint32_t ps2_pdac_adj;
378};
379
380struct radeon_encoder_lvds {
381 /* legacy lvds */
382 uint16_t panel_vcc_delay;
383 uint8_t panel_pwr_delay;
384 uint8_t panel_digon_delay;
385 uint8_t panel_blon_delay;
386 uint16_t panel_ref_divider;
387 uint8_t panel_post_divider;
388 uint16_t panel_fb_divider;
389 bool use_bios_dividers;
390 uint32_t lvds_gen_cntl;
391 /* panel mode */
392 struct drm_display_mode native_mode;
393 struct backlight_device *bl_dev;
394 int dpms_mode;
395 uint8_t backlight_level;
396};
397
398struct radeon_encoder_tv_dac {
399 /* legacy tv dac */
400 uint32_t ps2_tvdac_adj;
401 uint32_t ntsc_tvdac_adj;
402 uint32_t pal_tvdac_adj;
403
404 int h_pos;
405 int v_pos;
406 int h_size;
407 int supported_tv_stds;
408 bool tv_on;
409 enum radeon_tv_std tv_std;
410 struct radeon_tv_regs tv;
411};
412
413struct radeon_encoder_int_tmds {
414 /* legacy int tmds */
415 struct radeon_tmds_pll tmds_pll[4];
416};
417
418struct radeon_encoder_ext_tmds {
419 /* tmds over dvo */
420 struct radeon_i2c_chan *i2c_bus;
421 uint8_t slave_addr;
422 enum radeon_dvo_chip dvo_chip;
423};
424
425/* spread spectrum */
426struct radeon_encoder_atom_dig {
427 bool linkb;
428 /* atom dig */
429 bool coherent_mode;
430 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
431 /* atom lvds/edp */
432 uint32_t lcd_misc;
433 uint16_t panel_pwr_delay;
434 uint32_t lcd_ss_id;
435 /* panel mode */
436 struct drm_display_mode native_mode;
437 struct backlight_device *bl_dev;
438 int dpms_mode;
439 uint8_t backlight_level;
440 int panel_mode;
441 struct radeon_afmt *afmt;
442 struct r600_audio_pin *pin;
443 int active_mst_links;
444};
445
446struct radeon_encoder_atom_dac {
447 enum radeon_tv_std tv_std;
448};
449
450struct radeon_encoder_mst {
451 int crtc;
452 struct radeon_encoder *primary;
453 struct radeon_connector *connector;
454 struct drm_dp_mst_port *port;
455 int pbn;
456 int fe;
457 bool fe_from_be;
458 bool enc_active;
459};
460
461struct radeon_encoder {
462 struct drm_encoder base;
463 uint32_t encoder_enum;
464 uint32_t encoder_id;
465 uint32_t devices;
466 uint32_t active_device;
467 uint32_t flags;
468 uint32_t pixel_clock;
469 enum radeon_rmx_type rmx_type;
470 enum radeon_underscan_type underscan_type;
471 uint32_t underscan_hborder;
472 uint32_t underscan_vborder;
473 struct drm_display_mode native_mode;
474 void *enc_priv;
475 int audio_polling_active;
476 bool is_ext_encoder;
477 u16 caps;
478 struct radeon_audio_funcs *audio;
479 enum radeon_output_csc output_csc;
480 bool can_mst;
481 uint32_t offset;
482 bool is_mst_encoder;
483 /* front end for this mst encoder */
484};
485
486struct radeon_connector_atom_dig {
487 uint32_t igp_lane_info;
488 /* displayport */
489 u8 dpcd[DP_RECEIVER_CAP_SIZE];
490 u8 dp_sink_type;
491 int dp_clock;
492 int dp_lane_count;
493 bool edp_on;
494 bool is_mst;
495};
496
497struct radeon_gpio_rec {
498 bool valid;
499 u8 id;
500 u32 reg;
501 u32 mask;
502 u32 shift;
503};
504
505struct radeon_hpd {
506 enum radeon_hpd_id hpd;
507 u8 plugged_state;
508 struct radeon_gpio_rec gpio;
509};
510
511struct radeon_router {
512 u32 router_id;
513 struct radeon_i2c_bus_rec i2c_info;
514 u8 i2c_addr;
515 /* i2c mux */
516 bool ddc_valid;
517 u8 ddc_mux_type;
518 u8 ddc_mux_control_pin;
519 u8 ddc_mux_state;
520 /* clock/data mux */
521 bool cd_valid;
522 u8 cd_mux_type;
523 u8 cd_mux_control_pin;
524 u8 cd_mux_state;
525};
526
527enum radeon_connector_audio {
528 RADEON_AUDIO_DISABLE = 0,
529 RADEON_AUDIO_ENABLE = 1,
530 RADEON_AUDIO_AUTO = 2
531};
532
533enum radeon_connector_dither {
534 RADEON_FMT_DITHER_DISABLE = 0,
535 RADEON_FMT_DITHER_ENABLE = 1,
536};
537
538struct stream_attribs {
539 uint16_t fe;
540 uint16_t slots;
541};
542
543struct radeon_connector {
544 struct drm_connector base;
545 uint32_t connector_id;
546 uint32_t devices;
547 struct radeon_i2c_chan *ddc_bus;
548 /* some systems have an hdmi and vga port with a shared ddc line */
549 bool shared_ddc;
550 bool use_digital;
551 /* we need to mind the EDID between detect
552 and get modes due to analog/digital/tvencoder */
553 struct edid *edid;
554 void *con_priv;
555 bool dac_load_detect;
556 bool detected_by_load; /* if the connection status was determined by load */
557 bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */
558 uint16_t connector_object_id;
559 struct radeon_hpd hpd;
560 struct radeon_router router;
561 struct radeon_i2c_chan *router_bus;
562 enum radeon_connector_audio audio;
563 enum radeon_connector_dither dither;
564 int pixelclock_for_modeset;
565 bool is_mst_connector;
566 struct radeon_connector *mst_port;
567 struct drm_dp_mst_port *port;
568 struct drm_dp_mst_topology_mgr mst_mgr;
569
570 struct radeon_encoder *mst_encoder;
571 struct stream_attribs cur_stream_attribs[6];
572 int enabled_attribs;
573};
574
575struct radeon_framebuffer {
576 struct drm_framebuffer base;
577 struct drm_gem_object *obj;
578};
579
580#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
581 ((em) == ATOM_ENCODER_MODE_DP_MST))
582
583struct atom_clock_dividers {
584 u32 post_div;
585 union {
586 struct {
587#ifdef __BIG_ENDIAN
588 u32 reserved : 6;
589 u32 whole_fb_div : 12;
590 u32 frac_fb_div : 14;
591#else
592 u32 frac_fb_div : 14;
593 u32 whole_fb_div : 12;
594 u32 reserved : 6;
595#endif
596 };
597 u32 fb_div;
598 };
599 u32 ref_div;
600 bool enable_post_div;
601 bool enable_dithen;
602 u32 vco_mode;
603 u32 real_clock;
604 /* added for CI */
605 u32 post_divider;
606 u32 flags;
607};
608
609struct atom_mpll_param {
610 union {
611 struct {
612#ifdef __BIG_ENDIAN
613 u32 reserved : 8;
614 u32 clkfrac : 12;
615 u32 clkf : 12;
616#else
617 u32 clkf : 12;
618 u32 clkfrac : 12;
619 u32 reserved : 8;
620#endif
621 };
622 u32 fb_div;
623 };
624 u32 post_div;
625 u32 bwcntl;
626 u32 dll_speed;
627 u32 vco_mode;
628 u32 yclk_sel;
629 u32 qdr;
630 u32 half_rate;
631};
632
633#define MEM_TYPE_GDDR5 0x50
634#define MEM_TYPE_GDDR4 0x40
635#define MEM_TYPE_GDDR3 0x30
636#define MEM_TYPE_DDR2 0x20
637#define MEM_TYPE_GDDR1 0x10
638#define MEM_TYPE_DDR3 0xb0
639#define MEM_TYPE_MASK 0xf0
640
641struct atom_memory_info {
642 u8 mem_vendor;
643 u8 mem_type;
644};
645
646#define MAX_AC_TIMING_ENTRIES 16
647
648struct atom_memory_clock_range_table
649{
650 u8 num_entries;
651 u8 rsv[3];
652 u32 mclk[MAX_AC_TIMING_ENTRIES];
653};
654
655#define VBIOS_MC_REGISTER_ARRAY_SIZE 32
656#define VBIOS_MAX_AC_TIMING_ENTRIES 20
657
658struct atom_mc_reg_entry {
659 u32 mclk_max;
660 u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
661};
662
663struct atom_mc_register_address {
664 u16 s1;
665 u8 pre_reg_data;
666};
667
668struct atom_mc_reg_table {
669 u8 last;
670 u8 num_entries;
671 struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
672 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
673};
674
675#define MAX_VOLTAGE_ENTRIES 32
676
677struct atom_voltage_table_entry
678{
679 u16 value;
680 u32 smio_low;
681};
682
683struct atom_voltage_table
684{
685 u32 count;
686 u32 mask_low;
687 u32 phase_delay;
688 struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
689};
690
691/* Driver internal use only flags of radeon_get_crtc_scanoutpos() */
692#define USE_REAL_VBLANKSTART (1 << 30)
693#define GET_DISTANCE_TO_VBLANKSTART (1 << 31)
694
695extern void
696radeon_add_atom_connector(struct drm_device *dev,
697 uint32_t connector_id,
698 uint32_t supported_device,
699 int connector_type,
700 struct radeon_i2c_bus_rec *i2c_bus,
701 uint32_t igp_lane_info,
702 uint16_t connector_object_id,
703 struct radeon_hpd *hpd,
704 struct radeon_router *router);
705extern void
706radeon_add_legacy_connector(struct drm_device *dev,
707 uint32_t connector_id,
708 uint32_t supported_device,
709 int connector_type,
710 struct radeon_i2c_bus_rec *i2c_bus,
711 uint16_t connector_object_id,
712 struct radeon_hpd *hpd);
713extern uint32_t
714radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
715 uint8_t dac);
716extern void radeon_link_encoder_connector(struct drm_device *dev);
717
718extern enum radeon_tv_std
719radeon_combios_get_tv_info(struct radeon_device *rdev);
720extern enum radeon_tv_std
721radeon_atombios_get_tv_info(struct radeon_device *rdev);
722extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
723 u16 *vddc, u16 *vddci, u16 *mvdd);
724
725extern void
726radeon_combios_connected_scratch_regs(struct drm_connector *connector,
727 struct drm_encoder *encoder,
728 bool connected);
729extern void
730radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
731 struct drm_encoder *encoder,
732 bool connected);
733
734extern struct drm_connector *
735radeon_get_connector_for_encoder(struct drm_encoder *encoder);
736extern struct drm_connector *
737radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
738extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
739 u32 pixel_clock);
740
741extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
742extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
743extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
744extern int radeon_get_monitor_bpc(struct drm_connector *connector);
745
746extern struct edid *radeon_connector_edid(struct drm_connector *connector);
747
748extern void radeon_connector_hotplug(struct drm_connector *connector);
749extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
750 struct drm_display_mode *mode);
751extern void radeon_dp_set_link_config(struct drm_connector *connector,
752 const struct drm_display_mode *mode);
753extern void radeon_dp_link_train(struct drm_encoder *encoder,
754 struct drm_connector *connector);
755extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
756extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
757extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
758extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
759 struct drm_connector *connector);
760extern int radeon_dp_get_dp_link_config(struct drm_connector *connector,
761 const u8 *dpcd,
762 unsigned pix_clock,
763 unsigned *dp_lanes, unsigned *dp_rate);
764extern void radeon_dp_set_rx_power_state(struct drm_connector *connector,
765 u8 power_state);
766extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector);
767extern ssize_t
768radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg);
769
770extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
771extern void atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override);
772extern void radeon_atom_encoder_init(struct radeon_device *rdev);
773extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
774extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
775 int action, uint8_t lane_num,
776 uint8_t lane_set);
777extern void atombios_dig_transmitter_setup2(struct drm_encoder *encoder,
778 int action, uint8_t lane_num,
779 uint8_t lane_set, int fe);
780extern void atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder,
781 int fe);
782extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
783extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
784void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
785
786extern void radeon_i2c_init(struct radeon_device *rdev);
787extern void radeon_i2c_fini(struct radeon_device *rdev);
788extern void radeon_combios_i2c_init(struct radeon_device *rdev);
789extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
790extern void radeon_i2c_add(struct radeon_device *rdev,
791 struct radeon_i2c_bus_rec *rec,
792 const char *name);
793extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
794 struct radeon_i2c_bus_rec *i2c_bus);
795extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
796 struct radeon_i2c_bus_rec *rec,
797 const char *name);
798extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
799extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
800 u8 slave_addr,
801 u8 addr,
802 u8 *val);
803extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
804 u8 slave_addr,
805 u8 addr,
806 u8 val);
807extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
808extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
809extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
810
811extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
812 struct radeon_atom_ss *ss,
813 int id);
814extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
815 struct radeon_atom_ss *ss,
816 int id, u32 clock);
817extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
818 u8 id);
819
820extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
821 uint64_t freq,
822 uint32_t *dot_clock_p,
823 uint32_t *fb_div_p,
824 uint32_t *frac_fb_div_p,
825 uint32_t *ref_div_p,
826 uint32_t *post_div_p);
827
828extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
829 u32 freq,
830 u32 *dot_clock_p,
831 u32 *fb_div_p,
832 u32 *frac_fb_div_p,
833 u32 *ref_div_p,
834 u32 *post_div_p);
835
836extern void radeon_setup_encoder_clones(struct drm_device *dev);
837
838struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
839struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
840struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
841struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
842struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
843extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
844extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
845extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
846extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
847extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
848extern bool radeon_encoder_is_digital(struct drm_encoder *encoder);
849
850extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
851extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
852 struct drm_framebuffer *old_fb);
853extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
854 struct drm_framebuffer *fb,
855 int x, int y,
856 enum mode_set_atomic state);
857extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
858 struct drm_display_mode *mode,
859 struct drm_display_mode *adjusted_mode,
860 int x, int y,
861 struct drm_framebuffer *old_fb);
862extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
863
864extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
865 struct drm_framebuffer *old_fb);
866extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
867 struct drm_framebuffer *fb,
868 int x, int y,
869 enum mode_set_atomic state);
870extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
871 struct drm_framebuffer *fb,
872 int x, int y, int atomic);
873extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc,
874 struct drm_file *file_priv,
875 uint32_t handle,
876 uint32_t width,
877 uint32_t height,
878 int32_t hot_x,
879 int32_t hot_y);
880extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
881 int x, int y);
882extern void radeon_cursor_reset(struct drm_crtc *crtc);
883
884extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
885 unsigned int flags, int *vpos, int *hpos,
886 ktime_t *stime, ktime_t *etime,
887 const struct drm_display_mode *mode);
888
889extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
890extern struct edid *
891radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
892extern bool radeon_atom_get_clock_info(struct drm_device *dev);
893extern bool radeon_combios_get_clock_info(struct drm_device *dev);
894extern struct radeon_encoder_atom_dig *
895radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
896extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
897 struct radeon_encoder_int_tmds *tmds);
898extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
899 struct radeon_encoder_int_tmds *tmds);
900extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
901 struct radeon_encoder_int_tmds *tmds);
902extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
903 struct radeon_encoder_ext_tmds *tmds);
904extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
905 struct radeon_encoder_ext_tmds *tmds);
906extern struct radeon_encoder_primary_dac *
907radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
908extern struct radeon_encoder_tv_dac *
909radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
910extern struct radeon_encoder_lvds *
911radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
912extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
913extern struct radeon_encoder_tv_dac *
914radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
915extern struct radeon_encoder_primary_dac *
916radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
917extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
918extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
919extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
920extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
921extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
922extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
923extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
924extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
925extern void
926radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
927extern void
928radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
929extern void
930radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
931extern void
932radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
933extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
934 u16 blue, int regno);
935extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
936 u16 *blue, int regno);
937int radeon_framebuffer_init(struct drm_device *dev,
938 struct radeon_framebuffer *rfb,
939 const struct drm_mode_fb_cmd2 *mode_cmd,
940 struct drm_gem_object *obj);
941
942int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
943bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
944bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
945void radeon_atombios_init_crtc(struct drm_device *dev,
946 struct radeon_crtc *radeon_crtc);
947void radeon_legacy_init_crtc(struct drm_device *dev,
948 struct radeon_crtc *radeon_crtc);
949
950void radeon_get_clock_info(struct drm_device *dev);
951
952extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
953extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
954
955void radeon_enc_destroy(struct drm_encoder *encoder);
956void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
957void radeon_combios_asic_init(struct drm_device *dev);
958bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
959 const struct drm_display_mode *mode,
960 struct drm_display_mode *adjusted_mode);
961void radeon_panel_mode_fixup(struct drm_encoder *encoder,
962 struct drm_display_mode *adjusted_mode);
963void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
964
965/* legacy tv */
966void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
967 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
968 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
969void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
970 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
971 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
972void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
973 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
974 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
975void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
976 struct drm_display_mode *mode,
977 struct drm_display_mode *adjusted_mode);
978
979/* fmt blocks */
980void avivo_program_fmt(struct drm_encoder *encoder);
981void dce3_program_fmt(struct drm_encoder *encoder);
982void dce4_program_fmt(struct drm_encoder *encoder);
983void dce8_program_fmt(struct drm_encoder *encoder);
984
985/* fbdev layer */
986int radeon_fbdev_init(struct radeon_device *rdev);
987void radeon_fbdev_fini(struct radeon_device *rdev);
988void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
989bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
990void radeon_fbdev_restore_mode(struct radeon_device *rdev);
991
992void radeon_fb_output_poll_changed(struct radeon_device *rdev);
993
994void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id);
995
996void radeon_fb_add_connector(struct radeon_device *rdev, struct drm_connector *connector);
997void radeon_fb_remove_connector(struct radeon_device *rdev, struct drm_connector *connector);
998
999void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
1000
1001int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);
1002
1003/* mst */
1004int radeon_dp_mst_init(struct radeon_connector *radeon_connector);
1005int radeon_dp_mst_probe(struct radeon_connector *radeon_connector);
1006int radeon_dp_mst_check_status(struct radeon_connector *radeon_connector);
1007int radeon_mst_debugfs_init(struct radeon_device *rdev);
1008void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode);
1009
1010void radeon_setup_mst_connector(struct drm_device *dev);
1011
1012int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx);
1013void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx);
1014#endif