tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/*
2 * Broadcom SATA3 AHCI Controller Driver
3 *
4 * Copyright © 2009-2015 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/ahci_platform.h>
18#include <linux/compiler.h>
19#include <linux/device.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/io.h>
23#include <linux/kernel.h>
24#include <linux/libata.h>
25#include <linux/module.h>
26#include <linux/of.h>
27#include <linux/platform_device.h>
28#include <linux/string.h>
29
30#include "ahci.h"
31
32#define DRV_NAME "brcm-ahci"
33
34#define SATA_TOP_CTRL_VERSION 0x0
35#define SATA_TOP_CTRL_BUS_CTRL 0x4
36 #define MMIO_ENDIAN_SHIFT 0 /* CPU->AHCI */
37 #define DMADESC_ENDIAN_SHIFT 2 /* AHCI->DDR */
38 #define DMADATA_ENDIAN_SHIFT 4 /* AHCI->DDR */
39 #define PIODATA_ENDIAN_SHIFT 6
40 #define ENDIAN_SWAP_NONE 0
41 #define ENDIAN_SWAP_FULL 2
42 #define OVERRIDE_HWINIT BIT(16)
43#define SATA_TOP_CTRL_TP_CTRL 0x8
44#define SATA_TOP_CTRL_PHY_CTRL 0xc
45 #define SATA_TOP_CTRL_PHY_CTRL_1 0x0
46 #define SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE BIT(14)
47 #define SATA_TOP_CTRL_PHY_CTRL_2 0x4
48 #define SATA_TOP_CTRL_2_SW_RST_MDIOREG BIT(0)
49 #define SATA_TOP_CTRL_2_SW_RST_OOB BIT(1)
50 #define SATA_TOP_CTRL_2_SW_RST_RX BIT(2)
51 #define SATA_TOP_CTRL_2_SW_RST_TX BIT(3)
52 #define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET BIT(14)
53 #define SATA_TOP_CTRL_PHY_OFFS 0x8
54 #define SATA_TOP_MAX_PHYS 2
55
56#define SATA_FIRST_PORT_CTRL 0x700
57#define SATA_NEXT_PORT_CTRL_OFFSET 0x80
58#define SATA_PORT_PCTRL6(reg_base) (reg_base + 0x18)
59
60/* On big-endian MIPS, buses are reversed to big endian, so switch them back */
61#if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
62#define DATA_ENDIAN 2 /* AHCI->DDR inbound accesses */
63#define MMIO_ENDIAN 2 /* CPU->AHCI outbound accesses */
64#else
65#define DATA_ENDIAN 0
66#define MMIO_ENDIAN 0
67#endif
68
69#define BUS_CTRL_ENDIAN_CONF \
70 ((DATA_ENDIAN << DMADATA_ENDIAN_SHIFT) | \
71 (DATA_ENDIAN << DMADESC_ENDIAN_SHIFT) | \
72 (MMIO_ENDIAN << MMIO_ENDIAN_SHIFT))
73
74enum brcm_ahci_quirks {
75 BRCM_AHCI_QUIRK_NO_NCQ = BIT(0),
76 BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE = BIT(1),
77};
78
79struct brcm_ahci_priv {
80 struct device *dev;
81 void __iomem *top_ctrl;
82 u32 port_mask;
83 u32 quirks;
84};
85
86static const struct ata_port_info ahci_brcm_port_info = {
87 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
88 .link_flags = ATA_LFLAG_NO_DB_DELAY,
89 .pio_mask = ATA_PIO4,
90 .udma_mask = ATA_UDMA6,
91 .port_ops = &ahci_platform_ops,
92};
93
94static inline u32 brcm_sata_readreg(void __iomem *addr)
95{
96 /*
97 * MIPS endianness is configured by boot strap, which also reverses all
98 * bus endianness (i.e., big-endian CPU + big endian bus ==> native
99 * endian I/O).
100 *
101 * Other architectures (e.g., ARM) either do not support big endian, or
102 * else leave I/O in little endian mode.
103 */
104 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
105 return __raw_readl(addr);
106 else
107 return readl_relaxed(addr);
108}
109
110static inline void brcm_sata_writereg(u32 val, void __iomem *addr)
111{
112 /* See brcm_sata_readreg() comments */
113 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
114 __raw_writel(val, addr);
115 else
116 writel_relaxed(val, addr);
117}
118
119static void brcm_sata_alpm_init(struct ahci_host_priv *hpriv)
120{
121 struct brcm_ahci_priv *priv = hpriv->plat_data;
122 u32 bus_ctrl, port_ctrl, host_caps;
123 int i;
124
125 /* Enable support for ALPM */
126 bus_ctrl = brcm_sata_readreg(priv->top_ctrl +
127 SATA_TOP_CTRL_BUS_CTRL);
128 brcm_sata_writereg(bus_ctrl | OVERRIDE_HWINIT,
129 priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL);
130 host_caps = readl(hpriv->mmio + HOST_CAP);
131 writel(host_caps | HOST_CAP_ALPM, hpriv->mmio);
132 brcm_sata_writereg(bus_ctrl, priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL);
133
134 /*
135 * Adjust timeout to allow PLL sufficient time to lock while waking
136 * up from slumber mode.
137 */
138 for (i = 0, port_ctrl = SATA_FIRST_PORT_CTRL;
139 i < SATA_TOP_MAX_PHYS;
140 i++, port_ctrl += SATA_NEXT_PORT_CTRL_OFFSET) {
141 if (priv->port_mask & BIT(i))
142 writel(0xff1003fc,
143 hpriv->mmio + SATA_PORT_PCTRL6(port_ctrl));
144 }
145}
146
147static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
148{
149 void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
150 (port * SATA_TOP_CTRL_PHY_OFFS);
151 void __iomem *p;
152 u32 reg;
153
154 if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
155 return;
156
157 /* clear PHY_DEFAULT_POWER_STATE */
158 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
159 reg = brcm_sata_readreg(p);
160 reg &= ~SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
161 brcm_sata_writereg(reg, p);
162
163 /* reset the PHY digital logic */
164 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
165 reg = brcm_sata_readreg(p);
166 reg &= ~(SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB |
167 SATA_TOP_CTRL_2_SW_RST_RX);
168 reg |= SATA_TOP_CTRL_2_SW_RST_TX;
169 brcm_sata_writereg(reg, p);
170 reg = brcm_sata_readreg(p);
171 reg |= SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
172 brcm_sata_writereg(reg, p);
173 reg = brcm_sata_readreg(p);
174 reg &= ~SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
175 brcm_sata_writereg(reg, p);
176 (void)brcm_sata_readreg(p);
177}
178
179static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port)
180{
181 void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
182 (port * SATA_TOP_CTRL_PHY_OFFS);
183 void __iomem *p;
184 u32 reg;
185
186 if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
187 return;
188
189 /* power-off the PHY digital logic */
190 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
191 reg = brcm_sata_readreg(p);
192 reg |= (SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB |
193 SATA_TOP_CTRL_2_SW_RST_RX | SATA_TOP_CTRL_2_SW_RST_TX |
194 SATA_TOP_CTRL_2_PHY_GLOBAL_RESET);
195 brcm_sata_writereg(reg, p);
196
197 /* set PHY_DEFAULT_POWER_STATE */
198 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
199 reg = brcm_sata_readreg(p);
200 reg |= SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
201 brcm_sata_writereg(reg, p);
202}
203
204static void brcm_sata_phys_enable(struct brcm_ahci_priv *priv)
205{
206 int i;
207
208 for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
209 if (priv->port_mask & BIT(i))
210 brcm_sata_phy_enable(priv, i);
211}
212
213static void brcm_sata_phys_disable(struct brcm_ahci_priv *priv)
214{
215 int i;
216
217 for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
218 if (priv->port_mask & BIT(i))
219 brcm_sata_phy_disable(priv, i);
220}
221
222static u32 brcm_ahci_get_portmask(struct platform_device *pdev,
223 struct brcm_ahci_priv *priv)
224{
225 void __iomem *ahci;
226 struct resource *res;
227 u32 impl;
228
229 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ahci");
230 ahci = devm_ioremap_resource(&pdev->dev, res);
231 if (IS_ERR(ahci))
232 return 0;
233
234 impl = readl(ahci + HOST_PORTS_IMPL);
235
236 if (fls(impl) > SATA_TOP_MAX_PHYS)
237 dev_warn(priv->dev, "warning: more ports than PHYs (%#x)\n",
238 impl);
239 else if (!impl)
240 dev_info(priv->dev, "no ports found\n");
241
242 devm_iounmap(&pdev->dev, ahci);
243 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
244
245 return impl;
246}
247
248static void brcm_sata_init(struct brcm_ahci_priv *priv)
249{
250 /* Configure endianness */
251 brcm_sata_writereg(BUS_CTRL_ENDIAN_CONF,
252 priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL);
253}
254
255#ifdef CONFIG_PM_SLEEP
256static int brcm_ahci_suspend(struct device *dev)
257{
258 struct ata_host *host = dev_get_drvdata(dev);
259 struct ahci_host_priv *hpriv = host->private_data;
260 struct brcm_ahci_priv *priv = hpriv->plat_data;
261 int ret;
262
263 ret = ahci_platform_suspend(dev);
264 brcm_sata_phys_disable(priv);
265 return ret;
266}
267
268static int brcm_ahci_resume(struct device *dev)
269{
270 struct ata_host *host = dev_get_drvdata(dev);
271 struct ahci_host_priv *hpriv = host->private_data;
272 struct brcm_ahci_priv *priv = hpriv->plat_data;
273
274 brcm_sata_init(priv);
275 brcm_sata_phys_enable(priv);
276 brcm_sata_alpm_init(hpriv);
277 return ahci_platform_resume(dev);
278}
279#endif
280
281static struct scsi_host_template ahci_platform_sht = {
282 AHCI_SHT(DRV_NAME),
283};
284
285static int brcm_ahci_probe(struct platform_device *pdev)
286{
287 struct device *dev = &pdev->dev;
288 struct brcm_ahci_priv *priv;
289 struct ahci_host_priv *hpriv;
290 struct resource *res;
291 int ret;
292
293 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
294 if (!priv)
295 return -ENOMEM;
296 priv->dev = dev;
297
298 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "top-ctrl");
299 priv->top_ctrl = devm_ioremap_resource(dev, res);
300 if (IS_ERR(priv->top_ctrl))
301 return PTR_ERR(priv->top_ctrl);
302
303 if (of_device_is_compatible(dev->of_node, "brcm,bcm7425-ahci")) {
304 priv->quirks |= BRCM_AHCI_QUIRK_NO_NCQ;
305 priv->quirks |= BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE;
306 }
307
308 brcm_sata_init(priv);
309
310 priv->port_mask = brcm_ahci_get_portmask(pdev, priv);
311 if (!priv->port_mask)
312 return -ENODEV;
313
314 brcm_sata_phys_enable(priv);
315
316 hpriv = ahci_platform_get_resources(pdev);
317 if (IS_ERR(hpriv))
318 return PTR_ERR(hpriv);
319 hpriv->plat_data = priv;
320 hpriv->flags = AHCI_HFLAG_WAKE_BEFORE_STOP;
321
322 brcm_sata_alpm_init(hpriv);
323
324 ret = ahci_platform_enable_resources(hpriv);
325 if (ret)
326 return ret;
327
328 if (priv->quirks & BRCM_AHCI_QUIRK_NO_NCQ)
329 hpriv->flags |= AHCI_HFLAG_NO_NCQ;
330
331 ret = ahci_platform_init_host(pdev, hpriv, &ahci_brcm_port_info,
332 &ahci_platform_sht);
333 if (ret)
334 return ret;
335
336 dev_info(dev, "Broadcom AHCI SATA3 registered\n");
337
338 return 0;
339}
340
341static int brcm_ahci_remove(struct platform_device *pdev)
342{
343 struct ata_host *host = dev_get_drvdata(&pdev->dev);
344 struct ahci_host_priv *hpriv = host->private_data;
345 struct brcm_ahci_priv *priv = hpriv->plat_data;
346 int ret;
347
348 ret = ata_platform_remove_one(pdev);
349 if (ret)
350 return ret;
351
352 brcm_sata_phys_disable(priv);
353
354 return 0;
355}
356
357static const struct of_device_id ahci_of_match[] = {
358 {.compatible = "brcm,bcm7425-ahci"},
359 {.compatible = "brcm,bcm7445-ahci"},
360 {},
361};
362MODULE_DEVICE_TABLE(of, ahci_of_match);
363
364static SIMPLE_DEV_PM_OPS(ahci_brcm_pm_ops, brcm_ahci_suspend, brcm_ahci_resume);
365
366static struct platform_driver brcm_ahci_driver = {
367 .probe = brcm_ahci_probe,
368 .remove = brcm_ahci_remove,
369 .driver = {
370 .name = DRV_NAME,
371 .of_match_table = ahci_of_match,
372 .pm = &ahci_brcm_pm_ops,
373 },
374};
375module_platform_driver(brcm_ahci_driver);
376
377MODULE_DESCRIPTION("Broadcom SATA3 AHCI Controller Driver");
378MODULE_AUTHOR("Brian Norris");
379MODULE_LICENSE("GPL");
380MODULE_ALIAS("platform:sata-brcmstb");