Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
38#include <linux/mlx5/mlx5_ifc.h>
39
40#if defined(__LITTLE_ENDIAN)
41#define MLX5_SET_HOST_ENDIANNESS 0
42#elif defined(__BIG_ENDIAN)
43#define MLX5_SET_HOST_ENDIANNESS 0x80
44#else
45#error Host endianness not defined
46#endif
47
48/* helper macros */
49#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51#define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
52#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
53#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
54#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
55#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
56#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
57#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
58
59#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
60#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
61#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
62#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
63#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
64#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
65#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
66
67/* insert a value to a struct */
68#define MLX5_SET(typ, p, fld, v) do { \
69 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
70 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
71 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
72 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
73 << __mlx5_dw_bit_off(typ, fld))); \
74} while (0)
75
76#define MLX5_SET_TO_ONES(typ, p, fld) do { \
77 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
78 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
79 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
80 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
81 << __mlx5_dw_bit_off(typ, fld))); \
82} while (0)
83
84#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
85__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
86__mlx5_mask(typ, fld))
87
88#define MLX5_GET_PR(typ, p, fld) ({ \
89 u32 ___t = MLX5_GET(typ, p, fld); \
90 pr_debug(#fld " = 0x%x\n", ___t); \
91 ___t; \
92})
93
94#define MLX5_SET64(typ, p, fld, v) do { \
95 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
96 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
97 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
98} while (0)
99
100#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
101
102#define MLX5_GET64_PR(typ, p, fld) ({ \
103 u64 ___t = MLX5_GET64(typ, p, fld); \
104 pr_debug(#fld " = 0x%llx\n", ___t); \
105 ___t; \
106})
107
108enum {
109 MLX5_MAX_COMMANDS = 32,
110 MLX5_CMD_DATA_BLOCK_SIZE = 512,
111 MLX5_PCI_CMD_XPORT = 7,
112 MLX5_MKEY_BSF_OCTO_SIZE = 4,
113 MLX5_MAX_PSVS = 4,
114};
115
116enum {
117 MLX5_EXTENDED_UD_AV = 0x80000000,
118};
119
120enum {
121 MLX5_CQ_STATE_ARMED = 9,
122 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
123 MLX5_CQ_STATE_FIRED = 0xa,
124};
125
126enum {
127 MLX5_STAT_RATE_OFFSET = 5,
128};
129
130enum {
131 MLX5_INLINE_SEG = 0x80000000,
132};
133
134enum {
135 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
136};
137
138enum {
139 MLX5_MIN_PKEY_TABLE_SIZE = 128,
140 MLX5_MAX_LOG_PKEY_TABLE = 5,
141};
142
143enum {
144 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
145};
146
147enum {
148 MLX5_PFAULT_SUBTYPE_WQE = 0,
149 MLX5_PFAULT_SUBTYPE_RDMA = 1,
150};
151
152enum {
153 MLX5_PERM_LOCAL_READ = 1 << 2,
154 MLX5_PERM_LOCAL_WRITE = 1 << 3,
155 MLX5_PERM_REMOTE_READ = 1 << 4,
156 MLX5_PERM_REMOTE_WRITE = 1 << 5,
157 MLX5_PERM_ATOMIC = 1 << 6,
158 MLX5_PERM_UMR_EN = 1 << 7,
159};
160
161enum {
162 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
163 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
164 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
165 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
166 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
167};
168
169enum {
170 MLX5_ACCESS_MODE_PA = 0,
171 MLX5_ACCESS_MODE_MTT = 1,
172 MLX5_ACCESS_MODE_KLM = 2
173};
174
175enum {
176 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
177 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
178 MLX5_MKEY_BSF_EN = 1 << 30,
179 MLX5_MKEY_LEN64 = 1 << 31,
180};
181
182enum {
183 MLX5_EN_RD = (u64)1,
184 MLX5_EN_WR = (u64)2
185};
186
187enum {
188 MLX5_BF_REGS_PER_PAGE = 4,
189 MLX5_MAX_UAR_PAGES = 1 << 8,
190 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
191 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
192};
193
194enum {
195 MLX5_MKEY_MASK_LEN = 1ull << 0,
196 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
197 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
198 MLX5_MKEY_MASK_PD = 1ull << 7,
199 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
200 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
201 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
202 MLX5_MKEY_MASK_KEY = 1ull << 13,
203 MLX5_MKEY_MASK_QPN = 1ull << 14,
204 MLX5_MKEY_MASK_LR = 1ull << 17,
205 MLX5_MKEY_MASK_LW = 1ull << 18,
206 MLX5_MKEY_MASK_RR = 1ull << 19,
207 MLX5_MKEY_MASK_RW = 1ull << 20,
208 MLX5_MKEY_MASK_A = 1ull << 21,
209 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
210 MLX5_MKEY_MASK_FREE = 1ull << 29,
211};
212
213enum {
214 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
215
216 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
217 MLX5_UMR_CHECK_FREE = (2 << 5),
218
219 MLX5_UMR_INLINE = (1 << 7),
220};
221
222#define MLX5_UMR_MTT_ALIGNMENT 0x40
223#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
224#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
225
226#define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
227
228enum {
229 MLX5_EVENT_QUEUE_TYPE_QP = 0,
230 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
231 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
232};
233
234enum mlx5_event {
235 MLX5_EVENT_TYPE_COMP = 0x0,
236
237 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
238 MLX5_EVENT_TYPE_COMM_EST = 0x02,
239 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
240 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
241 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
242
243 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
244 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
245 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
246 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
247 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
248 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
249
250 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
251 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
252 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
253 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
254
255 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
256 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
257
258 MLX5_EVENT_TYPE_CMD = 0x0a,
259 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
260
261 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
262 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
263};
264
265enum {
266 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
267 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
268 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
269 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
270 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
271 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
272 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
273};
274
275enum {
276 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
277 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
278 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
279 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
280 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
281 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
282 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
283 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
284 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
285 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
286 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
287 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
288};
289
290enum {
291 MLX5_ROCE_VERSION_1 = 0,
292 MLX5_ROCE_VERSION_2 = 2,
293};
294
295enum {
296 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
297 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
298};
299
300enum {
301 MLX5_ROCE_L3_TYPE_IPV4 = 0,
302 MLX5_ROCE_L3_TYPE_IPV6 = 1,
303};
304
305enum {
306 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
307 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
308};
309
310enum {
311 MLX5_OPCODE_NOP = 0x00,
312 MLX5_OPCODE_SEND_INVAL = 0x01,
313 MLX5_OPCODE_RDMA_WRITE = 0x08,
314 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
315 MLX5_OPCODE_SEND = 0x0a,
316 MLX5_OPCODE_SEND_IMM = 0x0b,
317 MLX5_OPCODE_LSO = 0x0e,
318 MLX5_OPCODE_RDMA_READ = 0x10,
319 MLX5_OPCODE_ATOMIC_CS = 0x11,
320 MLX5_OPCODE_ATOMIC_FA = 0x12,
321 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
322 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
323 MLX5_OPCODE_BIND_MW = 0x18,
324 MLX5_OPCODE_CONFIG_CMD = 0x1f,
325
326 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
327 MLX5_RECV_OPCODE_SEND = 0x01,
328 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
329 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
330
331 MLX5_CQE_OPCODE_ERROR = 0x1e,
332 MLX5_CQE_OPCODE_RESIZE = 0x16,
333
334 MLX5_OPCODE_SET_PSV = 0x20,
335 MLX5_OPCODE_GET_PSV = 0x21,
336 MLX5_OPCODE_CHECK_PSV = 0x22,
337 MLX5_OPCODE_RGET_PSV = 0x26,
338 MLX5_OPCODE_RCHECK_PSV = 0x27,
339
340 MLX5_OPCODE_UMR = 0x25,
341
342};
343
344enum {
345 MLX5_SET_PORT_RESET_QKEY = 0,
346 MLX5_SET_PORT_GUID0 = 16,
347 MLX5_SET_PORT_NODE_GUID = 17,
348 MLX5_SET_PORT_SYS_GUID = 18,
349 MLX5_SET_PORT_GID_TABLE = 19,
350 MLX5_SET_PORT_PKEY_TABLE = 20,
351};
352
353enum {
354 MLX5_MAX_PAGE_SHIFT = 31
355};
356
357enum {
358 MLX5_ADAPTER_PAGE_SHIFT = 12,
359 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
360};
361
362enum {
363 MLX5_CAP_OFF_CMDIF_CSUM = 46,
364};
365
366struct mlx5_inbox_hdr {
367 __be16 opcode;
368 u8 rsvd[4];
369 __be16 opmod;
370};
371
372struct mlx5_outbox_hdr {
373 u8 status;
374 u8 rsvd[3];
375 __be32 syndrome;
376};
377
378struct mlx5_cmd_query_adapter_mbox_in {
379 struct mlx5_inbox_hdr hdr;
380 u8 rsvd[8];
381};
382
383struct mlx5_cmd_query_adapter_mbox_out {
384 struct mlx5_outbox_hdr hdr;
385 u8 rsvd0[24];
386 u8 intapin;
387 u8 rsvd1[13];
388 __be16 vsd_vendor_id;
389 u8 vsd[208];
390 u8 vsd_psid[16];
391};
392
393enum mlx5_odp_transport_cap_bits {
394 MLX5_ODP_SUPPORT_SEND = 1 << 31,
395 MLX5_ODP_SUPPORT_RECV = 1 << 30,
396 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
397 MLX5_ODP_SUPPORT_READ = 1 << 28,
398};
399
400struct mlx5_odp_caps {
401 char reserved[0x10];
402 struct {
403 __be32 rc_odp_caps;
404 __be32 uc_odp_caps;
405 __be32 ud_odp_caps;
406 } per_transport_caps;
407 char reserved2[0xe4];
408};
409
410struct mlx5_cmd_init_hca_mbox_in {
411 struct mlx5_inbox_hdr hdr;
412 u8 rsvd0[2];
413 __be16 profile;
414 u8 rsvd1[4];
415};
416
417struct mlx5_cmd_init_hca_mbox_out {
418 struct mlx5_outbox_hdr hdr;
419 u8 rsvd[8];
420};
421
422struct mlx5_cmd_teardown_hca_mbox_in {
423 struct mlx5_inbox_hdr hdr;
424 u8 rsvd0[2];
425 __be16 profile;
426 u8 rsvd1[4];
427};
428
429struct mlx5_cmd_teardown_hca_mbox_out {
430 struct mlx5_outbox_hdr hdr;
431 u8 rsvd[8];
432};
433
434struct mlx5_cmd_layout {
435 u8 type;
436 u8 rsvd0[3];
437 __be32 inlen;
438 __be64 in_ptr;
439 __be32 in[4];
440 __be32 out[4];
441 __be64 out_ptr;
442 __be32 outlen;
443 u8 token;
444 u8 sig;
445 u8 rsvd1;
446 u8 status_own;
447};
448
449
450struct health_buffer {
451 __be32 assert_var[5];
452 __be32 rsvd0[3];
453 __be32 assert_exit_ptr;
454 __be32 assert_callra;
455 __be32 rsvd1[2];
456 __be32 fw_ver;
457 __be32 hw_id;
458 __be32 rsvd2;
459 u8 irisc_index;
460 u8 synd;
461 __be16 ext_synd;
462};
463
464struct mlx5_init_seg {
465 __be32 fw_rev;
466 __be32 cmdif_rev_fw_sub;
467 __be32 rsvd0[2];
468 __be32 cmdq_addr_h;
469 __be32 cmdq_addr_l_sz;
470 __be32 cmd_dbell;
471 __be32 rsvd1[120];
472 __be32 initializing;
473 struct health_buffer health;
474 __be32 rsvd2[880];
475 __be32 internal_timer_h;
476 __be32 internal_timer_l;
477 __be32 rsvd3[2];
478 __be32 health_counter;
479 __be32 rsvd4[1019];
480 __be64 ieee1588_clk;
481 __be32 ieee1588_clk_type;
482 __be32 clr_intx;
483};
484
485struct mlx5_eqe_comp {
486 __be32 reserved[6];
487 __be32 cqn;
488};
489
490struct mlx5_eqe_qp_srq {
491 __be32 reserved1[5];
492 u8 type;
493 u8 reserved2[3];
494 __be32 qp_srq_n;
495};
496
497struct mlx5_eqe_cq_err {
498 __be32 cqn;
499 u8 reserved1[7];
500 u8 syndrome;
501};
502
503struct mlx5_eqe_port_state {
504 u8 reserved0[8];
505 u8 port;
506};
507
508struct mlx5_eqe_gpio {
509 __be32 reserved0[2];
510 __be64 gpio_event;
511};
512
513struct mlx5_eqe_congestion {
514 u8 type;
515 u8 rsvd0;
516 u8 congestion_level;
517};
518
519struct mlx5_eqe_stall_vl {
520 u8 rsvd0[3];
521 u8 port_vl;
522};
523
524struct mlx5_eqe_cmd {
525 __be32 vector;
526 __be32 rsvd[6];
527};
528
529struct mlx5_eqe_page_req {
530 u8 rsvd0[2];
531 __be16 func_id;
532 __be32 num_pages;
533 __be32 rsvd1[5];
534};
535
536struct mlx5_eqe_page_fault {
537 __be32 bytes_committed;
538 union {
539 struct {
540 u16 reserved1;
541 __be16 wqe_index;
542 u16 reserved2;
543 __be16 packet_length;
544 u8 reserved3[12];
545 } __packed wqe;
546 struct {
547 __be32 r_key;
548 u16 reserved1;
549 __be16 packet_length;
550 __be32 rdma_op_len;
551 __be64 rdma_va;
552 } __packed rdma;
553 } __packed;
554 __be32 flags_qpn;
555} __packed;
556
557struct mlx5_eqe_vport_change {
558 u8 rsvd0[2];
559 __be16 vport_num;
560 __be32 rsvd1[6];
561} __packed;
562
563union ev_data {
564 __be32 raw[7];
565 struct mlx5_eqe_cmd cmd;
566 struct mlx5_eqe_comp comp;
567 struct mlx5_eqe_qp_srq qp_srq;
568 struct mlx5_eqe_cq_err cq_err;
569 struct mlx5_eqe_port_state port;
570 struct mlx5_eqe_gpio gpio;
571 struct mlx5_eqe_congestion cong;
572 struct mlx5_eqe_stall_vl stall_vl;
573 struct mlx5_eqe_page_req req_pages;
574 struct mlx5_eqe_page_fault page_fault;
575 struct mlx5_eqe_vport_change vport_change;
576} __packed;
577
578struct mlx5_eqe {
579 u8 rsvd0;
580 u8 type;
581 u8 rsvd1;
582 u8 sub_type;
583 __be32 rsvd2[7];
584 union ev_data data;
585 __be16 rsvd3;
586 u8 signature;
587 u8 owner;
588} __packed;
589
590struct mlx5_cmd_prot_block {
591 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
592 u8 rsvd0[48];
593 __be64 next;
594 __be32 block_num;
595 u8 rsvd1;
596 u8 token;
597 u8 ctrl_sig;
598 u8 sig;
599};
600
601enum {
602 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
603};
604
605struct mlx5_err_cqe {
606 u8 rsvd0[32];
607 __be32 srqn;
608 u8 rsvd1[18];
609 u8 vendor_err_synd;
610 u8 syndrome;
611 __be32 s_wqe_opcode_qpn;
612 __be16 wqe_counter;
613 u8 signature;
614 u8 op_own;
615};
616
617struct mlx5_cqe64 {
618 u8 rsvd0[4];
619 u8 lro_tcppsh_abort_dupack;
620 u8 lro_min_ttl;
621 __be16 lro_tcp_win;
622 __be32 lro_ack_seq_num;
623 __be32 rss_hash_result;
624 u8 rss_hash_type;
625 u8 ml_path;
626 u8 rsvd20[2];
627 __be16 check_sum;
628 __be16 slid;
629 __be32 flags_rqpn;
630 u8 hds_ip_ext;
631 u8 l4_hdr_type_etc;
632 __be16 vlan_info;
633 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
634 __be32 imm_inval_pkey;
635 u8 rsvd40[4];
636 __be32 byte_cnt;
637 __be32 timestamp_h;
638 __be32 timestamp_l;
639 __be32 sop_drop_qpn;
640 __be16 wqe_counter;
641 u8 signature;
642 u8 op_own;
643};
644
645static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
646{
647 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
648}
649
650static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
651{
652 return (cqe->l4_hdr_type_etc >> 4) & 0x7;
653}
654
655static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
656{
657 return !!(cqe->l4_hdr_type_etc & 0x1);
658}
659
660static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
661{
662 u32 hi, lo;
663
664 hi = be32_to_cpu(cqe->timestamp_h);
665 lo = be32_to_cpu(cqe->timestamp_l);
666
667 return (u64)lo | ((u64)hi << 32);
668}
669
670enum {
671 CQE_L4_HDR_TYPE_NONE = 0x0,
672 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
673 CQE_L4_HDR_TYPE_UDP = 0x2,
674 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
675 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
676};
677
678enum {
679 CQE_RSS_HTYPE_IP = 0x3 << 6,
680 CQE_RSS_HTYPE_L4 = 0x3 << 2,
681};
682
683enum {
684 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
685 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
686 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
687};
688
689enum {
690 CQE_L2_OK = 1 << 0,
691 CQE_L3_OK = 1 << 1,
692 CQE_L4_OK = 1 << 2,
693};
694
695struct mlx5_sig_err_cqe {
696 u8 rsvd0[16];
697 __be32 expected_trans_sig;
698 __be32 actual_trans_sig;
699 __be32 expected_reftag;
700 __be32 actual_reftag;
701 __be16 syndrome;
702 u8 rsvd22[2];
703 __be32 mkey;
704 __be64 err_offset;
705 u8 rsvd30[8];
706 __be32 qpn;
707 u8 rsvd38[2];
708 u8 signature;
709 u8 op_own;
710};
711
712struct mlx5_wqe_srq_next_seg {
713 u8 rsvd0[2];
714 __be16 next_wqe_index;
715 u8 signature;
716 u8 rsvd1[11];
717};
718
719union mlx5_ext_cqe {
720 struct ib_grh grh;
721 u8 inl[64];
722};
723
724struct mlx5_cqe128 {
725 union mlx5_ext_cqe inl_grh;
726 struct mlx5_cqe64 cqe64;
727};
728
729struct mlx5_srq_ctx {
730 u8 state_log_sz;
731 u8 rsvd0[3];
732 __be32 flags_xrcd;
733 __be32 pgoff_cqn;
734 u8 rsvd1[4];
735 u8 log_pg_sz;
736 u8 rsvd2[7];
737 __be32 pd;
738 __be16 lwm;
739 __be16 wqe_cnt;
740 u8 rsvd3[8];
741 __be64 db_record;
742};
743
744struct mlx5_create_srq_mbox_in {
745 struct mlx5_inbox_hdr hdr;
746 __be32 input_srqn;
747 u8 rsvd0[4];
748 struct mlx5_srq_ctx ctx;
749 u8 rsvd1[208];
750 __be64 pas[0];
751};
752
753struct mlx5_create_srq_mbox_out {
754 struct mlx5_outbox_hdr hdr;
755 __be32 srqn;
756 u8 rsvd[4];
757};
758
759struct mlx5_destroy_srq_mbox_in {
760 struct mlx5_inbox_hdr hdr;
761 __be32 srqn;
762 u8 rsvd[4];
763};
764
765struct mlx5_destroy_srq_mbox_out {
766 struct mlx5_outbox_hdr hdr;
767 u8 rsvd[8];
768};
769
770struct mlx5_query_srq_mbox_in {
771 struct mlx5_inbox_hdr hdr;
772 __be32 srqn;
773 u8 rsvd0[4];
774};
775
776struct mlx5_query_srq_mbox_out {
777 struct mlx5_outbox_hdr hdr;
778 u8 rsvd0[8];
779 struct mlx5_srq_ctx ctx;
780 u8 rsvd1[32];
781 __be64 pas[0];
782};
783
784struct mlx5_arm_srq_mbox_in {
785 struct mlx5_inbox_hdr hdr;
786 __be32 srqn;
787 __be16 rsvd;
788 __be16 lwm;
789};
790
791struct mlx5_arm_srq_mbox_out {
792 struct mlx5_outbox_hdr hdr;
793 u8 rsvd[8];
794};
795
796struct mlx5_cq_context {
797 u8 status;
798 u8 cqe_sz_flags;
799 u8 st;
800 u8 rsvd3;
801 u8 rsvd4[6];
802 __be16 page_offset;
803 __be32 log_sz_usr_page;
804 __be16 cq_period;
805 __be16 cq_max_count;
806 __be16 rsvd20;
807 __be16 c_eqn;
808 u8 log_pg_sz;
809 u8 rsvd25[7];
810 __be32 last_notified_index;
811 __be32 solicit_producer_index;
812 __be32 consumer_counter;
813 __be32 producer_counter;
814 u8 rsvd48[8];
815 __be64 db_record_addr;
816};
817
818struct mlx5_create_cq_mbox_in {
819 struct mlx5_inbox_hdr hdr;
820 __be32 input_cqn;
821 u8 rsvdx[4];
822 struct mlx5_cq_context ctx;
823 u8 rsvd6[192];
824 __be64 pas[0];
825};
826
827struct mlx5_create_cq_mbox_out {
828 struct mlx5_outbox_hdr hdr;
829 __be32 cqn;
830 u8 rsvd0[4];
831};
832
833struct mlx5_destroy_cq_mbox_in {
834 struct mlx5_inbox_hdr hdr;
835 __be32 cqn;
836 u8 rsvd0[4];
837};
838
839struct mlx5_destroy_cq_mbox_out {
840 struct mlx5_outbox_hdr hdr;
841 u8 rsvd0[8];
842};
843
844struct mlx5_query_cq_mbox_in {
845 struct mlx5_inbox_hdr hdr;
846 __be32 cqn;
847 u8 rsvd0[4];
848};
849
850struct mlx5_query_cq_mbox_out {
851 struct mlx5_outbox_hdr hdr;
852 u8 rsvd0[8];
853 struct mlx5_cq_context ctx;
854 u8 rsvd6[16];
855 __be64 pas[0];
856};
857
858struct mlx5_modify_cq_mbox_in {
859 struct mlx5_inbox_hdr hdr;
860 __be32 cqn;
861 __be32 field_select;
862 struct mlx5_cq_context ctx;
863 u8 rsvd[192];
864 __be64 pas[0];
865};
866
867struct mlx5_modify_cq_mbox_out {
868 struct mlx5_outbox_hdr hdr;
869 u8 rsvd[8];
870};
871
872struct mlx5_enable_hca_mbox_in {
873 struct mlx5_inbox_hdr hdr;
874 u8 rsvd[8];
875};
876
877struct mlx5_enable_hca_mbox_out {
878 struct mlx5_outbox_hdr hdr;
879 u8 rsvd[8];
880};
881
882struct mlx5_disable_hca_mbox_in {
883 struct mlx5_inbox_hdr hdr;
884 u8 rsvd[8];
885};
886
887struct mlx5_disable_hca_mbox_out {
888 struct mlx5_outbox_hdr hdr;
889 u8 rsvd[8];
890};
891
892struct mlx5_eq_context {
893 u8 status;
894 u8 ec_oi;
895 u8 st;
896 u8 rsvd2[7];
897 __be16 page_pffset;
898 __be32 log_sz_usr_page;
899 u8 rsvd3[7];
900 u8 intr;
901 u8 log_page_size;
902 u8 rsvd4[15];
903 __be32 consumer_counter;
904 __be32 produser_counter;
905 u8 rsvd5[16];
906};
907
908struct mlx5_create_eq_mbox_in {
909 struct mlx5_inbox_hdr hdr;
910 u8 rsvd0[3];
911 u8 input_eqn;
912 u8 rsvd1[4];
913 struct mlx5_eq_context ctx;
914 u8 rsvd2[8];
915 __be64 events_mask;
916 u8 rsvd3[176];
917 __be64 pas[0];
918};
919
920struct mlx5_create_eq_mbox_out {
921 struct mlx5_outbox_hdr hdr;
922 u8 rsvd0[3];
923 u8 eq_number;
924 u8 rsvd1[4];
925};
926
927struct mlx5_destroy_eq_mbox_in {
928 struct mlx5_inbox_hdr hdr;
929 u8 rsvd0[3];
930 u8 eqn;
931 u8 rsvd1[4];
932};
933
934struct mlx5_destroy_eq_mbox_out {
935 struct mlx5_outbox_hdr hdr;
936 u8 rsvd[8];
937};
938
939struct mlx5_map_eq_mbox_in {
940 struct mlx5_inbox_hdr hdr;
941 __be64 mask;
942 u8 mu;
943 u8 rsvd0[2];
944 u8 eqn;
945 u8 rsvd1[24];
946};
947
948struct mlx5_map_eq_mbox_out {
949 struct mlx5_outbox_hdr hdr;
950 u8 rsvd[8];
951};
952
953struct mlx5_query_eq_mbox_in {
954 struct mlx5_inbox_hdr hdr;
955 u8 rsvd0[3];
956 u8 eqn;
957 u8 rsvd1[4];
958};
959
960struct mlx5_query_eq_mbox_out {
961 struct mlx5_outbox_hdr hdr;
962 u8 rsvd[8];
963 struct mlx5_eq_context ctx;
964};
965
966enum {
967 MLX5_MKEY_STATUS_FREE = 1 << 6,
968};
969
970struct mlx5_mkey_seg {
971 /* This is a two bit field occupying bits 31-30.
972 * bit 31 is always 0,
973 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
974 */
975 u8 status;
976 u8 pcie_control;
977 u8 flags;
978 u8 version;
979 __be32 qpn_mkey7_0;
980 u8 rsvd1[4];
981 __be32 flags_pd;
982 __be64 start_addr;
983 __be64 len;
984 __be32 bsfs_octo_size;
985 u8 rsvd2[16];
986 __be32 xlt_oct_size;
987 u8 rsvd3[3];
988 u8 log2_page_size;
989 u8 rsvd4[4];
990};
991
992struct mlx5_query_special_ctxs_mbox_in {
993 struct mlx5_inbox_hdr hdr;
994 u8 rsvd[8];
995};
996
997struct mlx5_query_special_ctxs_mbox_out {
998 struct mlx5_outbox_hdr hdr;
999 __be32 dump_fill_mkey;
1000 __be32 reserved_lkey;
1001};
1002
1003struct mlx5_create_mkey_mbox_in {
1004 struct mlx5_inbox_hdr hdr;
1005 __be32 input_mkey_index;
1006 __be32 flags;
1007 struct mlx5_mkey_seg seg;
1008 u8 rsvd1[16];
1009 __be32 xlat_oct_act_size;
1010 __be32 rsvd2;
1011 u8 rsvd3[168];
1012 __be64 pas[0];
1013};
1014
1015struct mlx5_create_mkey_mbox_out {
1016 struct mlx5_outbox_hdr hdr;
1017 __be32 mkey;
1018 u8 rsvd[4];
1019};
1020
1021struct mlx5_destroy_mkey_mbox_in {
1022 struct mlx5_inbox_hdr hdr;
1023 __be32 mkey;
1024 u8 rsvd[4];
1025};
1026
1027struct mlx5_destroy_mkey_mbox_out {
1028 struct mlx5_outbox_hdr hdr;
1029 u8 rsvd[8];
1030};
1031
1032struct mlx5_query_mkey_mbox_in {
1033 struct mlx5_inbox_hdr hdr;
1034 __be32 mkey;
1035};
1036
1037struct mlx5_query_mkey_mbox_out {
1038 struct mlx5_outbox_hdr hdr;
1039 __be64 pas[0];
1040};
1041
1042struct mlx5_modify_mkey_mbox_in {
1043 struct mlx5_inbox_hdr hdr;
1044 __be32 mkey;
1045 __be64 pas[0];
1046};
1047
1048struct mlx5_modify_mkey_mbox_out {
1049 struct mlx5_outbox_hdr hdr;
1050 u8 rsvd[8];
1051};
1052
1053struct mlx5_dump_mkey_mbox_in {
1054 struct mlx5_inbox_hdr hdr;
1055};
1056
1057struct mlx5_dump_mkey_mbox_out {
1058 struct mlx5_outbox_hdr hdr;
1059 __be32 mkey;
1060};
1061
1062struct mlx5_mad_ifc_mbox_in {
1063 struct mlx5_inbox_hdr hdr;
1064 __be16 remote_lid;
1065 u8 rsvd0;
1066 u8 port;
1067 u8 rsvd1[4];
1068 u8 data[256];
1069};
1070
1071struct mlx5_mad_ifc_mbox_out {
1072 struct mlx5_outbox_hdr hdr;
1073 u8 rsvd[8];
1074 u8 data[256];
1075};
1076
1077struct mlx5_access_reg_mbox_in {
1078 struct mlx5_inbox_hdr hdr;
1079 u8 rsvd0[2];
1080 __be16 register_id;
1081 __be32 arg;
1082 __be32 data[0];
1083};
1084
1085struct mlx5_access_reg_mbox_out {
1086 struct mlx5_outbox_hdr hdr;
1087 u8 rsvd[8];
1088 __be32 data[0];
1089};
1090
1091#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
1092
1093enum {
1094 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
1095};
1096
1097struct mlx5_allocate_psv_in {
1098 struct mlx5_inbox_hdr hdr;
1099 __be32 npsv_pd;
1100 __be32 rsvd_psv0;
1101};
1102
1103struct mlx5_allocate_psv_out {
1104 struct mlx5_outbox_hdr hdr;
1105 u8 rsvd[8];
1106 __be32 psv_idx[4];
1107};
1108
1109struct mlx5_destroy_psv_in {
1110 struct mlx5_inbox_hdr hdr;
1111 __be32 psv_number;
1112 u8 rsvd[4];
1113};
1114
1115struct mlx5_destroy_psv_out {
1116 struct mlx5_outbox_hdr hdr;
1117 u8 rsvd[8];
1118};
1119
1120#define MLX5_CMD_OP_MAX 0x920
1121
1122enum {
1123 VPORT_STATE_DOWN = 0x0,
1124 VPORT_STATE_UP = 0x1,
1125};
1126
1127enum {
1128 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0,
1129 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1,
1130 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2,
1131};
1132
1133enum {
1134 MLX5_L3_PROT_TYPE_IPV4 = 0,
1135 MLX5_L3_PROT_TYPE_IPV6 = 1,
1136};
1137
1138enum {
1139 MLX5_L4_PROT_TYPE_TCP = 0,
1140 MLX5_L4_PROT_TYPE_UDP = 1,
1141};
1142
1143enum {
1144 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
1145 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
1146 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
1147 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
1148 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
1149};
1150
1151enum {
1152 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
1153 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
1154 MLX5_MATCH_INNER_HEADERS = 1 << 2,
1155
1156};
1157
1158enum {
1159 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
1160 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
1161};
1162
1163enum {
1164 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
1165 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
1166 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
1167};
1168
1169enum mlx5_list_type {
1170 MLX5_NVPRT_LIST_TYPE_UC = 0x0,
1171 MLX5_NVPRT_LIST_TYPE_MC = 0x1,
1172 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
1173};
1174
1175enum {
1176 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1177 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
1178};
1179
1180/* MLX5 DEV CAPs */
1181
1182/* TODO: EAT.ME */
1183enum mlx5_cap_mode {
1184 HCA_CAP_OPMOD_GET_MAX = 0,
1185 HCA_CAP_OPMOD_GET_CUR = 1,
1186};
1187
1188enum mlx5_cap_type {
1189 MLX5_CAP_GENERAL = 0,
1190 MLX5_CAP_ETHERNET_OFFLOADS,
1191 MLX5_CAP_ODP,
1192 MLX5_CAP_ATOMIC,
1193 MLX5_CAP_ROCE,
1194 MLX5_CAP_IPOIB_OFFLOADS,
1195 MLX5_CAP_EOIB_OFFLOADS,
1196 MLX5_CAP_FLOW_TABLE,
1197 MLX5_CAP_ESWITCH_FLOW_TABLE,
1198 MLX5_CAP_ESWITCH,
1199 /* NUM OF CAP Types */
1200 MLX5_CAP_NUM
1201};
1202
1203/* GET Dev Caps macros */
1204#define MLX5_CAP_GEN(mdev, cap) \
1205 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1206
1207#define MLX5_CAP_GEN_MAX(mdev, cap) \
1208 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
1209
1210#define MLX5_CAP_ETH(mdev, cap) \
1211 MLX5_GET(per_protocol_networking_offload_caps,\
1212 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1213
1214#define MLX5_CAP_ETH_MAX(mdev, cap) \
1215 MLX5_GET(per_protocol_networking_offload_caps,\
1216 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1217
1218#define MLX5_CAP_ROCE(mdev, cap) \
1219 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
1220
1221#define MLX5_CAP_ROCE_MAX(mdev, cap) \
1222 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
1223
1224#define MLX5_CAP_ATOMIC(mdev, cap) \
1225 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
1226
1227#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1228 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
1229
1230#define MLX5_CAP_FLOWTABLE(mdev, cap) \
1231 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1232
1233#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1234 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1235
1236#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1237 MLX5_GET(flow_table_eswitch_cap, \
1238 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1239
1240#define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1241 MLX5_GET(flow_table_eswitch_cap, \
1242 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1243
1244#define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1245 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1246
1247#define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1248 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1249
1250#define MLX5_CAP_ESW(mdev, cap) \
1251 MLX5_GET(e_switch_cap, \
1252 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1253
1254#define MLX5_CAP_ESW_MAX(mdev, cap) \
1255 MLX5_GET(e_switch_cap, \
1256 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1257
1258#define MLX5_CAP_ODP(mdev, cap)\
1259 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1260
1261enum {
1262 MLX5_CMD_STAT_OK = 0x0,
1263 MLX5_CMD_STAT_INT_ERR = 0x1,
1264 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1265 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1266 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1267 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1268 MLX5_CMD_STAT_RES_BUSY = 0x6,
1269 MLX5_CMD_STAT_LIM_ERR = 0x8,
1270 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1271 MLX5_CMD_STAT_IX_ERR = 0xa,
1272 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1273 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1274 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1275 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1276 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1277 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1278};
1279
1280enum {
1281 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1282 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1283 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1284 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1285 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1286 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1287 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11
1288};
1289
1290static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1291{
1292 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1293 return 0;
1294 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1295}
1296
1297#define MLX5_BY_PASS_NUM_PRIOS 9
1298
1299#endif /* MLX5_DEVICE_H */