tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/*
2 * Renesas Clock Pulse Generator / Module Standby and Software Reset
3 *
4 * Copyright (C) 2015 Glider bvba
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11#ifndef __CLK_RENESAS_CPG_MSSR_H__
12#define __CLK_RENESAS_CPG_MSSR_H__
13
14 /*
15 * Definitions of CPG Core Clocks
16 *
17 * These include:
18 * - Clock outputs exported to DT
19 * - External input clocks
20 * - Internal CPG clocks
21 */
22
23struct cpg_core_clk {
24 /* Common */
25 const char *name;
26 unsigned int id;
27 unsigned int type;
28 /* Depending on type */
29 unsigned int parent; /* Core Clocks only */
30 unsigned int div;
31 unsigned int mult;
32 unsigned int offset;
33};
34
35enum clk_types {
36 /* Generic */
37 CLK_TYPE_IN, /* External Clock Input */
38 CLK_TYPE_FF, /* Fixed Factor Clock */
39 CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
40
41 /* Custom definitions start here */
42 CLK_TYPE_CUSTOM,
43};
44
45#define DEF_TYPE(_name, _id, _type...) \
46 { .name = _name, .id = _id, .type = _type }
47#define DEF_BASE(_name, _id, _type, _parent...) \
48 DEF_TYPE(_name, _id, _type, .parent = _parent)
49
50#define DEF_INPUT(_name, _id) \
51 DEF_TYPE(_name, _id, CLK_TYPE_IN)
52#define DEF_FIXED(_name, _id, _parent, _div, _mult) \
53 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
54#define DEF_DIV6P1(_name, _id, _parent, _offset) \
55 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
56
57
58 /*
59 * Definitions of Module Clocks
60 */
61
62struct mssr_mod_clk {
63 const char *name;
64 unsigned int id;
65 unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */
66};
67
68/* Convert from sparse base-100 to packed index space */
69#define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
70
71#define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x))
72
73#define DEF_MOD(_name, _mod, _parent...) \
74 { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
75
76
77struct device_node;
78
79 /**
80 * SoC-specific CPG/MSSR Description
81 *
82 * @core_clks: Array of Core Clock definitions
83 * @num_core_clks: Number of entries in core_clks[]
84 * @last_dt_core_clk: ID of the last Core Clock exported to DT
85 * @num_total_core_clks: Total number of Core Clocks (exported + internal)
86 *
87 * @mod_clks: Array of Module Clock definitions
88 * @num_mod_clks: Number of entries in mod_clks[]
89 * @num_hw_mod_clks: Number of Module Clocks supported by the hardware
90 *
91 * @crit_mod_clks: Array with Module Clock IDs of critical clocks that
92 * should not be disabled without a knowledgeable driver
93 * @num_crit_mod_clks: Number of entries in crit_mod_clks[]
94 *
95 * @core_pm_clks: Array with IDs of Core Clocks that are suitable for Power
96 * Management, in addition to Module Clocks
97 * @num_core_pm_clks: Number of entries in core_pm_clks[]
98 *
99 * @init: Optional callback to perform SoC-specific initialization
100 * @cpg_clk_register: Optional callback to handle special Core Clock types
101 */
102
103struct cpg_mssr_info {
104 /* Core Clocks */
105 const struct cpg_core_clk *core_clks;
106 unsigned int num_core_clks;
107 unsigned int last_dt_core_clk;
108 unsigned int num_total_core_clks;
109
110 /* Module Clocks */
111 const struct mssr_mod_clk *mod_clks;
112 unsigned int num_mod_clks;
113 unsigned int num_hw_mod_clks;
114
115 /* Critical Module Clocks that should not be disabled */
116 const unsigned int *crit_mod_clks;
117 unsigned int num_crit_mod_clks;
118
119 /* Core Clocks suitable for PM, in addition to the Module Clocks */
120 const unsigned int *core_pm_clks;
121 unsigned int num_core_pm_clks;
122
123 /* Callbacks */
124 int (*init)(struct device *dev);
125 struct clk *(*cpg_clk_register)(struct device *dev,
126 const struct cpg_core_clk *core,
127 const struct cpg_mssr_info *info,
128 struct clk **clks, void __iomem *base);
129};
130
131extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
132#endif