Linux kernel mirror (for testing)
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1/*
2 * include/asm-parisc/cache.h
3 */
4
5#ifndef __ARCH_PARISC_CACHE_H
6#define __ARCH_PARISC_CACHE_H
7
8
9/*
10 * PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors
11 * have 32-byte cachelines. The L1 length appears to be 16 bytes but this
12 * is not clearly documented.
13 */
14#define L1_CACHE_BYTES 16
15#define L1_CACHE_SHIFT 4
16
17#ifndef __ASSEMBLY__
18
19#define SMP_CACHE_BYTES L1_CACHE_BYTES
20
21#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
22
23#define __read_mostly __attribute__((__section__(".data..read_mostly")))
24
25void parisc_cache_init(void); /* initializes cache-flushing */
26void disable_sr_hashing_asm(int); /* low level support for above */
27void disable_sr_hashing(void); /* turns off space register hashing */
28void free_sid(unsigned long);
29unsigned long alloc_sid(void);
30
31struct seq_file;
32extern void show_cache_info(struct seq_file *m);
33
34extern int split_tlb;
35extern int dcache_stride;
36extern int icache_stride;
37extern struct pdc_cache_info cache_info;
38void parisc_setup_cache_timing(void);
39
40#define pdtlb(addr) asm volatile("pdtlb 0(%%sr1,%0)" : : "r" (addr));
41#define pitlb(addr) asm volatile("pitlb 0(%%sr1,%0)" : : "r" (addr));
42#define pdtlb_kernel(addr) asm volatile("pdtlb 0(%0)" : : "r" (addr));
43
44#endif /* ! __ASSEMBLY__ */
45
46/* Classes of processor wrt: disabling space register hashing */
47
48#define SRHASH_PCXST 0 /* pcxs, pcxt, pcxt_ */
49#define SRHASH_PCXL 1 /* pcxl */
50#define SRHASH_PA20 2 /* pcxu, pcxu_, pcxw, pcxw_ */
51
52#endif